Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis

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Clement McDaniel
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1 August 17, 2006 Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

technical needs concerning semiconductor technology, please call Sales at Chipworks.

2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Low-Voltage Transistors 3.7 Peripheral High-Voltage Transistors 3.8 Flash Array Transistors and Poly 3.9 Isolation 3.10 Wells and Substrate 4 Memory Cell Analysis 4.1 Plan-View Analysis 4.2 Cross-Sectional Analysis Parallel to Bit Line 4.3 Cross-Sectional Analysis Parallel to Word Line 5 Materials Analysis 5.1 TEM-EDS Analysis of Dielectrics 5.2 TEM-EDS Analysis of Metals

5 Vias and Contacts 3.6 Peripheral Low-Voltage Transistors 3.7 Peripheral High-Voltage Transistors 3.8 Flash Array Transistors and Poly 3.9 Isolation 3.

3 Structural Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions Report Evaluation

4 Overview Overview 1.1 List of Figures 2 Package and Die Analysis Package Top Photograph Package Bottom Photograph Plan-View Package X-Ray Die Photograph Die Markings Die Corner Die Corner Die Corner Die Corner Bond Pads 3 Process Analysis General Device Structure Die Edge Overview Die Seal Structure Detail of Poly Stack at Die Seal Bond Pad Overview Bond Pad Edge Bond Pad Center Passivation Overview Passivation 2 TEM IMD IMD 1-1 TEM PMD Minimum Pitch Metal Metal 2 Profile TEM Minimum Pitch Metal Minimum Pitch Metal 1 TEM Detail of Metal 1 Barrier TEM Minimum Pitch Vias Poly 4 Contact Bit Line Contact Detail of Metal 1 to Poly 4 Contact Poly 3 Contact Source Line Contact Detail of Metal 1 to Poly 3 Contact

5 Overview Minimum Pitch Contacts to Poly Contact to Poly Minimum Pitch Contacts to N + Diffusion Contacts to P + Diffusion Minimum Gate Length Peripheral NMOS Transistors Detail of Minimum Gate Length Peripheral NMOS Transistors Plan-View of Peripheral Transistor Layout Peripheral Transistor Gate Gate Width Direction Peripheral HVNMOS Transistor Detail of Peripheral HVNMOS Transistor S/D Contact Peripheral HVPMOS Transistor Detail of Peripheral HVPMOS Transistor S/D Contact HVMOS Transistor TEM Detail of HVMOS Transistor TEM TEM Lattice Image Minimum Pitch Floating Gate Array Transistors Minimum Pitch Floating Transistors on STI Source Line Select Transistor and Storage Transistors TEM Detail of Floating Gate Stroage Transistor TEM ONO Interpoly Dielectric TEM ONO at Gate Stack Edge TEM Storage Transistor Gate Dielectric TEM Storage Transistor (Gate Width Direction) TEM Stacked Poly Over STI Minimum Width STI STI/Gate Oxide Interface TEM Array N-Well SCM of Array Wells SRP Profile of Array Well Structure SRP Profile of Periphery P-Well 4 Memory Cell Analysis Die Photograph Die Deprocessed to Poly Plan-View Word Line Drivers Plan-View Detail of Word Line Drivers and Edge of Array Plan-View Page Buffer/Write Drivers Plan-View Detail of Write Drivers and Edge of Array

1 Peripheral HVNMOS Transistor 3.7.2 Detail of Peripheral HVNMOS Transistor S/D Contact 3.7.3 Peripheral HVPMOS Transistor 3.7.4 Detail of Peripheral HVPMOS Transistor S/D Contact 3.7.5 HVMOS Transistor TEM 3.

6 Overview Plan-View Detail Edge of Array Plan-View Detail of Word Lines Flash Array Parallel to Bit Line Bit Line Contact to Flash Array TEM Detail of Floating Gate Storage Transistors TEM Floating Gates Detail of Floating Gates Bit Line Select Line Source Line Between Blocks 5 Materials Analysis TEM-EDS Spectrum of Passivation TEM-EDS Spectrum of Passivation TEM-EDS Spectrum of Passivation 1 (Metal 2 ARC) TEM-EDS Spectrum of ILD TEM-EDS Spectrum of ILD TEM-EDS Spectrum of ILD 1-1 (Metal 1 ARC) TEM-EDS Spectrum of PMD TEM-EDS Spectrum of PMD TEM-EDS Spectrum of Sidewall Spacer TEM-EDS Spectrum of Metal 2 Adhesion Layer TEM-EDS Spectrum of Metal 1 Adhesion Layer TEM-EDS Spectrum of Gate Silicide 6 Critical Dimensions 1.2 List of Tables Device Summary Process Summary Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Polycide Dimensions

1.3 TEM-EDS Spectrum of Passivation 1 (Metal 2 ARC) 5.1.4 TEM-EDS Spectrum of ILD 1-3 5.1.5 TEM-EDS Spectrum of ILD 1-2 5.1.6 TEM-EDS Spectrum of ILD 1-1 (Metal 1 ARC) 5.1.7 TEM-EDS Spectrum of PMD 2 5.

7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in

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