Nanotechnologies for the Integrated Circuits

Transcription

1 Nanotechnologies for the Integrated Circuits September 23, 2015 Dr. Bertrand Cambou Professor of Practice NAU, Cybersecurity School of Informatics, Computing, and Cyber-Systems

2 Agenda The Market Silicon processing: the starting point Processor technology MEMS & Sensors Dynamic Random Access Memory Mass memory: Flash Important Research: new class of memories Nanotechnologies for Cybersecurity: PUFs

3 Semiconductor market: moderate growth

4 Semiconductor market: moderate growth

5 Silicon the perfect element 1- Abundant and cheap (28% earth composition by mass) 2- Mid column on periodic table; Oxidation state +/-4 3- Face Centered Cubic Crystal (Diamond) 4- Un-doped: Insulant MΩ s 5- Quantum Physics: Band gap 6- N/P-type doping (P, As, B) >>>Transistor 7- Strong Oxide SiO2 >>>MOS

6 Silicon the perfect element 1- Abundant and cheap (28% earth composition by mass) 2- Mid column on periodic table; Oxidation state +/-4 3- Face Centered Cubic Crystal (Diamond) 4- Un-doped: Insulant MΩ s 5- Quantum Physics: Band gap 6- N/P-type doping (P, As, B) >>>Transistor 7- Strong Oxide SiO2 >>>MOS Band gap analysis: Metal / Oxide / Silicon Conduction: Electrons - Band Gap: No conduction Metal Silicon Conduction: Holes +

7 CMOS Physics: Basics

8 CMOS Physics: Basics

9 Processing equipment & Materials Lithography: EUV Material: Bulk, Epitaxial deposition, SOI Doping: Ion Implantation Etching: Plasma Deposition: Plasma, MOCVD, Sputtering, Planarization: CMP Interconnect: W, CU, Ti, Co, Al, Ta. Dielectrics: Low k, High k, EUV: $200M

10 Processor Technology Moore and More

11 Processor Technology Cache memory Cache: SRAM Cell 70% of the footprint of a microprocessor is Cache

12 Processor Technology Trade off

13 Intense Research to shrink the CMOS

14 Analog devices MEMS Sensors Power devices: 1,000 V; 1,000 A RF devices: 1-100GHz MEMS (Micro-Electro-Mechanical-Systems) Gyroscope Accelerometer Sensors: Magnetic Sensors Electro-chemical Bio & Medical Sensors Opto-electronic Gyroscope Magnetic Sensor Chemical Sensor

15 DRAM Technology: a brutal business

16 DRAM: Nanotechnology + 3D 3D packaging 16 DRAMs + Logic

17 NAND Technology: Mass Memory solution

18 NAND : 3D stacks - 3bit/cell

19 SanDisk/Toshiba views: Emerging NV-Memories Emerging ReRAM

20 SanDisk/Toshiba views: ReRAM positioning

21 BREAKING NEWS FROM INTEL/MICRON July 27, 2015 Intel, Micron Launch "Bulk-Switching" ReRAM Peter ClarkeEETimes 7/28/2015 Intel Corp. and Micron Technology Inc. have launched a new class of non-volatile memory that they have called 3D Xpoint and which the companies said would be available as samples later this year for special customers. This is the introduction of the first new category of memory since the introduction of NAND flash in 1989! If the memory lives up to its promise of being up to 1000 times faster than NAND flash and 8 to 10 times denser than DRAM and therefore lower cost it could bring a major transformation in the electronics industry and to computer architectures for data centers and with possible application in solid-state drives. Durcan and Rob Crooke, general manager of the non-volatile memory group at Intel, revealed the memories on a 300mm wafer saying that while manufacturing would be done jointly the two companies would take 3D XPoint memories to market in 2016 developing products based on the technology separately. The prepared infographics suggest a resistive RAM with an in-built select diode allowing for a dense device structure. This would give it similarities to ReRAMs being developed by Crossbar Inc. (Santa Clara, Calif.). L-to-R. Rob Crooke, senior vice president at Intel and Mark Durcan, CEO of Micron Technology. 3D XPoint shown in diagramatic form with twoterminal select device stacked above two-terminal memory cell. So far one-bit per cell. Source: Intel. 300mm wafer bearing 3D XPoint 128Gbit memory ICs.

22 Various Resistive RAM candidates

23 Conductive Filament with dual states + ANODE ANODE ANODE S0LID ELECTROLYTE TiO2 Pt Pt FILAMENT CATHODE Pt - CATHODE CATHODE

24 Usage of Nanotechnology for Cyber-Security: Generation of PUF Integrated Circuits

25 Physically Unclonable Functions: Digital Fingerprint Terminal 3- Yes or No? PUF 2- PUF Response Server PUF component leveraging Nanotechnologies Exploit microscopic variations of nano-devices: generate digital fingerprint PUF Challenge: Initial print (or DNA ) of the component PUF Response: Print after activation Authentication: Secret identification of the hardware

26 PUF designed with Resistive RAM Memory based PUF Physical natural parameters subject to manufacturing variations can determine how to generate streams of 0s and 1s. This can create digital signatures exploitable as part of a PUF. Security with PUFs Challenges: generated with memories - stored in a server. Responses: generated by the same memory when activated. CRPs matching are checked by the server.

27 Experimental data: ReRAM samples Cu/TaOx/Pt resistive crossbar arrays have been fabricated on thermally oxidized Si wafers. The cross-section is shown (a), microscopic top-view of the array(b). Cu/TaO x /Pt switches rely on the formation/rupture of Conductive Filaments (CF) between the Cu and Pt electrodes. CF is being formed at Vset (c). When the voltage applied is swept positively, the current stays close to zero until V set is reached, at which a Cu CF is formed connecting the Cu and Pt electrodes, and the cell switches from a high resistive state, HRS (R off 100 MΩ) to a low state, LRS (R on 1,000 Ω); R off /R on With negative voltage is applied to LRS, CF ruptures at V reset and the cell switches to HRS state. The rupture is triggered by the current I reset = V reset /R on. For a set operation to logic state 1, the maximum voltage must be slightly larger than V set on each cell. The operation for writing a logic '0' requires a reset voltage slightly larger in magnitude than V reset on each cell.

28 PUF Challenge-Response generation from Vset Fig shows the cum. V set probability distribution within ReRAM arrays. Mean is µ=2.1 V and standard deviation is σ std =0.545 V. During Challenge generation: 0 [below µ ασ] X [µ ασ, µ+ασ] 1 [above µ+ασ] During Response generation: 0 [below threshold (ex: 2.1V)] 1 [above threshold (ex: 2.1V)] PUF Challenge-Response-Pair Matching CRP errors occur when a 0 (tested during Challenge generation <μ-ασ) is measured above 2.1V, or a 1 (tested during Challenge generation >μ+ασ) is measured below 2.1V. During authentication CRPs are tested, comparing the Responses generated by the memory against the Challenges that are provided by the server.

29 PUF CRP error rate To study the CRPs error rate, V set distribution was characterized for several individual ReRAM cells. The variation is plotted below: The statistical analysis based of these experimental data is presented below: The error rate during authentication of a PUF stream of N bits is calculated with Poisson equation. If P(n) is the probability to have n failures over N bits, p is the probability to have one CRP mismatch due to errors: P(n) = λ n /n! e -λ λ= pn The design point α=1.0 with a threshold of 1.9 volt has a CRPs error rate p=8ppm. Assuming N=128: P(0)= 99.2%; P(1)= 0.794%; P(2)= 30ppm; P(3) 0 With N=128, the probability that at least 126 CRPs are matching during authentication is almost certain

30 QUESTIONS?