3D Charge Trapping (CT) NAND Flash Yen-Hao Shih

Transcription

1 3D Charge Trapping (CT) NAND Flash Yen-Hao Shih Macronix International Co., Ltd. Hsinchu,, Taiwan 1

2 Outline Why Does NAND Go to 3D? Design a 3D NAND Flash Memory Challenges and Opportunities in 3D CT NAND Flash Memory Summary 2

3 Floating Gate (FG) Flash Memory ~10F 2 ~4F 2 Control gate ONO Floating gate Oxide Source Drain Single cell structure 1967 FG Transistor invented by D. Kahng and S. M. Sze (Bell Labs) 1984 NOR Flash invented by Fujio Masuoka (Toshiba) 1987 NAND Flash invented also by Fujio Masuoka (Toshiba) 3

4 Flash Memory Applications Flash Memory NAND (High Density for Data Storage) NOR (Fast for Code Access) 4

5 Scaling of FG NAND Memory (2D) 0.25um K. Shimizu, et al., (Toshiba) IEDM nm D.C. Kim, et al., (Samsung) IEDM /100 of area in 13 years (~ increase, or one node per 2 years) 25nm K. Prall, et al., (Micron) IEDM

6 Recent Scaling is Even Faster (at 1.5 Year/Gen) IMFT Samsung Toshiba Hynix Design Rule (nm) Q1 Q2 Q3 Q4 08 Q1 Q2 Q3 Q4 09 Q1 Q2 Q3 Q4 YEAR 10 Q1 Q2 Q3 Q4 11 Q1 Q2 Q3 Q4 6

7 2D Scaling Fulfills Demands and Creates New Applications Kinam Kim (Samsung), IMW

8 However, 2D Scaling is Running Out of Electrons ONO and Tunnel Oxide can t be scaled. For the same Vt window, Q = C * Vt, Source Control gate ONO Floating gate Tunnel Oxide Drain Single cell structure the electron number decreases as NAND cells are scaled down. Ne: Electron Number Electron number of FG GCR=0.7, Tono=15 nm, Tox=9nm GCR=0.65, Tono=13 nm, Tox=8nm Technology Node: F (nm) Number of electrons in FG device (~ 20 for 10nm device) 8

9 Impact of the Small Number of Electrons Number of electrons per logic level Node 45nm 32nm 22nm 16nm 11nm 8nm SLC (2 levels) MLC (4 levels) TLC (8 levels) QLC (16 levels) OLC (256 levels) Statistical fluctuation ~ N / N. N = 10 30%. 9

10 Solution is the 3D NAND Flash Stack up 2D devices Punch through multiple layers 2-layer TANOS NAND (Epitaxial Si growth) Samsung: IEDM layer BE-SONOS NAND (TFT device) Macronix: IEDM 2006 Bit-cost scalable (BiCS) TFT SONOS Toshiba: VLSI 2007 C.Y. Lu (Macronix), Semicon Taiwan

11 Difference between 3D Stacked NAND and BiCS H. Tanaka, et al., (TOSHIBA), VLSI 2007 Both types maintain the electron number at a reasonable level. 3D Stacked NAND can t further reduce cost when layer number >=4. BiCS uses only one critical contact drill hole for many layers so the bit cost is scalable, even when more than 16 layers are used. Later 3D NAND technologies have followed the BiCS concept. 11

12 Outline Why Does NAND Go to 3D? Design a 3D NAND Flash Memory Challenges and Opportunities in 3D CT NAND Flash Memory Summary 12

13 To Build 3D NAND, Start from 2D Conventional structure Charges stored in FG Charges in/out through the tunnel oxide. SONOS CT structure Charges stored in nitride Charges in/out through the tunnel dielectric (ONO here). 13

14 How NAND Flash Works? Asymmetric E-fields and Jg On/Off Ratio P/E Program E tunnel Erase E blocking High On/Off Ratio Jg (log scale) E blocking e - CG E tunnel Fast P/E Substrate e - CG IPD/ Blocking Oxide Tunnel Oxide Charge Storage IPD/ Blocking Oxide Charge Storage Tunnel Oxide h + FG: GCR design CT: high WF CG high-k blocking ONO tunnel dielectric Substrate Good Retention E-field 14

15 Glance over Various 2D CT Devices Theoretically the highest performance Best reported reliability, no new process H. T. Lue et al., (Macronix), TDMR

16 Retention of 2D BE-SONOS NAND 75nm BE-SONOS (Non-cut-ONO), P/E=1K Bit Counts 10 5 Before bake Disturbed EV 10min min 1100min min 7230min 10080min C Baking V T (V) PV H.T. Lue, et al., (Macronix), IEDM 2005 C. C. Hsieh, et al., (Macronix), IEDM 2010 Retention is excellent, and there is no single tail bit. The best reported CT reliability so far. BE-SONOS fundamentally solves traditional CT erase-retention dilemma. 16

17 CT is Easier than FG for 3D SungJin Whang, et al., (Hynix), IEDM 2010 C.H. Hung, et al., (Macronix), VLSI D CT devices are simpler in topology. 3D CT devices are smaller than 3D FG devices. CT is more process-friendly. 17

18 Various 3D NAND Architectures ~ Stacked NAND IEDM 2006 BiCS VLSI Symp P-BiCS VLSI Symp SONOS/TANOS Multi TFT IEDM 2006 TCAT VLSI Symp VSAT VLSI Symp VG TFT VLSI Symp Hybrid 3D IMW PNVG TFT VLSI Symp VG-NAND VLSI Symp FG Univ. of Tokyo S-SGT IEDM 2001 DC -SF IEDM Stacking Devices: High Process Cost BiCS Concept: Low Process Cost 18

19 In 2010, the Last of Several Crucial Elements Fell into Place for 3D NAND 2005, BE-SONOS, (Macronix) 2007, BiCS (Toshiba) 2009, Vertical Gate (VG) NAND (Samsung) 2010, 3D Decoding (Macronix) There are occasionally short windows in time when incredibly important things get invented that shape the lives of humans Steve Wozniak 19

20 Macronix s BE-SONOS 3D NAND 75nm half-pitch, 8-layer device is fabricated. Equivalent cell size = um 2 (MLC). Each device is a double-gate TFT BE-SONOS device. H. T. Lue et al., (Macronix), VLSI

21 3D Decoding Method A by Using Island Gate Devices H. T. Lue, et al., (Macronix), VLSI 2010 The method uses self-boosting scheme. Conventional WL, BL are grouped into planes. One additional SSL s device also grouped into planes. Three planes select a memory cell. 21

22 3D Decoding Method B by Using P-N Polysilicon Diode 1 st phase, decodes a NAND vertical plane, by conventional selfboosting. 2 nd phase, decodes a layer in the selected plane by source-side biasing. C.H. Hung et al., (Macronix), VLSI

23 Comparison among the Architectures [P-BiCS] R. Katsumata, et al, VLSI Symposia, pp , [TCAT] J. Jang, et al, VLSI Symposia, pp , [VSAT] J. Kim, et al, VLSI Symposia, pp , [VG] W. Kim, et al, VLSI Symposia, pp ,

24 Outline Why Does NAND Go to 3D? Design a 3D NAND Flash Memory Challenges and Opportunities in 3D CT NAND Flash Memory Summary 24

25 Process Integration for 3D CT NAND Flash Memory 3D memory in FEOL or BEOL? CMOS under or beside the memory array? How to handle PL layers left on periphery area Planarization between 3D memory and 2D CMOS Thermal budget management Takashi Maeda, et al., (Toshiba), VLSI

26 HK-MG for Better Performance HK can reduce the E-field and suppress the gate injection. MG can reduce WL resistivity for faster R/W. SEMATECH has been engaging HK-MG for years. The experience should be very useful to 3D CT NAND community. Jaehoon Jang, et al., (Samsung), VLSI

27 Contact Holes for Layers Contact holes for layers are very area consuming. Which approach is the most compact and manufacturable? H. Tanaka, et al., (Toshiba), VLSI 2007 Jaehoon Jang, et al., (Samsung), VLSI 2009 Jiyoung Jim, et al., (UCLA), VLSI

28 Patterning and Etching At 5xnm node, 3D memory should be more than 32 layers, in order to compete with 1Z nm MLC NAND. For 30nm layer pitch, 32 layers gives a stack height of 960nm. The hole etching is challenging not only due to the high A/R but also due to different materials. Jungdal Choi, et al., (Samsung), VLSI

29 Scaling or Stacking or MLC In 3D VG NAND, there are 3 ways to shrink equivalent cell size. Pitch scaling BL gap fill-in WL bridging Layer stacking Deep etching and profile control Multi-level cell Device variation Which is the right way in terms of business? Relative Bit Cost Ref. (25nm MLC FG NAND) 1 Log scale F=66nm, 6F 2 F=50nm, 6F 2 F=35nm, 4F 2 F=25nm, 4F 2 F=25nm, 6F 2 VG possible Number of Layer for 3D stacks 29

30 Polysilicon TFT Channel Engineering M. Mizukami, et al., (Toshiba), SSDM 2009 The Worst-On-Current (WOC) of the NAND string is strongly affected by the electron mobility in polysilicon. It should be carefully engineered. Polysilicon uniformity on the same layer and layer-to-layer uniformity are both challenging. Y. Fukuzumi, et al., (Toshiba), VLSI

31 In 2D-to-3D Paradigm Shift, Challenges = Opportunities To make 3D NAND Flash happen, collaboration should be considered. By 2013, 3D NAND Flash is going into commercialization. This will be the biggest paradigm shift in NVM business. Jungdal Choi, et al., (Samsung), VLSI

32 Summary 2D FG NAND is running out of electrons. 3D is a must to meet demands. For 3D NAND Flash, CT type is more processfriendly, and VG is the most scalable architecture. Single deep etching (for realizing the BiCS concept) and polysilicon TFT device uniformity are the most challenging topics. Macronix and other NAND giants are dedicated in this field for years. To accelerate the progress, collaboration is a good way, and should be considered. 32