SLC vs MLC: Which is best for high-reliability apps?

Transcription

1 SLC vs MLC: Which is best for high-reliability apps? Here's an examination of trade-offs, with an emphasis on how they affect the reliability of storage targeted at industrial, military and avionic applications. By Charles Cassidy Director of the Advanced Products Group TeleCommunication Systems As with most storage technologies, NAND flash vendors are constantly being pressed to minimise cost and increase density. One way the industry has responded is by packing more than one bit in a single flash storage cell. Known as multi-level cell (MLC) memory, this technology allows for a doubling or tripling of the data density with just a small increase in the cost and size of the overall silicon. This increase in density and decrease in cost per bit does come with its own trade-offs, however, which have to be considered within the context of the application. Industrial, military, and avionic applications impose very different demands in terms of environmental stresses, data endurance requirements, and expected usable life compared to consumer products such as USB thumb drives, memory cards for digital cameras, or even SSDs for consumer laptops and tablets. We ll examine those trade-offs, with an emphasis on how they affect the reliability of storage targeted at industrial, military and avionic applications. Flash cell operation Before discussing the differences between single-level cell (SLC) and MLC NAND flash, it is important to understand what makes up a flash cell. Each cell consists of a single transistor, with an additional floating gate that can store electrons (figure 1). Figure 1: A basic flash cell consists of a transistor with a (floating) gate capable of storing electrons. The cell operates as follows. For reading, the gate is electrically disconnected. The conductivity between the source and drain is then a function of the amount of charge on the floating gate. A voltage difference is set up between the drain and the source, Vd Vs and is varied to determine the threshold voltage V t when current flows between source and drain. The threshold voltage represents the amount of charge on the gate. A large amount of charge is used to represent logic 0, and a small amount of charge used to represent logic 1. Writing is done by applying the programming voltage Vp to the gate and grounding the channel, which sets up an electric field such that electrons are attracted to the surface of the channel. Some of these collide or encounter the barrier with enough energy to tunnel through the insulating layer. These electrons are captured by the floating gate. Erasing is the opposite operation, with the gate grounded and with V p applied to the channel to create an electric field with the opposite polarity. This attracts electrons back to the channel, many of which will have enough energy to cross the insulating barrier. This process is called Fowler-Nordheim Tunneling. EE Times-India eetindia.com Copyright 2012 emedia Asia Ltd. Page 1 of 6

2 This explains one of the key challenges of flash technology while it s easy to attract electrons to the floating gate one cell at a time, it s difficult to get them to leave. Reversing the process requires putting the channel at a voltage that could disturb adjacent cells, since the channel is common to many cells. For this reason, flash is erased in blocks, not a word or bit at a time. The blocks are sized by the flash manufacturer in order to balance silicon area (since each erase block carries a fair amount of overhead circuitry) and ease of use. Because of the logic structure of NAND flash, the flash must also be written or read in fairly large pages, typically 1 K to 4 KB. These pages are written from or read to a page buffer, from which individual byte reads or writes are done. Each erase block contains between 32 and 128 pages. This also helps explain why flash cells can only be written a limited number of times before they wear out. While many of the electrons travel with enough energy to cross the insulating oxide, some have enough to cross the barrier between the channel and oxide, but not enough to go all the way to the floating gate. These get trapped in the oxide. With each write/erase cycle, more electrons get trapped, which reduces the conductivity difference between the programmed and erased states. We will discuss this further when we talk about the endurance differences between single-level cell (SLC) and multi-level cell (MLC). SLC operation SLC NAND flash cells operate pretty much as described in the basic operation above. Both writing and erasing are done gradually to avoid over-stressing, which can degrade the lifetime of the cell by increasing the number of electrons trapped in the oxide or by causing oxide damage. Essentially, a write or erase is attempted, then stopped, and the cell is tested to see if the erase/write was successful. If not, it is reattempted, possibly with stronger or longer pulses. This is done several times until the operation time exceeds the specification and the cell is declared bad. Since there are only two states, a cell represents only one bit value. Each bit can have a value of programmed or erased. A 0 or 1 is determined by the threshold voltage Vt of the cell (table 1). The threshold voltage can be manipulated by the amount of charge put on the floating gate of the flash cell. Table 1: The bit value of the cell translates as either programmed or erased. Placing a charge on the floating gate will increase the threshold voltage of the cell. When the threshold voltage is high enough, the cell will be read as programmed (figure 2). No charge, or a threshold voltage of less than the minimum programmed voltage, will cause the cell to be sensed as erased. As the cell wears, these two distributions move closer together, narrowing the difference between the values of Vt for erased and programmed. When they overlap, it is impossible to distinguish between programmed and erased states. Figure 2: The threshold for each determines whether a cell is read as programmed or erased. As electrons get trapped in the oxide, the conductivity difference between the two states. When the curves overlap, the system can no longer distinguish between programmed and erased states. EE Times-India eetindia.com Copyright 2012 emedia Asia Ltd. Page 2 of 6

3 2bit per cell MLC It is also possible to store more than one bit at each cell location by using multiple threshold voltages to encode multiple states (table 2). Table 2: State table describes the amount of charge in the floating gate of the flash cell. These four states yield two bits of information. After block erasure, the cell is in the fully erased state. By increasing the number of electrons stored on the floating gate, the cell can be brought from fully erased to partially erased, to partially programmed, and, finally, to fully programmed. This is done in the same manner as described earlier for gradually programming the SLC cell, by applying write pulses, then sensing the amount of charge to ensure that the cell was properly programmed. The gaps between the various states of an MLC are much smaller than the gap between the two states of an SLC NAND flash (figure 3). Another way to describe this is that the signal-to-noise ratio of an MLC cell is much less than for an SLC cell. Because of this, a more powerful error correction code is needed to correct for errors introduced by noise, which can be either true electrical noise or noise induced by a trapped charge in a cell that has seen many program /erase cycles. Figure 3: Because the gaps between the various states of an MLC are much smaller than the gap between the two states of an SLC NAND flash, the devices need more powerful error correction code. Table 3: Memory cells with three bits yield 2 3 or eight levels. EE Times-India eetindia.com Copyright 2012 emedia Asia Ltd. Page 3 of 6

4 3bit MLC flash The MLC concept can be extended beyond just two bits; devices with three bits per cell (referred to by many as three-level cell or TLC) are currently commercially available. Three bits actually yield 2 3 or eight levels (table 3). Some companies have begun to refer to devices with three bits per cell as MLC-3, which is a better way to characterise it. At this point, the difference in charge stored on the floating gate between the levels is on the order of 100 electrons or less, so for the time being, TLC is the practical limit of extending this concept, although there are companies beginning to experiment with four bits per cell. In fact, SanDisk has recently announced a four-bit-per-cell NAND flash for USB thumb drives. All of the issues with two bits per cell become even more difficult with a greater numbers of bits. Right memory for high-reliability apps Now that we've reviewed the differences between MLC and SLC technology, let s compare their specifications to make further distinctions between the two grades with an eye towards the requirements of military, avionics and industrial applications (table 4). These applications have more stringent demands on temperature range and the reliability of the storage. The cost of lost data in a critical mission is much higher than in consumer use. When life and property are on the line, or when you only get one shot at success, reliability is everything. Table 4: A comparison of the features and capabilities of SLC versus MLC memory. Performance Since the same basic flash cell is used for SLC and MLC NAND flash, MLC can more than double the density with almost no die size penalty, and hence no manufacturing cost penalty beyond possibly yield loss. In fact, because of the large consumer demand for MLC NAND flash for digital cameras, tablets, and smart phones, MLC enjoys economies of scale that give it a cost per bit cost less than half that of SLC. The read bandwidths between SLC and MLC are comparable: SLC can read a 1KB page in about half the time that MLC can read a 2KB page. In general, the available bandwidth of a solid-state drive is more related to the controller architecture and design than to the speed of the flash. MLC NAND flash technology does pay a price in terms of access speed, however. Access and programming times are two to three times slower than for the single-level design. For many consumer applications, this speed difference will be virtually undetectable. Endurance The endurance of SLC NAND flash is 10 to 30 times more than MLC NAND flash (figure 4). This, and the difference in operating temperature, are the main reasons why SLC NAND flash is considered industrial-grade, and MLC NAND flash is considered consumer-grade. The endurance difference is also generally not a problem in consumer use. For example, a USB drive application that used the 10,000 write/erase cycles would enable the user to completely write and erase the entire contents once per day for 27 years well beyond the life of the hardware. On the other hand, a data logging application that was constantly writing telemetry or sensor data might completely write the contents of the drive 10 times a day, leading to an endurance of only 2.7 years. EE Times-India eetindia.com Copyright 2012 emedia Asia Ltd. Page 4 of 6

5 Figure 4: The endurance of SLcC is significantly higher than for MLC, making it a better fit for mission-critical applications. Error rate The error rate for MLC NAND flash is 10 to 100 times worse than that of SLC NAND flash and degrades more rapidly with increasing program/erase cycles. This is driven by the very narrow margin between voltage threshold levels in MLC. There are four principal error mechanisms that affect flash data reliability: 1. Program disturb 2. Read disturb 3. Leakage 4. Charge trapping Program disturb is caused by the stress to unselected cells in the same erase block as the cell being programmed. These unselected cells can either be adjacent bits on the same page or the corresponding bit on adjacent pages. This voltage stress can cause a small amount of charge to be deposited on the floating gates of these adjoining cells, thus weakly programming them. While not a major problem for SLC NAND flash, the addition of a small amount of charge can cause a shift between the levels in an MLC NAND flash cell. This can be a particular problem with repeated program cycles of adjoining cells. For this reason, well-designed flash controllers program pages sequentially within an erase block. This also explains why MLC NAND flash cannot withstand multiple writes per page. Read disturb is caused by the voltage difference between the selected page being read and adjacent, unselected pages. This can stress the cells in the adjacent pages and cause a small amount of charge to be transferred to the gate of an erased cell, weakly programming them; again, this is a larger problem for MLC NAND flash cells then SLC cells, since a very small voltage shift can affect the value stored. Leakage of the charge on the floating gate is the phenomenon that leads to a limit on the data retention time for a cell. The floating gates can lose electrons at a very slow rate, on the order of an electron every week to every month. With the various values in multi-level cells only differentiated by 10s to 100s of electrons, however, this can lead to data retention times that are measured in months, rather than years. This is one of the reasons for the large difference between SLC and MLC data retention and endurance. Leakage is also increased by higher temperatures, which is why MLC NAND flash is generally only appropriate for commercial temperature range applications. Charge trapping The three previous error mechanisms are transient in nature. They only affect the reliability of the data stored in the cell and cause no physical change to the hardware of the flash cell. An erase and program of the cell will remove the error; in other words, these data errors can be scrubbed. The fourth error mechanism, charge trapping, does cause a permanent change to the cell. With every program or erase cycle, electrons that don t quite have enough energy can get trapped in the insulating oxide between the channel and the floating gate. These electrons cause a permanent shift in the voltage threshold and narrow the gap between the erased and programmed states. They also interfere with the Fowler-Nordheim tunnelling effect, the mechanism for moving electrons to and from the floating gate, which leads to longer program and erase times. At the end of a cell s endurance, the programming or erase time becomes too long, and the page or block must be retired. EE Times-India eetindia.com Copyright 2012 emedia Asia Ltd. Page 5 of 6

6 Although MLC NAND flash has definite advantages in the area of cost, SLC NAND flash is a clear winner for rugged avionic, military and industrial applications. MLC NAND flash issues with data retention at higher temperature, higher bit error rates and slower access times make it unsuitable for these applications. When human lives, critical missions, or valuable capital are at stake, designers need to select the most reliable non-volatile storage available. About the author Charles Cassidy is director of the Advanced Products Group of TeleCommunication Systems (TCS) Space & Component Technology Division (SCT), which is a part of the Government Solutions Group. In his role, Cassidy leads product design, development, and manufacturing for TCS line of ruggedized solid-state drives in both high-customised and industry-standard configurations for military, aerospace, and industrial applications.he has a bachelor of science in electrical engineering from Rensselaer Polytechnic Institute in Troy, NY, and has done graduate studies in electrical engineering and computer science at Worcester Polytechnic Institute in Worcester, MA. EE Times-India eetindia.com Copyright 2012 emedia Asia Ltd. Page 6 of 6