Curriculum Vitae et Studiorum Graziano Pravadelli

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1 Curriculum Vitae et Studirum Grazian Pravadelli 1. Persnal data 2 2. Higher educatin 2 3. Awards 3 4. Schlarships and grants 3 5. Research interests Mdelling and simulatin f embedded systems Semi-frmal appraches fr embedded system verificatin Fault mdels and test generatin fr embedded systems System-level pwer cnsumptin estimatin f embedded systems 7 6. Transfer f technlgy 7 7. Teaching activities and teaching bks 7 8. Advising activities 8 9. Organizatinal activities Funded Eurpean prjects with peer review Funded Natinal prjects with peer review Industrial prjects Referee activities and participatin in prgramme cmmittees Institutinal activity Publicatins Internatinal jurnals Internatinal cnferences Bk chapters 24

2 1. Persnal data Place and date f birth: Legnag (VR) Italy, 04 July Marital status: Married since July 2003, tw sns. Current psitin: Wrking address: Previus psitins: Assciate prfessr, Università degli Studi di Verna, Italy, since January C-funder and head f prductin f EDALab s.r.l. ( since July Dipartiment di Infrmatica, Università degli Studi di Verna. Ca Vignal 2, Strada Le Grazie 15, Verna, Italy. Tel.: , Fax: grazian.pravadelli@univr.it grazian.pravadelli@edalab.it Web page: Assistant prfessr, Università degli Studi di Verna, Italy, frm January 2005 t December Pst-dc, Università degli Studi di Verna, Italy, frm April 2004 t December Higher educatin Ph.D.: Laurea: Ph.D., Cmputer Science, Università degli Studi di Verna, Italy, March Thesis title: Using functinal verificatin t evaluate the accuracy f mdel checking applied t embedded systems: thery and applicatin (advisr: Prf. Franc Fummi). Laurea degree (summa cum laude), Cmputer Science, Università degli Studi di Verna, Italy, April Thesis title (in Italian): Simulazine di errre per descrizini VHDL e SystemC per il test funzinale ( Functinal test by fault simulatin fr VHLD and SystemC mdels ) (advisr: Prf. Franc Fummi). 2

3 3. Awards Best paper candidate: A. Danese, F. Filini, G. Pravadelli A Time-Windw Based Apprach fr Dynamic Assertins Mining n Cntrl Signals, In: FIP/IEEE Internatinal Cnference n Very Large Scale Integratin (VLSI-SOC). Daejen, Krea, 5-7 Octber F. Cucchett, A. Lnardi, G. Pravadelli A cmmn architecture fr c-simulatin f SystemC mdels in QEMU and OVP virtual platfrms, In: FIP/IEEE Internatinal Cnference n Very Large Scale Integratin (VLSI-SOC). Playa del Carmen, Messic, 6-8 Octber M. Bnat, G. Di Guglielm, M. Fujita, F. Fummi, G. Pravadelli, Dynamic prperty mining fr embedded sftware. In: ACM/IEEE Internatinal Cnference n Hardware/Sftware Cdesign and System Synthesis (CODES+ISSS). Tampere, Finland, 7-12 Octber 2012, p N. Bmbieri, F. Fummi, G. Pravadelli. A Mutatin Mdel fr the SystemC TLM 2.0 Cmmunicatin Interfaces. In: ACM/IEEE Design, Autmatin and Test in Eurpe (DATE). Munich, Germany, March 2008, p Selected best paper: G. Di Guglielm, F. Fummi, C. Marcncini, G. Pravadelli. FATE: a Functinal ATPG t Traverse unstabilized EFSMs. In: IEEE Eurpean Test Sympsium (ETS). Suthamptn, UK, May p Schlarships and grants Nvember 2006: June 2004: January 2002: January 2001: Research grant Givani ricercatri 2006, Dipartiment di Infrmatica, Università degli Studi di Verna, Verna, Italy (1 year). SIGDA grant fr presenting the PhD thesis at the 7th SIGDA PhD Frum c-lcated with the 41st ACM/IEEE Design Autmatin Cnference (DAC), San Dieg, CA, USA. Research grant Givani ricercatri 2001, Dipartiment di Infrmatica, Università degli studi di Verna, Verna, Italy (1 year) Italian ministry schlarship supprting the PhD curse (3 years). 3

4 5. Research interests The research activity f Grazian Pravadelli is related t the fllwing fur main fields, partially supprted by the research prjects reprted in Sectin Mdelling and simulatin f embedded systems. 2. Semi-frmal appraches fr embedded system verificatin. 3. Fault mdels and test generatin fr embedded systems. 4. System-level pwer cnsumptin estimatin f embedded systems. Therefre, research interests f Grazian Pravadelli cncern main aspects f the design f embedded systems, including mdelling, simulatin, verificatin and testing. 5.1 Mdelling and simulatin f embedded systems The ever increasing cmplexity f mdern embedded systems requires that designers cnsider hetergeneus and ften cnflicting aspects, such as, fr example, the adptin f different levels f abstractin, the integratin f digital and analg cmpnents, the use f HW dependent sftware, the awareness f the presence f a physical envirnment in which the system is embedded, etc. This hetergeneity has been addressed thrugh varius mdelling and simulatin appraches, by adpting bth tp-dwn and bttm-up methdlgies, and by integrating mdel-based design, cmpnent-based design and c-simulatin-based techniques. Hwever, it is evident the lack f a cmputatinal mdel widely accepted that allws integrating hetergeneus cmpnents in a hmgeneus descriptin that can be easily manipulated and simulated during the varius stages f the design flw. In this cntext, Grazian Pravadelli crdinated the definitin and implementatin f a virtual prttyping and mdelling envirnment fr embedded systems (HIFSuite based n the HIF (Hetergeneus Intermediate Frmat) interchange frmat, and the definitin f the UNIVERcm (Universal Versatile Cmputatinal Mdel) cmputatinal mdel that allws t frmalize the semantics f HIF descriptins [5, 36]. Based n HIFSuite, Grazian Pravadelli eventually set up varius techniques and methdlgies fr mdelling, integratin, simulatin and verificatin f embedded systems [8, 32, 41, 43, 44, 52]. Of particular interest it is the definitin f an autmatic technique fr the abstractin f RTL (Register Transfer Level) mdels t TLM (Transactin Level Mdel) mdels [8], which avids the c-simulatin f mixed-rtl-tlm descriptins that slws dwn the simulatin speed (thse RTL), t take full advantage f the greater speed f TLM mdels. Mst f the activities related t HIFSuite and UNIVERcm were made as part f Eurpean prjects SYMBAD, VERTIGO, CONTREX, COMPLEX, SMAC and TOUCHMORE fr which HIFSuite has becme the main tl fr the creatin f virtual platfrms fr simulatin and verificatin f cmplex systems. HIFSuite is currently a cmmercial prduct f EDALab. 4

5 5.2 Semi-frmal appraches fr embedded system verificatin In the cntext f verificatin f embedded systems, the research activities f Grazian Pravadelli fcuses n the definitin f semi-frmal techniques and in particular n the study f appraches fr autmatin and ptimizatin f verificatin methdlgies based n assertins. In this cntext, the main cvered research fields are: Assertin-based verificatin fr embedded sftware [2, 3, 7, 35, 40, 42, 46, 48, 50]. The main cntributin f Grazian Pravadelli is represented by having defined a methdlgy and an autmated tl (radcheck - t apply assertin-based verificatin (ABV) t the wrld f embedded SW. ABV techniques are mainly riented t check descriptins based n transitin systems (e.g., extended finite state machines) typical f the RTL abstractin level, where the time reference fr synchrnizatin f mdels and checkers (simulated cmpnents crrespnding t the desired assertins ) is clsely related t the cncept f clck cycle. In the cntext f the embedded sftware, the absence f such a precise time reference makes it much mre difficult t apply ABV techniques. This limitatin has been vercme in [4, 40] using the principles f mdel-based mdelling. The research has led the implementatin f radcheck, an autmated tl fr assertin-based verificatin f embedded sftware develped under the VAFER prject. radcheck is currently marketed by STMPrducts and develped in cllabratin with EDALab with the scientific supervisin f Grazian Pravadelli. Other relevant cntributins were prduced as part f the ptimizatin f assertins in real-time systems, t avid that the timing cnstraints impsed by such systems were missed because f the time required fr the verificatin f statements in a cntext f selfchecking [7, 35, 50]. Autmatic generatin f assertins [21, 23, 24, 28, 39]. In these wrks, the traditinal flw that invlves first defining assertins crrespnding t the specificatins and then checking them has been reversed. In [23, 28, 39] sme methds are presented fr autmatic extractin f tempral assertins frm simulatin traces f HW/SW descriptins. Mined assertins can then be cmpared with the initial specificatins t analyse the presence f discrepancies, which wuld be symptm f an incrrect implementatin. Cmpared t techniques already existing in the literature that extract nly Blean prperties, the appraches prpsed by Grazian Pravadelli are distinguished by the ability t generate assertins that predicate bth at Blean and nn- Blean dmains by extracting arithmetic-lgic expressin n Blean, integer and flat data types. Extractin f invariants, i.e., arithmetic lgic expressins that represent a stable cnditin hlding n the analysed executin traces, has been investigated t [21, 24] by prpsing efficient strategies expliting the pwer f GPU architecture fr speeding-up the mining phase. Reuse and autmatic abstractin f assertins [2, 3, 29, 47, 51]. The issues related t the integratin and simulatin f descriptins represented at different levels f abstractin (e.g., RLT and TLM) and n different dmains (e.g., analg, digital) have a great impact in the cntext f verificatin t. An assertin initially written fr an analg mdel can nt be reused t check 5

6 the crrespnding digital mdel after its discretizatin. Similarly, an assertin defined at RTL level need t be rewritten when mving twards the TLM level. In this cntext, the activity f Grazian Pravadelli was cncentrated in the definitin f methdlgies fr the autmatic reuse and abstractin f assertins between different dmains and abstractin levels in rder t avid cstly (in terms f time) and risky (in terms f errrs that can be intrduced) manuals redefinitin. In particular, while there are several wrks that prpse appraches fr re-use f assertins frm TLM t RTL, the abstractin f assertins frm RTL t TLM has been addressed fr the first time in [2, 3, 29]. Assertin qualificatin [15, 16, 22, 59, 65, 71, 89]. The lack f exhaustiveness is ne f the biggest prblems related t the use f simulatin-based techniques fr digital system validatin. Frmal verificatin aims at vercming this prblem by prving assertins n mathematical mdels representing the system implementatin. In this cntext, tempral lgic assertins are defined t frmally check the crrectness f a design implementatin with respect t the specificatin. Hwever, the use f assertins cannt cmpletely assure the crrectness f the design implementatin. Assertin s vacuity, incmpleteness and incnsistency may prevent the effectiveness f assertin-based verificatin appraches, leading the verificatin engineers t a false sense f security. T imprve the degree f cnfidence n assertin-based verificatin, Grazian Pravadelli has prpsed several techniques t qualify the set f assertins in terms f design cverage [15, 16, 65, 89], vacuity analysis [59, 71] and degree f interestingness [22], when used fr checking the crrectness f a mdel. The wrk f Pravadelli distinguishes frm previus appraches since it is based n mutant analysis rather than symblic methds, which guarantees a mre accurate estimatin f assertin quality in a shrter time. Mst f the activities related t the semi-frmal-verificatin f embedded systems have been undertaken under the prjects EFFORT, VAFER, OPTIMUM and SMAC and cllabratins between EDALab and the University f Verna. 5.3 Fault mdels and test generatin fr embedded systems Autmatic test pattern generatin is the basis f all the verificatin techniques that are based n simulatin. Very ften this generatin is driven by metrics that require the applicatin f fault mdels t simulate the presence f errrs (design) r defects (physical) within the mdel and/r its implementatin. Such metrics measure the quality f the generated sequences accrding t their ability t "find" faults injected by cmparing the results f the fault-free mdel/implementatin with thse f the mdels/implementatins perturbed by faults. In this cntext, Grazian Pravadelli has prpsed numerus techniques fr the generatin f test sequences integrating symblic, cnclic and cncrete appraches [9, 45]. In additin, Grazian Pravadelli defined a language fr specifying test sequences (Testbench Specificatin Language) [37, 29] particularly suitable t represent cnstraints that must be met t activate (and then test) special cnditins that wuld nt be analysed by using traditinal prbabilistic appraches and that wuld require t space-time cnsuming resurces fr an exhaustive evaluatin. 6

7 Grazian Pravadelli wrked als n fault mdelling strategies [1, 6, 3, 33, 38, 49], bth fr hardware descriptins and embedded sftware. In particular, it is wrth nting the wrk published in [9] where fr the first time a fault mdel fr TLM descriptin is prpsed. Mst f the activities related t the semi-frmal-verificatin f embedded systems were carried n as part f the VAFER and OPTIMUM prjects and cllabratins between EDALab and the University f Verna. 5.4 System-level pwer cnsumptin estimatin f embedded systems Recently, Grazian Pravadelli has mved his attentin als twards system-level mdeling f extrafunctinal prperties, targeting, in particular, pwer behavirs f digital IPs. In this field he prpsed an innvative apprach fr the autmatic generatin f pwer state machines (PSMs) that allw validating the pwer cnsumptin f a system inside a virtual prttype [20]. Currently, nne ther apprach exists in the literature that autmatically generate PSMs. The apprach starts by dynamically mining tempral assertins frm the functinal traces. Frm them, the states and the transitins f a crrespnding set f PSMs are generated and ptimized by expliting a calibratin prcess relying n a set f training pwer traces. Future research activities in this cntext will be devted t address the generatin f PSMs fr time-dependent and data dependent designs and their abstractin twards the TLM level. 6. Transfer f technlgy Grazian Pravadelli is c-funder and head f the prductin f EDALab s.r.l. ( an Italian SME whse missin cnsists f giving supprt fr innvatin and technlgy transfer in embedded system mdeling and verificatin. EDALab was funded n July 16, 2007 and it currently emplys 13 persns in the develpment f embedded SW, and the design f CAD tls fr mdelling and verificatin f netwrked embedded systems. EDALab has been invlved in several industrial and scientific prjects (including the EU prjects CONTREX, COMPLEX, SMAC and COCONUT) in cperatin with internatinal cmpanies (e.g., STMicrelectrnics, Keysight (Agilent), Exr Internatinal), universities and research centres. Amng EDALab s main prducts, HIFSuite and radcheck fund their scientific basis n the research activity f Grazian Pravadelli. 7. Teaching activities and teaching bks Grazian Pravadelli s teaching activities include: Teaching activity at Università degli Studi di Verna, Italy (since 01/2005): perating systems (mre than 800 hurs); advanced perating systems (mre than 600 hurs); 7

8 design autmatin f embedded systems (mre than 200 hurs), basic infrmatin technlgy (mre than 150 hurs). Teaching activity at Plitecnic di Milan, Italy (since 09/2002): basic infrmatics (almst 1000 hurs). Teaching activity at University f Trent, Italy (since 02/2015): perating systems (60 hurs). Grazian Pravadelli is c-authr f the bk chapter (in Italian): D. Btturi, F. Fntana, G. Pravadelli, Appendice A: Labratri di Linux, in V. Manca Metdi Infrmazinali, Bllati Bringhieri 2003, pp Grazian Pravadelli translated frm English t Italian with Prf. Alfred Petrsin the bk: D.M. Dhamdhere, Operating systems. A cncept based apprach, McGraw-Hill, Grazian Pravadelli translated frm English t Italian the bk: D.M. Dhamdhere, A Slutins Manual fr Operating systems. A cncept based apprach, McGraw-Hill, Grazian Pravadelli translated frm English t Italian the fllwing bk chapters: Istruzini Macchina IA-32, in C. Hamacher, Z. Vranesic, S. Zacky Intrduzine all architettura dei calclatri, McGraw-Hill 2007, pp Elenc delle Istruzini Macchina IA-32, in C. Hamacher, Z. Vranesic, S. Zacky Intrduzine all architettura dei calclatri, McGraw-Hill 2007, pp Grazian Pravadelli revised the fllwing bks: D.M. Dhamdhere, Operating systems. A cncept based apprach, McGraw-Hill Intenatinal Editin A. Bellini, A. Guidi, Linguaggi C - Guida alla prgrammazine, McGraw-Hill Advising activities Grazian Pravadelli s advising activities include: Advising f 2 PhD students at Università degli Studi di Verna, Italy Tara Ghasempuri, Imprving ABV by autmatic generatin and abstractin f PSL assertins. Expected graduatin date: May 2016 Alessandr Danese, System-level functinal and extra-functinal characterizatin f SCs thrugh assertin mining. Expected graduatin date: May 2018 C-advising f 6 PhD students at Università degli Studi di Verna, Italy: Valeri Guarnieri, Design and verificatin techniques fr TLM-based design flws, May Sara Vinc, Reuse and integratin f hetergeneus cmpnents fr efficient embedded sftware generatin, May

9 Luigi Di Guglielm, Realizability f embedded cntrllers: frm hybrid mdels t cncrete implementatins, May Giuseppe Di Guglielm, On the validatin f embedded systems thrugh functinal ATPG, April Nicla Bmbieri, A TLM design fr verificatin methdlgy, March Cristina Marcncini, A Functinal ATPG as a bridge between validatin and testing. March Advising f mre than 60 between undergraduate and graduate student thesis in the field f embedded systems and perating systems at Università degli Studi di Verna, Italy. 9. Organizatinal activities Grazian Pravadelli has participated t rganizatinal activities in the cntext f: natinal and internatinal prjects; review activities and prgramme cmmittee; institutinal activities. 9.1 Funded Eurpean prjects with peer review Grazian Pravadelli has participated t the research activities in the fllwing prjects Eurpean prjects: 1. Title: Design f embedded mixed-criticality cntrl systems under cnsideratin f extrafunctinal prperties (CONTREX FP7-ICT ) Funding rganizatin: Eurpean cmmissin Funding schema: Large-scale integrating prject Perid: Octber 2013 September 2016 Number f participants: 15 Achieved cntributin: Rle in the prject: prject leader f system analysis, validatin and explratin f EDALab research unit and prject manager f HIFSuite develpment. 2. Title: Smart system c-design (SMAC FP7-ICT ) Funding rganizatin: Eurpean cmmissin Funding schema: Large-scale integrating prject Perid: Octber 2011 March 2015 Number f participants: 17 Achieved cntributin: Rle in the prject: prject leader f wrk package 2 cncerning the c-simulatin platfrm fr EDALab research unit and prject manager f HIFSuite develpment. 3. Title: Autmatic Custmizable Tl-chain fr Hetergeneus Multicre Platfrm Sftware Develpment (TOUCHMORE FP7-ICT ) 9

10 Funding rganizatin: Eurpean cmmissin Funding schema: Small r medium scale fcused research prject Perid: September 2011 September 2014 Number f participants: 8 Achieved cntributin: Rle in the prject: prject manager f HIFSuite develpment. 4. Title: Cdesign and pwer management in platfrm-based design space explratin (COMPLEX FP7-ICT ) Funding rganizatin: Eurpean cmmissin Funding schema: Large-scale integrating prject Perid: December 2009 Nvember 2012 Number f participants: 15 Achieved cntributin: Rle in the prject: prject manager f HIFSuite develpment. 5. Title: A crrect by cnstructin wrkbench fr design and verificatin f embedded systems (COCONUT FP IST ) Funding rganizatin: Eurpean cmmissin Funding schema: Small r medium scale fcused research prject Perid: January June 2010 Number f participants: 10 Achieved cntributin: Rle in the prject: discrete system prject manager. 6. Title: Verificatin and validatin f embedded design wrkbench (VERTIGO IST ) Funding rganizatin: Eurpean cmmissin Funding schema: Small r medium scale fcused research prject Perid: June Nvember 2008 Number f participants: 7 Achieved cntributin: Rle in the prject: technical respnsible f the research unit. 7. Title: Frmal verificatin in system level based design (SYMBAD IST ) Funding rganizatin: Eurpean cmmissin Funding schema: Small r medium scale fcused research prject Perid: March Octber 2004 Number f participants: 4 Achieved cntributin: Rle in the prject: crdinatr f the develpment f the research unit applicatins. 10

11 9.2 Funded Natinal prjects with peer review 1. Title: Mdeling and simulatin f cmplex integrated systems fr multimedia applicatins (CNR01) Funding rganizatin: Natinal research center (CNR) Funding schema: research prject Perid: Octber 2001 September 2002 Number f participants: 4 Achieved cntributin: Rle in the prject: Crdinatr f the develpment f research unit applicatins. 2. Title: Mdeling, simulatin and validatin f system n chips (PRIN02) Funding rganizatin: Italian Research Ministry (MIUR) Funding schema: Natinal interest research prject (PRIN) Perid: May 2002 April 2004 Number f participants: 6 Achieved cntributin: Rle in the prject: Crdinatr f the develpment f research unit applicatins. 3. Title: Reuse f IP-cre in distributed embedded systems (RISE) Funding rganizatin: Università degli Studi di Verna Funding schema: Yung researchers 2001 Perid: January 2002 December 2002 Number f participants: 1 Achieved cntributin: 5900 Rle in the prject: crdinatr. 4. Title: Mdeling, simulatin and verificatin f MPSC platfrms (PRIN05) Funding rganizatin: Italian Research Ministry (MIUR) Funding schema: Natinal interest research prject (PRIN) Perid: January 2006 December 2008 Number f participants: 5 Achieved cntributin: Rle in the prject: technical manager f the research unit. 5. Title: A smth refinement flw fr c-designing f hardware/sftware threads (SOFT) Funding rganizatin: Università degli Studi di Verna Funding schema: Yung researchers 2006 Perid: January 2007 December 2007 Number f participants: 1 Achieved cntributin: 2500 Rle in the prject: crdinatr. 11

12 6. Title: Yield Imprvement in Nantechnlgy Prductin Prcess f Standard Cells Based Integrated Circuits (ImpNanIC) Funding rganizatin: PDF Slutins, Desenzan del Garda (BS) Funding schema: Jint prject 2005, Università di Verna Perid: January 2007 December 2007 Number f participants: 2 Achieved cntributin: Rle in the prject: technical prject manager. 7. Title: An EFSM-based Framewrk fr Designing and Verifying Embedded Sftware (EFFORT) Funding rganizatin: STM Prducts, Verna Funding schema: Jint prject 2007 Università di Verna Perid: January 2008 December 2009 Number f participants: 2 Achieved cntributin: Rle in the prject: technical prject manager. 8. Title: Optimizing dependability via mutatin analysis fr micrelectrnics (OPTIMUM) Funding rganizatin: STM Prducts, Verna Funding schema: Jint prject 2010 Università di Verna Perid: January 2011 December 2012 Number f participants: 2 Achieved cntributin: Rle in the prject: prject manager. 9. Title: Frmal verificatin f embedded Systems (VAFER) Funding rganizatin: Regine Venet. Funding schema: Reginal prject t supprt industrial research activity, experimental analysis, innvatin and technlgical disseminatin (L.R. n.9 18/05/2007) Perid: Octber 2010 September 2012 Number f participants: 4 Achieved cntributin: Rle in the prject: prject manager. 10. Title: Smart ple WSN netwrk (SPAWNE) Funding rganizatin: Telefin s.p.a (VR) Funding schema: Jint prject 2014, Università di Verna Perid: January 2015 December 2015 Number f participants: 2 12

13 9.3 Industrial prjects Achieved cntributin: Rle in the prject: prject crdinatr. 1. Title: Applicatin f an hybrid methdlgy fr functinal verificatin based n frmal techniques and test pattern generatin (STM01) Funding rganizatin: STMicrelectrnics Agrate Brianza Funding schema: industrial prject Perid: May 2001 April 2002 Number f participants: 2 Achieved cntributin: Rle in the prject: Crdinatr f the develpment f applicatins. 2. Title: Develpment f an autmatic system fr the validatin f a develpment envirnment f embedded SW Funding rganizatin: STM Prducts, Verna Funding schema: Industrial prject Perid: April 2009 December 2009 Number f participants: 2 Achieved cntributin: Rle in the prject: technical manager. 3. Title: Lcalizatin f Visual Studi 2012 MSDN Library Funding rganizatin: Micrsft Crp. Redmnd USA Perid: Octber 2013 April 2014 Number f participants: 2 Achieved cntributin: Rle in the prject: crdinatr 4. Title: Lcalizatin f Visual Studi 2012 MSDN Library Funding rganizatin: Micrsft Crp. Redmnd USA Perid: June 2012 September 2012 Number f participants: 2 Achieved cntributin: Rle in the prject: crdinatr 5. Title: An innvative system fr mnitring and cntrl based n wireless sensrs Funding rganizatin: ABS Cmputers, Verna Perid: January 2012 December 2012 Number f participants: 2 Achieved cntributin: Rle in the prject: crdinatr 13

14 9.4 Referee activities and participatin in prgramme cmmittees Grazian Pravadelli has cperated as reviewer fr: several internatinal cnferences: IEEE CODES+ISSS, ACM/IEEE DAC, ACM/IEEE DATE, IEEE ETS, ACM GLSVLSI, IEEE HLDVT, IEEE ITC, IEEE MEMOCODE, IEEE MTV, IEEE BEC, IEEE FDL, IEEE ICCAD, IFIP/IEEE VLSI-SOC, and several internatinal jurnals: ACM Transactins n Design Autmatin f Electrnic Systems, ACM Transactins n Embedded Cmputing, IEEE Transactin n Cmputers, IEEE Transactin n Cmputer-Aided Design f Integrated Circuits and Systems, Kluwer Internatinal Jurnal f Parallel Prgramming, Springer Design Autmatin fr Embedded Systems, Springer Jurnal f Electrnic Testing, Elsevier Micrprcessrs and Micrsystems, Eurasip Jurnal f Embedded Systems, IEEE Eletrnic Ntes, Elsevier Integratin, The VLSI Jurnal). Grazian Pravadelli has been member f the prgramme cmmittee f the fllwing internatinal cnferences: ACM/IEEE Internatinal Cnference n Hardware/Sftware Cdesign and System Synthesis (CODES+ISSS) since 2011; IEEE Internatinal Cnference in Very Large Scale Integratin (VLSI-SC) since 2010 (track chair f Prttyping, Verificatin, Mdeling, and Simulatin in 2015); IEEE Biennial Baltic Electrnics Cnference (BEC) since 2008; Design, Analysis and Tls fr Integrated Circuits and Systems (DATICS) frm 2008 t 2012; Internatinal Cnference n Infrmatin and Sftware Technlgies since Latin American Test Sympsium since Grazian Pravadelli has been finance chair ACM/IEEE Internatinal Sympsium n Netwrks-n-Chip (NOCS) Grazian Pravadelli has been rganizer and speaker f the fllwing tutrials: Methds and tls fr smart device integratin and simulatin In ACM/IEEE Embedded Systems Week (ESWEEK) 2014, New Delhi, India Assertin-based verificatin: a Cmmn Verificatin Infrastructure fr SC and Embedded Sftware. In ACM/IEEE Design, Autmatin and Test in Eurpe (DATE) 2013, Grenble, France. Assertin-based verificatin fr SC and embedded sftware. In IEEE Asia and Suth Pacific Design Autmatin Cnference (ASP-DAC) 2012, Sydney, Australia. 9.5 Institutinal activity Grazian Pravadelli has serviced at University f Verna in the fllwing rles: 14

15 President f the self-evaluatin cmmissin f the master curse n Cmputer Science and Engineering (since 2014). President f the self-evaluatin cmmissin f the bachelr curse n Cmputer Science (frm 2009 t 2014). President f the Cmitat Area CIVR 09 (frm 2008 t 2010). Delegate f the Teaching Staff Cuncil fr the pst-graduate degree in Cmputer Science at the Graduate Schl f Science Engineering Medicine (frm 2007 t 2009). 10. Publicatins 10.1 Internatinal jurnals 1. D. Ferrarett, G. Pravadelli, Simulatin-based fault injectin with QEMU fr speeding-up dependability analysis f embedded sftware, «Jurnal f Electrnic Testing: Thery and Applicatins» (accepted fr publicatin, t appear in 2016). 2. N. Bmbieri, F. Fummi V. Guarnieri, G. Pravadelli F. Stefanni; T. Ghasempuri, M Lra, G. Auditre, M. Negr Marcigaglia, Reusing RTL assertin checkers fr verificatin f SystemC TLM mdels, «Jurnal f Electrnic Testing: Thery and Applicatins», Vl. 31, n.2, 2015, pp N. Bmbieri, F. Fummi, V. Guarnieri. G. Pravadelli, Testbench qualificatin f SystemC TLM prtcls thrugh Mutatin Analysis. «IEEE Transactins n Cmputers». Vl. 63, n.5, 2014, pp G. Di Guglielm, L. Di Guglielm, A. Fltinek, M. Fujita, F. Fummi, C. Marcncini, G. Pravadelli. On the integratin f mdel-driven design and dynamic assertin-based verificatin fr embedded sftware. «The Jurnal f Systems and Sftware», vl. 86, 2013, pp L. Di Guglielm, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinc. UNIVERCM: The UNIversal VERsatile Cmputatinal Mdel fr Hetergeneus System Integratin. «IEEE Transactins n Cmputers», vl. 62, 2013, pp V. Guarnieri, G. Di Guglielm, N. Bmbieri, G. Pravadelli, F. Fummi, H. Hantsn, J. Raik, M. Jenihhin, R. Ubar. On the Reuse f TLM Mutatin Analysis at RTL. «Jurnal f Electrnic Testing: Thery and Applicatins», vl. 28, n. 4, 2012, pp V. Izsimv, G. Di Guglielm, M. Lra, G. Pravadelli, F. Fummi, Z. Peng, M. Fujita. Time- Cnstraint-Aware Optimizatin f Assertins in Embedded Sftware. «Jurnal f Electrnic Testing: Thery and Applicatins», vl. 28, n. 4, 2012, pp N. Bmbieri, F. Fummi, G. Pravadelli. Autmatic Abstractin f RTL IPs int Equivalent TLM Descriptins. «IEEE Transactins n Cmputers», vl. 60, n. 12, 2011, pp

16 9. G. Di Guglielm, L. Di Guglielm, F. Fummi Franc, G. Pravadelli. Efficient Generatin f Stimuli fr Functinal Verificatin by Backjumping Acrss Extended FSMs. «Jurnal f Electrnic Testing: Thery and Applicatins», vl. 27, n. 2, 2011, pp N. Bmbieri, M. Ferrari, F. Fummi, G. Di Guglielm, G. Pravadelli, F. Stefanni, A. Venturelli. HIFSuite: Tls fr HDL Cde Cnversin and Manipulatin. «Eurasip Jurnal On Embedded Systems», vl. 2010, n /2010/436328, 2010, pp F. Fummi, M. Lghi, M. Pncin, G. Pravadelli. A C-Simulatin Methdlgy fr HW/SW Validatin and Perfrmance Estimatin. «ACM Transactins n Design Autmatin f Electrnic Systems», vl. 14, n. 2, 2009, pp. 23:1-23: N. Bmbieri, F. Fummi, G. Pravadelli. Reuse and Optimizatin f Testbenches and Prperties in a TLM-t-RTL Design Flw. «ACM Transactins n Design Autmatin f Electrnic Systems», vl. 13, n. 3, 2008, pp. 47:1-47: N. Bmbieri, A. Fedeli, F. Fummi, G. Pravadelli. Hybrid Incremental Assertin-Based Verificatin fr Functinal Validatin in TLM Design Flws. «IEEE Design &Test f Cmputers», vl. 24, n. 2, 2007, pp G. Di Guglielm, F. Fummi, C. Marcncini, G. Pravadelli. Imprving High-Level and Gate- Level Testing with FATE: a Functinal ATPG Traversing Unstabilized EFSMs. «IET Cmputers & Digital Techniques», vl. 1, n. 3, 2007, pp A. Fedeli, F. Fummi, G. Pravadelli. Prperties Incmpleteness Evaluatin by Functinal Verificatin. «IEEE Transactins n Cmputers», vl. 56, n. 4, 2007, pp F. Fummi, G. Pravadelli. T Few r t Many Prperties? Measure it by ATPG!. «Jurnal f Electrnic Testing: Thery and Applicatins», vl. 23, n. 5, 2007, pp M. Lghi, T. Margaria, G. Pravadelli, B. Steffen. Dynamic and Frmal Verificatin f Embedded Systems: A Cmparative Survey. «Internatinal Jurnal f Parallel Prgramming», vl. 33, n. 6, 2005, pp F. Fummi, C. Marcncini, G. Pravadelli. Lgic-Level Mapping f High-Level Faults. «Integratin, the VLSI Jurnal», vl. 38, n. 3, 2004, pp F. Ferrandi, F. Fummi, G. Pravadelli, D. Sciut. Identificatin f Design Errrs thrugh Functinal Testing. «IEEE Transactins n Reliability», vl. 52, n. 4, 2003, pp Internatinal cnferences 20. A. Danese, G. Pravadelli, I. Zandnà. Autmatic generatin f pwer state machines thrugh dynamic mining f tempral assertins. In ACM/IEEE Design autmatin and Test in Eurpe (DATE), Dresden, Germany, March 2016 (t appear). 21. N. Bmbieri, F. Busat, A. Danese, L. Picclbni, G. Pravadelli. Expliting GPU Architectures fr Dynamic Invariant Mining. In IEEE Internatinal Cnference n Cmputer Design (ICCD), New Yrk, NY, USA, Octber

17 22. T. Ghasempuri, G. Pravadelli. On the estimatin f assertin interestingness. In IFIP/IEEE Internatinal Cnference n Very Large Scale Integratin (VLSI-SOC), Daejen, Krea, 5-7 Octber A. Danese, F. Filini, G. Pravadelli. A time-windw based apprach fr dynamic assertins mining n cntrl signals. In IFIP/IEEE Internatinal Cnference n Very Large Scale Integratin (VLSI-SOC), Daejen, Krea, 5-7 Octber A. Danese, L. Picclbni, G. Pravadelli. A parallelizable apprach fr mining likely invariants. In ACM/IEEE Internatinal Cnference Hardware/Sftware Cdesign and System Synthesis (CODES+ISSS), Amsterdam, The Netherland, 5-8 Octber A. Danese, T. Ghasempuri, G. Pravadelli, Autmatic extractin f assertins frm executin traces f behaviural mdels. In ACM/IEEE Design autmatin and Test in Eurpe (DATE), Grenble, France, 9-13 March N. Bmbieri, R. Filippzzi, F. Stefanni, G. Pravadelli, RTL prperty abstractin fr TLM assertin-based verificatin. In ACM/IEEE Design autmatin and Test in Eurpe (DATE), Grenble, France, 9-13 March D. Ferrarett, G. Pravadelli, Efficient fault injectin in QEMU. In IEEE Latin American Test Sympsium (LATS), March L. Picclbni, G. Pravadelli, Simplified stimuli generatin fr scenari and assertin based verificatin. In IEEE Latin-American Test Wrkshp (LATW), Frtaleza, Brasil, March, 2014, pp N. Bmbieri, F. Fummi, V. Guarnieri, G. Pravadelli, F. Stefanni, T. Ghasempuri, M. Lra, G. Auditre, M. Negr Marcigaglia, On the Reuse f RTL assertins in Systemc TLM Verificatin. In IEEE Latin-American Test Wrkshp (LATW), Frtaleza, Brasil, March, 2014, pp F. Cucchett, A. Lnardi, G. Pravadelli, A cmmn architecture fr c-simulatin f SystemC mdels in QEMU and OVP virtual platfrms. In IFIP/IEEE Internatinal Cnference n Very Large Scale Integratin, Playa del Carmen, Mexic, 6-8 Octber, 2014, pp M. Bertasi, G. Di Guglielm, G. Pravadelli. Autmatic Generatin f Cmpact Frmal Prperties fr Effective Errr Detectin. In "ACM/IEEE Internatinal Cnference Hardware/Sftware Cdesign and System Synthesis", Mntreal, Canada, 28 September - 4 Octber 2013, pp F. Fummi, V. Guarnieri, G. Pravadelli, F. Stefanni, W. Vendraminett. Autmatic HDL Cnversin and Abstractin Methdlgies. In "Embedded Wrld Cnference", Nuremberg, Germany, February 2013, pp G. Di Guglielm, D. Ferrarett, F. Fummi, G. Pravadelli. Efficient Fault Simulatin thrugh Dynamic Binary Translatin fr Dependability Analysis f Embedded Sftware. In "IEEE Eurpean Test Sympsium (ETS)", Avignn, France, May 2013, pp

18 34. F. Fummi, C. Marcncini, G. Pravadelli. Teaching embedded sftware design with radsuite. In "ACM Wrkshp n Embedded and Cyber-Physical Systems Educatin (WESE)", Mntreal, Canada, 3 Octber 2013, pp S. Brnuzzi, G. Di Guglielm, F. Fummi, G. Pravadelli. Accurate Prfiling f Oracles fr Self- Checking Time-Cnstrained Embedded Sftware. In "IEEE Internatinal High-Level Design Validatin and Test Wrkshp (HLDVT)", Huntingtn Beach, CA, 9-10 Nvember 2012, pp L. Di Guglielm, F. Fummi, G. Pravadelli, F Stefanni, S. Vinc. A Frmal Supprt fr Hmgeneus Simulatin f Hetergeneus Embedded Systems. In "IEEE Internatinal Sympsium n Industrial Embedded Systems", Karlsruhe, Germany, June G. Di Guglielm, G. Pravadelli. A testbench specificatin language fr SystemC Verificatin. In "IEEE Internatinal Cnference n Hardware/Sftware Cdesign and System Synthesis", Tampere, Finland, 7-12 Octber 2012, pp U. Repinski, H. Hantsn, M. Jenihhin, J. Raik, R. Ubar, G. Di Guglielm, G. Pravadelli, F. Fummi. Cmbining Dynamic Slicing and Mutatin Operatrs fr ESL Crrectin. In "IEEE Eurpean Test Sympsium", Annecy, France, 28 May 1 June 2012, pp M. Bnat, G. Di Guglielm, M. Fujita., F. Fummi, G. Pravadelli. Dynamic prperty mining fr embedded sftware. In "Internatinal Cnference n Hardware/Sftware Cdesign and System Synthesis", Tampere, Finland, 7-12 Octber 2012, pp G. Di Guglielm G, L. Di Guglielm, F. Fummi, G. Pravadelli. Enabling dynamic assertinbased verificatin f embedded sftware thrugh mdel-driven design. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Dresden, Germany, March 2012, pp M. Becker, G.B. Gnkam Def, W. Mueller, F. Fummi, G. Pravadelli, S. Vinc. MOUSSE: scaling MOdelling and verificatin t cmplex hetergeneus embedded Systems Evlutin. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Dresden, Germany, March 2012, pp G. Di Guglielm, L. Di Guglielm, G. Pravadelli, F. Fummi. On the use f assertins fr embedded-sftware dynamic verificatin. In "Sympsium n Design and Diagnstics f Electrnic Circuits and Systems", Tallinn, Estnia, April 2012, pp N. Bmbieri, F. Fummi, V. Guarnieri, G. Pravadelli, S. Vinc. Redesign and Verificatin f RTL IPs thrugh RTL-t-TLM Abstractin and TLM Synthesis. In "IEEE Internatinal Wrkshp n Micrprcessr Test and Verificatin (MTV)", Austin, TX, USA, December 2012, pp D. Braga, F. Fummi, G. Pravadelli, S. Vinc. The Strange Pair: IP-XACT and UNIVERCM t Integrate Hetergeneus Embedded Systems. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp (HLDVT)", Huntingtn Beach, CA, 9-10 Nvember 2012, pp

19 45. G. Di Guglielm, M. Fujita, F. Fummi, G. Pravadelli, S. Sffia. EFSM-based mdel-driven apprach t cnclic testing f system-level design. In "ACM/IEEE Internatinal Cnference n Frmal Methds and Mdels fr Cdesign", Cambridge, UK, July 2011, pp G. Di Guglielm, L. Di Guglielm, F. Fummi, G. Pravadelli. IPA: Assertin-based verificatin in embedded-sftware design. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp", Napa Valley, CA, USA, 9-11 Nvember 2011, pp L. Di Guglielm, F. Fummi, G. Pravadelli. IPA: Reusing f Prperties after Discretizatin f Hybrid Autmata. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp (HLDVT)", Napa Valley, CA, USA, 9-11 Nvember, 2011, pp G. Di Guglielm, M. Fujita, L. Di Guglielm, F. Fummi, G. Pravadelli, C. Marcncini, A. Fltinek. Mdel-Driven Design and Validatin f Embedded Sftware. In "IEEE/ACM Internatinal Wrkshp n Autmatin f Sftware Testing (ICSE Wrkshp)", Waikiki, Hnulu, Hawaii, May 2011, pp V. Guarnieri, N. Bmbieri, G. Pravadelli, F. Fummi, H. Hantsn, J. Raik, M. Jenihhin, R. Ubar. Mutatin Analysis fr SystemC Designs at TLM. In "IEEE Latin-American Test Wrkshp (LATW)", Prt de Galinhas (PE), Brazil, March 2011, pp V. Izsimv, Z. Peng, M. Lra, G. Pravadelli, F. Fummi, G. Di Guglielm, M. Fujita. Optimizatin f assertin placement in time-cnstrained embedded systems. In "IEEE Eurpean Test Sympsium", Trndheim, Nrway, May 2011, pp L. Di Guglielm, F. Fummi, G. Pravadelli. Reusing f Prperties after Discretizatin f Hybrid Autmata. In "Internatinal Wrkshp n Micrprcessr Test and Verificatin (MTV)", Austin, TX, USA, 5-7 December L. Di Guglielm, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinc. UNIVERCM: the UNIversal VERsatile Cmputatinal Mdel fr hetergeneus embedded system design. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp (HLDVT)", Napa Valley, CA, USA, 9-11 Nvember 2011, pp N. Bmbieri, F. Fummi, G. Pravadelli. Abstractin f RTL IPs int Embedded Sftware. In "ACM/IEEE Design Autmatin Cnference (DAC)", Anaheim, CA, USA, June 2010, pp L. Di Guglielm, F. Fummi, N. Orlandi, G. Pravadelli. DDPSL: an Easy Way f Defining Prperties. In "IEEE Internatinal Cnference n Cmputer Design (ICCD)", Amsterdam (The Netherlands), 3-6 Octber 2010, pp M. Bertasi G. Di Guglielm, F. Fummi, G. Pravadelli. Effective EFSM generatin fr HW/SWdesign verificatin. In "Biennial Baltic Electrnics Cnference", Tallinn, Estnia, 4-6 Octber 2010, pp N. Bmbieri, G. Di Guglielm, L. Di Guglielm, M. Ferrari, F. Fummi, G. Pravadelli, F. Stefanni, A. Venturelli. HIFSuite: Tls fr HDL Cde Cnversin and Manipulatin. In "IEEE 19

20 Internatinal High Level Design Validatin and Test Wrkshp", Anaheim, CA, June 2010, pp M. Becker, G. Di Guglielm, F. Fummi, W. Mueller, G. Pravadelli. T. Xie. RTOS-aware refinement fr TLM2.0-based HW/SW designs. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Dresden, Germany, 8-12 March 2010, pp G. Di Guglielm, F. Fummi, G. Pravadelli, S. Sffia, M. Rveri. Semi-Frmal Functinal Verificatin by EFSM traversing via NuSMV. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp", Anaheim, CA, USA, June 2010, pp Di Guglielm Luigi; Fummi Franc; Pravadelli Grazian. Vacuity Analysis fr Prperty Qualificatin by Mutatin f Checkers. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Dresden, Germany, 8-12 March 2010, pp N. Bmbieri, F. Fummi, G. Pravadelli, S. Vinc. Crrect-by-cnstructin generatin f device drivers based n RTL testbenches. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Nice, France, April 2009, pp N. Bmbieri, F. Fummi, G. Pravadelli, M. Hamptn, F. Letmbe. Functinal qualificatin f TLM verificatin. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Nice, France, April 2009, pp G. Di Guglielm; F. Fummi; M. Hamptn; F. Letmbe, G. Pravadelli. On the Functinal Qualificatin f a Platfrm Mdel. In "IEEE Internatinal Sympsium n Defect and Fault Tlerance in VLSI Systems (DFTS)", Chicag, IL, USA, 7-9 Octber, N. Bmbieri, F. Fummi, G. Pravadelli. On the Mutatin Analysis f SystemC TLM-2.0 Standard. In "IEEE Internatinal Wrkshp n Micrprcessr Test and Verificatin (MTV)", Austin, TX, USA, 7-9 December, 2009, pp D. Breslin, G. Di Guglielm, F. Fummi, G. Pravadelli, T. Villa. The impact f EFSM cmpsitin n functinal ATPG. In "IEEE Sympsium n Design and Diagnstics f Electrnic Circuits and Systems", Liberec, Czech Republic, April 2009, pp F. Fummi; G. Pravadelli; L. Di Guglielm. The Rle f Mutatin Analysis fr Prperty Qualificatin. In "ACM/IEEE Internatinal Cnference n Frmal Methds and Mdels fr Cdesign (MEMOCODE)", Cambridge, MA, USA, July N. Bmbieri, F. Fummi, G. Pravadelli. A Mutatin Mdel fr the SystemC TLM 2.0 Cmmunicatin Interfaces. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Munich, Germany, March 2008, pp F. Fummi, V. Guarnieri, C. Marcncini, G. Pravadelli. An Optimized CLP-based Technique fr Generating Prpagatin Sequences. In "IEEE East-West Design & Test Sympsium (EWDTS)", Lviv, Ukraine, 9-13 Octber, 2008, pp A. Chepurv, G. Di Guglielm, F. Fummi, G. Pravadelli, J. Raik, R. Ubar, T. Viilukas. Autmatic generatin f EFSMs and HLDDs fr functinal ATPG, In "IEEE Internatinal 20

21 Biennal Baltic Electrnics Cnference (BEC)". Tallinn, Estnia, 6-8 Octber 2008, pp N. Bmbieri, F. Fummi, G. Pravadelli, RTL-TLM Equivalence Checking Based n Simulatin. In "IEEE East-West Design & Test Sympsium (EWDTS)". Lviv, Ukraine, 9-13 Octber 2008, pp G. Di Guglielm, F. Fummi, M. Hamptn, G. Pravadelli, F. Stefanni. The rle f parallel simulatin in functinal verificatin. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp", Incline Village, NV, USA, Nvember 2008, pp L. Di Guglielm, F. Fummi, G. Pravadelli. Vacuity Analysis by Fault Simulatin. In "ACM/IEEE Internatinal Cnference n Frmal Methds and Mdels fr C-Design (MEMOCODE)", Anaheim, CA, USA, 5-7 June 2008, pp F. Fummi, I.G. Harris, C. Marcncini, G. Pravadelli. A CLP-based Functinal ATPG fr Extended FSMs. In "IEEE Micrprcessr Test and Verificatin Wrkshp (MTV)", Austin, TX, USA, 4-6 December 2007, pp P. Destr, F. Fummi, G. Pravadelli. A Smth Refinement Flw fr C-designing HW and SW Threads. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Acrplis, Nice, France, April 2007, pp N. Bmbieri, F. Fummi, G. Pravadelli. Incremental ABV fr Functinal Validatin f TL-t- RTL Design Refinement. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Acrplis, Nice, France, April, 2007, pp G. Di Guglielm, F. Fummi, M. Jenihhin, G. Pravadelli, J. Raik, R. Ubar. On the Cmbined Use f HLDDs and EFSMs fr Functinal ATPG. In "IEEE East-West Design and Test Sympsium (EWDTS)", Yerevan, Armenia, 7-10 September 2007, pp N. Bmbieri, F. Fummi, J.P. Marques-Silva, G. Pravadelli. Twards Equivalence Checking Between TLM and RTL Mdels. In "ACM/IEEE Internatinal Cnference n Frmal Methds and Mdels fr Cdesign (MEMOCODE)", Nice, France, 30 May - 1 June 2007, pp N. Bmbieri, F. Fummi, G. Pravadelli. A Methdlgy fr Abstracting RTL Designs int TL Descriptins. In "ACM/IEEE Internatinal Cnference n Frmal Methds and Mdels fr C- Design (MEMOCODE)", Napa Valley, CA, USA, July 2006, pp N. Bmbieri, F. Fummi, G. Pravadelli. A TLM Design fr Verificatin Methdlgy. In "IEEE Ph.D. Research in Micrelectrnics and Electrnics (PRIME)", Otrant (LE), Italy, June 2006, pp G. Di Guglielm, F. Fummi, C. Marcncini, G. Pravadelli. EFSM Manipulatin t Increase High-Level ATPG, In "IEEE Internatinal Sympsium n Quality Electrnic Design (ISQED)", San Jse, CA, USA, March, 2006, pp

22 80. G. Di Guglielm, F. Fummi, C. Marcncini, G. Pravadelli. FATE: a Functinal ATPG t Traverse unstabilized EFSMs. In "IEEE Eurpean Test Sympsium (ETS)", Suthamptn, UK, May 2006, pp G. Di Guglielm, F. Fummi, C. Marcncini, G. Pravadelli. Imprving Gate-Level ATPG by Traversing Cncurrent EFSMs. In "IEEE VLSI Test Sympsium (VTS)", Berkeley, CA, USA, 30 April - 4 May 2006, pp N. Bmbieri, F. Fummi, G. Pravadelli, Incremental ABV fr TL-t-RTL Design Refinement. In "IEEE East-West Design & Test Internatinal Wrkshp (EWDTW)". Schi (Russia), September 2006, pp N. Bmbieri, F. Fummi, G. Pravadelli. On the Evaluatin f Transactr-based Verificatin fr Reusing TLM Assertins and Testbenches at RTL. In "ACM/IEEE Design, Autmatin and Test in Eurpe (DATE)", Munich, Germany, 6-10 March 2006, pp F. Fummi, C. Marcncini, G. Pravadelli. An EFSM-based Apprach fr Functinal ATPG. In "ACM Great Lakes Sympsium n VLSI (GLSVLSI)", Chicag, April, 2005, pp M. Brgatti, A. Capell, F. Fummi, J.-L. Lambert, I. Mussa, G. Pravadelli, U. Rssi. An Integrated Design and Verificatin Methdlgy fr Recnfigurable Multimedia Systems. In "IEEE Design Autmatin and Test in Eurpe Cnference (DATE) Designer's Frum", Munich, Germany, 7-11 March 2005, pp G. Di Guglielm, F. Fummi, C. Marcncini, G. Pravadelli. A Pseud-Deterministic Functinal ATPG based n EFSM Traversing. In "ACM/IEEE Internatinal Wrkshp n Micrprcessr Test and Verificatin (MTV)", Austin, TX, USA, 3-4 Nvember 2005, pp F. Fummi, G. Pravadelli, F. Tt. Cverage f Frmal Prperties based n a High-Level Fault Mdel and Functinal ATPG. In "IEEE Eurpean Test Sympsium (ETS)", Tallin, Estnia, May 2005, pp N. Bmbieri, F. Fummi, G. Pravadelli. Functinal Verificatin f Netwrked Embedded Systems. In "ACM/IEEE Internatinal Sympsium n Quality Electrnic Design (ISQED)", San Jse, CA, USA, March 2005, pp S. Brait, F. Fummi, G. Pravadelli. On the Use f a High-Level Fault Mdel t Analyze Lgical Cnsequence f Prperties. In "ACM/IEEE Internatinal Cnference n Frmal Methds and Mdels fr C-Design (MEMOCODE)", Verna, July 2005, pp G. Pravadelli. Symbad: Frmal Verificatin in System Level-based Design. In "Cngress Annuale AICA", Udine, Italy, 5-7 Octber 2005, pp A. Fedeli, F. Fummi, G. Pravadelli, U. Rssi. Symbad: Frmal Verificatin in System Levelbased Design (Extended Versin). In "IEEE East-West Design and Test Wrkshp (EWDTW)", Odessa, Ukraine, September

23 92. L. FrMay, F. Fummi, G. Pravadelli. A Timing-Accurate HW/SW C-Simulatin f an ISS with SystemC. In "IEEE/ACM/IFIP Internatinal Cnference n Hardware/Sftware Cdesign and System Synthesis (CODES+ISSS)", Stcklm, Sweden, 8-10 September 2004, pp N. Bmbieri, F. Fummi, G. Pravadelli. At-Speed Functinal Verificatin f Prgrammable Devices. In "IEEE Internatinal Sympsium n Defect and Fault Tlerance in VLSI Systems (DFT)", Cannes, France, Octber 2004, pp M. Brgatti, A. Fedeli, F. Fummi, J.L. Lambert, C. Marcncini, I. Mussa, G. Pravadelli, U.Rssi. A Verificatin Methdlgy fr Recnfigurable Systems. In "IEEE Internatinal Wrkshp n Micrprcessr Test and Verificatin (MTV)", Austin, TX, USA, 9-10 September 2004, pp F. Fummi, C. Marcncini, G. Pravadelli. Functinal Fault Cverage: the Chamber f Secrets r an Accurate Estimatin f Gate-Level Cverage?. In "IEEE Eurpean Test Sympsium (ETS)", Ajacci, France, May 2004, pp F. Fummi, C. Marcncini, G. Pravadelli. Functinal Verificatin based n the EFSM Mdel. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp (HLDVT)", Snma Valley, CA, USA, Nvember 2004, pp F.Fummi, G.Pravadelli. Lgic-Level Analysis f High-Level Faults. In "ACM Great Lake Sympsium n VLSI (GLSVLSI)", Bstn, MA, USA, April 2004, pp A.Fin, F.Fummi, M.Pncin, G.Pravadelli. A SystemC-based Framewrk fr Prperties Incmpleteness Evaluatin. In "ACM/IEEE Internatinal Wrkshp n Micrprcessr Test and Verificatin (MTV)". Austin, TX, USA, May 2003, pp A.Fin, F.Fummi, G.Pravadelli, U.Rssi, F.Tt. Mixing ATPG and Prperty Checking fr Testing HW/SW Interfaces. In "ACM Great Lakes Sympsium n VLSI (GLSVLSI)", Washingtn D.C., USA, April 2003, pp A.Fedeli, F.Fummi, G.Pravadelli, U.Rssi, F.Tt. On the Use f a High-level Fault Mdel t Check Prperties Incmpleteness. In "ACM/IEEE Internatinal Cnference n Frmal Methds and Mdels fr C-Design (MEMOCODE)", Le Mnt Saint Michel, France, June 2003, pp F.Fummi, C.Marcncini, G.Pravadelli. Redundant Functinal Faults Reductin by Sabteur Synthesis. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp (HLDVT)", San Francisc, CA, USA, Nvember 2003, pp A.Castelnuv, A.Fedeli, A.Fin, F.Fummi, G.Pravadelli, U.Rssi, F.Sfrza, F.Tt. A 1000X Speed Up fr Prperties Cmpleteness Evaluatin. In "IEEE Internatinal High Level Design Validatin and Test Wrkshp (HLDVT)", Cannes, France, Octber 2002, pp P. Azzni, A. Fedeli, F. Fummi, G. Pravadelli, U. Rssi, F. Tt. An Errr Simulatin Based Apprach t Measure Errr Cverage f Frmal Prperties. In "ACM Great Lakes Sympsium n VLSI (GLSVLSI)", New Yrk, NY, USA, April 2002, pp