Università degli Studi di Verona, Facoltà di Scienze MM. FF. NN. Curriculum Vitae

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1 Curriculum Vitae Franco Fummi:, Università di Verona Strada le Grazie, Verona tel.: ; cell.: Education First degree: Master: Ph.D.: Laurea in Electronic Engineering at Politecnico di Milano, Italy; started on October the 1st 1985, graduated on December the 20th 1990; major course in electronic engineering. Master in Information and Communication Technology at CEFRIEL Research Center Milano, Italy; started on October the 1st 1990, graduated on September the 23rd 1991; major course in VLSI design. Ph.D. in Electronic and Communication Engineering at Politecnico di Milano, Italy; started on January the 1st 1992, graduated on March the 15th 1995; thesis on the Testability of VLSI Circuits with a high Functional Complexity. 2 Academic career Research Assistant: in Computer Science from May to December 1994 at University of Victoria, B.C., Canada. Post-Doc.: in Computer Science and Automation from May 1995 at the Dipartimento di Elettronica e Informazione of Politecnico di Milano, Italy. Assistant Professor: in Computer Architecture from December the 13th 1996 at the Dipartimento di Elettronica e Informazione of Politecnico di Milano, Italy. Associate Professor: in Computer Architecture from November the 2nd 1998 at the Computer Science Department of Università di Verona, Italy. Full Professor: in Computer Architecture from July the 14th 2000 at the Computer Science Department of Università di Verona, Italy. 3 Teaching activity From 1994 to 1998 he teaches as adjunct professor courses on Introduction to Computer Science at: 1

2 Università Carlo Cattaneo di Castellanza; Politecnico di Milano, branches of Milano, Cremona and Piacenza. From 1999 to 2008 he teaches at the Computer Science Faculty of Università di Verona the following courses: Computer Architecture, bachelor degree in Computer Science; Advanced Computer Architecture, degree in Computer Science; VLSI Design, degree in Computer Science. From 2009 he teaches at the Computer Science Faculty of Università di Verona the following courses: Computer Architecture, bachelor degree in Computer Science; Embedded Systems Software, degree in Computer Engineering; Embedded Systems Design, degree in Computer Engineering; He is coauthor of the book Progettazione Digitale (Digital Design), McGraw-Hill From 1999 he has been supervisor of more than 60 master students and 13 Ph.D. students. 4 Research activity He is leading the Electronic Systems Design (ESD) group at the Università di Verona ( currently composed of more than 20 people and working on hardware description languages and electronic design automation methodologies for modeling, verification, testing and optimization of embedded systems. The main research directions exploited are: Embedded system verification (Static verification - Dynamic verification- Semi-formal verification - Hybrid and real-time systems); Networked embedded systems (System/Network co-simulation - System/Network co-design - QoSenabled design - Sensor networks and M2M systems); Embedded systems design (TLM-RTL synthesis and abstraction - RTL-to-SW abstraction - TLM transactor generation - Device-driver generation - Embedded SW for multicore systems - Middleware-based design). In relation to such research areas, he published more than 230 papers; three of them received the best paper award respectively at IEEE EURODAC'96, IEEE DATE'99 and IEEE FDL 11. He coordinated: 25 research projected commissioned by companies; Siemens, STMicroelectronics, TelecomItalia, Neuricam, Sitek, Telefin, Infracom, Data4, RCH, etc.; 6 projects funded by national foundations; MIUR, CNR, Regione Veneto, etc.; 2

3 8 projects funded by the European Commission; FP5-IST (SYMBAD), FP IST (VERTIGO), FP IST (ANGEL), FP IST (COCONUT), FP7-REGPOT (CREDES), FP IST (COMPLEX), FP7- ICT (SMAC), FP7-ICT (TOUCHMORE). The global funding received has been more than 3M. He is part of the Program Committee of the following conferences: ACM/IEEE Design Automation Conference (DAC), IEEE European Test Symposium (ETS), IEEE Microprocessor Test Verification (MTV), IEEE Design and Test in Europe (DATE), IEEE Formal Methods and Models for Codesign (MEMOCODE), IEEE High Level Design Verification and Test (HLDVT), IEEE Embedded System Week (ESWeek), Forum on Specification and Design Languages (FDL), IEEE Very Large Scale Integration (VLSI-SOC), Haifa Verification Conference (HVC), IEEE Industrial Embedded Systems (SIES). He has had the following roles in conference organization: IEEE ITC'03 invited speaker panel IEEE ETS'03 invited speaker panel IJPP'05 special issue chair IEEE EWDTW'05 keynote speaker IEEE HASE'05 keynote speaker IEEE HLDVT'05 European liaison chair IEEE MEMOCODE'05 local chair IEEE DATE'06 "simulation and validation" topic co-chair IEEE SFM-06:HV Ph.D. school invited speaker IEEE EWDTW'06 invited speaker IEEE DATE'07 "simulation and validation" topic co-chair ICESC'07 special session chair IEEE CODES-ISS'07 "simulation and verification" topic chair IEEE DATE'08 "simulation and validation" topic chair IEEE CODES-ISS'08 "simulation and verification" topic chair IEEE MEMOCODE'08 keynote speakers chair IEEE MICRO'08 invited tutorial IEEE DATE'09 "simulation and validation" topic chair IEEE DATE'09 invited session 3

4 IEEE CODES-ISS'09 "simulation and verification" topic chair IEEE ESWeek'09 finance chair IEEE DATE'10 European project Chair IEEE DATE'10 invited speaker panel IEEE ESWeek'10 finance chair IEEE CODES-ISS'10 "simulation and verification" topic chair IEEE VLSI-SOC'10 "Prototyping, Validation, Verification, Modeling and Simulation" topic chair IEEE SIES'10 program chair IEEE DATE'11 European project Chair IEEE DATE'11 "simulation and validation" topic co-chair IEEE VLSI-SOC'11 "Prototyping, Validation, Verification, Modeling and Simulation" topic chair IEEE ESWeek'11 finance co-chair FDL'11 invited speaker panel IEEE DATE'12 "simulation and validation" topic co-chair IEEE VLSI-SOC'12 "Prototyping, Validation, Verification, Modeling and Simulation" topic chair IEEE CODES-ISSS'12 program chair IEEE HLDVT 12 special session chair IEEE DATE 13 tutorial chair IEEE DATE 13 "simulation and validation" topic chair 5 Academic organization activity : Vice-rector for the IT services of the Università di Verona. 2004: Vice-head of the faculty of Sciences of the Università di Verona : Member of the board of the Università di Verona. 2007: Member of the board of Consorzio per gli Studi Universitari in Verona : Director of the master in Design and Managing of Networked Systems at the Department of Computer Science of the Università di Verona : President of the didactic commission of the senate of the Università di Verona : Member of the senate of the Università di Verona. 4

5 6 Professional activity : Member of the technical committee of the Scientific Park of Verona : Member of the board of the telecommunication company MiPiace.com : Director of the Embedded Systems Design unit of the Scientific Park of Verona : Member of the technical advisor board of the EDA company Certess : Co-founder and president of the EDA company EDALab ( spin-off of the Università di Verona focused on networked embedded systems design and tools.member of the technical committee of the Scientific Park of Verona. 7 Most significant publications 1. L.Di Guglielmo, F. Fummi, G. Pravadelli, F.Stefanni, S. Vinco, UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous system integration «IEEE Transactions on Computers», in press, V. Izosimov, G.Di Guglielmo, M. Lora, G. Pravadelli, F. Fummi, Z. Peng, M. Fujita, Time-constraint-aware optimization of assertions in embedded software «Journal of Electronic Testing: Theory and Applications», in press, N. Bombieri, F. Fummi, V. Guarnieri, FAST: an RTL Fault Simulation Framework based on RTL-to-TLM Abstraction «Journal of Electronic Testing: Theory and Applications», in press, V. Guarnieri, G.Di Guglielmo, N.Bombieri, G. Pavadelli, F. Fummi, H. Hantson, J. Raik, M. Jenihhin, R. Ubar On the Reuse of TLM Mutation Analysis at RTL «Journal of Electronic Testing: Theory and Applications», in press, N. Bombieri, F. Fummi, V. Guarnieri, F. Stefanni, S. Vinco, HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels «An International Journal on Design Automation for Embedded Systems», vol. 16, n. 2, 2012, pp N. Bombieri, F. Fummi, G. Pravadelli, Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions «IEEE Transactions on Computers», vol. 60, n. 12, 2011, pp G.Di Guglielmo, L.Di Guglielmo, F.Fummi, G.Pravadelli, Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs «Journal of Electronic Testing: Theory and Applications», vol. 27, n. 2, 2011, pp N.Bombieri, M.Ferrari, F.Fummi, G.Di Guglielmo, G.Pravadelli, F.Stefanni, A.Venturelli, HIFSuite: Tools for HDL Code Conversion and Manipulation «Eurasip Journal on Advances in Signal Processing», vol.2010, n /2010/436328, 2010, pp N.Bombieri, F.Fummi, D.Quaglia, System/Network Design Space Exploration based on TLM for Networked Embedded Systems «ACM Transactions on Embedded Computing Systems», vol.9, n.4, 2010, pp.37:1-37: F.Fummi, M.Loghi, M.Poncino, G.Pravadelli, A Co-Simulation Methodology for HW/SW Validation and Performance Estimation «ACM Transactions on Design Automation of Electronic Systems», vol.14, n.2, 2009, pp.23:1-23: F.Stefanni, D.Quaglia, F.Fummi, SystemC Simulation of Networked Embedded Systems «Languages for Embedded Systems and their Applications», Prof.Dr.Martin Radetzki, Springer Science, 2009, pp

6 12. G.Di Guglielmo, F.Fummi, C.Marconcini, G.Pravadelli, Test generation based on CLP «Micro electronic and mechanical systems», Kenichi Takahata, I-Tech, 2009, pp N.Bombieri, F.Fummi, G.Pravadelli, Reuse and Optimization of Testbenches and Properties in a TLM-to- RTL Design Flow «ACM Transactions on Design Automation of Electronic Systems», vol.13, n.3, 2008, pp.47:1-47: F.Fummi, G.Perbellini, eepc: an EPCglobal-compliant Embedded Architecture for RFID-based Solutions «Journal of Communications», vol.2, n.7, 2007, pp N.Bombieri, A.Fedeli, F.Fummi, G.Pravadelli, Hybrid Incremental Assertion-Based Verification for Functional Validation in TLM Design Flows «IEEE Design &Test of Computers», vol.24, n.2, 2007, pp G.Di Guglielmo, F.Fummi, C.Marconcini, G.Pravadelli, Improving High-Level and Gate-Level Testing with FATE: a Functional ATPG Traversing Unstabilized EFSMs «IET Computers & Digital Techniques», vol.1, n.3, 2007, pp A.Fedeli, F.Fummi, G.Pravadelli, Properties Incompleteness Evaluation by Functional Verification «IEEE Transactions on Computers», vol.56, n.4, 2007, pp F.Fummi, M.Loghi, G.Perbellini, M.Poncino, SystemC co-simulation for core-based embedded systems «An International Journal on Design Automation for Embedded Systems», vol.11, 2007, pp F.Fummi, G.Pravadelli, Too Few or too Many Properties? Measure it by ATPG! «Journal of Electronic Testing: Theory and Applications», vol.23, n.5, 2007, pp N.Bombieri, F.Fummi, G.Pravadelli, Hardware Design and Simulation for Verification, M.Bernardo, A.Cimatti «Formal Methods for Hardware Verification», Springer, 2006, pp F.Fummi, G.Pravadelli, Test Generation: A Symbolic Approach, Z.Peng; M.Sonza Reorda; M.Violante «System-level Test and Validation of Hardware/Software Systems», Springer, 2005, pp F.Fummi, C.Marconcini, G.Pravadelli, Logic-Level Mapping of High-Level Faults «Integration, the VLSI Journal», vol.38, n.3, 2004, pp A.Fin, F.Fummi, A Remote Methodology for Embedded Systems Design and Validation «An International Journal on Design Automation for Embedded Systems», vol. 8, 2003, pp A.Fin, F.Fummi, LAERTE++: An Object Oriented High-Level TPG for SystemC Designs, Grimm C. «Languages for System Specification», Kluwer Academic Publishers, 2004, pp A.Fin, F.Fummi, G.Pravadelli, SystemC as a Complete Design and Validation Environment, W.Mueller, W.Rosenstiel, J.Ruf, «SystemC - Methodologies and Application», Norwell, Kluwer Academic Publishers, 2003, pp F.Ferrandi, F.Fummi, G.Pravadelli, D.Sciuto, Identification of Design Erros through Functional Testing «IEEE Transactions on Reliability», vol. 52, n. 4, 2003, pp L. Benini, D.Bertozzi, D.Bruni, N.Drago, F.Fummi, M.Poncino, SystemC Co-Simulation and Emulation of Multi-Processor Systems-on-Chip «IEEE Computer», vol. 36, n. 4, 2003, pp F.Ferrandi, F.Fummi, D.Sciuto, Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications «IEEE Transactions on Computers», vol.51, n.2, 2002, pp G.Biasoli, F.Ferrandi, A.Fin, F.Fummi, D.Sciuto, Behavioral Test Generation for the Selection of BIST Logic «Journal of Systems Architecture», n.47, 2002, pp

7 30. F.Ferrandi, A.Fin A, F.Fummi, D.Sciuto, Functional Test Generation: Overview and Proposal of a Hybrid Genetic Approach, R.Drechsler «Evolutionary Algorithms for System Design», Kluwer Academic Publishers, 2002, pp F.Fummi, M.Boschini, X.Yu, E.M.Rudnick, Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach «Journal of Electronic Testing: Theory and Applications», vol.17, 2001, pp F.Fummi, D.Sciuto, A Hierarchical Approach to Test Generation for Large Controllers «IEEE Transactions on Computers», vol.49, n.4, 2000, pp G.Buonanno, F.Fummi, D.Sciuto, An Extended UIO-Based Method for Protocol Conformance Testing «Journal of Systems Architecture», vol.46, 2000, pp F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto, Symbolic Optimization of FSM Networks Based on Redundancies Identification and Removal «IEEE Transactions on CAD/ICAS», vol.19, n.7, 2000, pp D.Corvino, I.Epicoco, F.Ferrandi, F.Fummi, D.Sciuto, Controller and Data-Path Separation by VHDL Restructuring «The Best of FDL'98 and FDL'99», Jean Mermet, Kluwer Academic Publishers, F.Fummi, D.Sciuto, M.Serra, Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal «IEEE Transactions on Computers», vol.48, n.12, 1999, pp F.Fummi, D.Sciuto, C.Silvano, Automatic Generation of Error Control Codes for Computer Applications «IEEE Transactions on VLSI Systems», vol.3(6), 1998, pp C.Alippi, F.Fummi, V.Piuri, M.Sami, D.Sciuto, Testability Analysis and Behavioral Testing of the Hopfield Neural Paradigm «IEEE Transactions on VLSI Systems», vol.3, n.6, 1998, pp F.Fummi, D.Sciuto, A Complete Testing Strategy Based on Interacting and Hierarchical FSMs «Integration, the VLSI Journal», vol.23, 1997, pp F.Fummi, U.Rovati, D.Sciuto, Functional Design for Testability of Control-Dominated Architectures «ACM Transactions on Design Automation of Electronic Systems», vol.2, 1997, pp F.Ferrandi, F.Fummi, E.Macii, M.Poncino, D.Sciuto, Testing Core-Based Digital Systems: A Symbolic Methodology «IEEE Design &Test of Computers», vol.4(13), 1997, pp G.Buonanno, F.Fummi, D.Sciuto, F.Lombardi, FsmTest: Functional Test Generator for Sequential Circuits «Integration, the VLSI Journal», vol.20, 1996, pp G.Buonanno, F.Fummi, D.Sciuto, Functional Fault Models and Gate Level Coverage for Sequential Architectures «Journal of Microelectronic System Integration», vol.4, 1996, pp G.Buonanno, F.Fummi, D.Sciuto, TIES: a Testability Increase Expert System for VLSI Design «Journal of Electronic Testing: Theory and Applications», vol.6, 1995, pp C.Bolchini, F.Fummi, D.Sciuto, Two-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues «Journal of Microelectronic System Integration», vol.1, 1993, pp Franco Fummi 7