Equivalence Checking. Sean Weaver

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1 Equivlene Cheking Sen Wever

2 Equivlene Cheking Given two Boolen funtions, prove whether or not two they re funtionlly equivlent This tlk fouses speifilly on the mehnis of heking the equivlene of pirs of omintionl iruits

3 Types of Ciruits Comintionl Ciruit Digitl iruit No stte-holding elements No feedk loops Output is funtion of the urrent input Sequentil Ciruit Cn hve stte-holding elements Cn hve feedk loops Must trnsform (e.g. BMC) into omintionl iruit for equivlene heking

4 Ciruit Equivlene Cheking Cheking the equivlene of pir of iruits For ll possile input vetors (2 #input its ), the outputs of the two iruits must e equivlent Testing ll possile input-output pirs is CoNP- Hrd However, the equivlene hek of iruits with similr struture is esy [1] So, we must e le to identify shred struture, nd we need tool tht n effiiently solve NP-Complete prolems (Stisfiility solver, BDDs, Gröner Bsis solver, et.) 1. E. Golderg, Y. Novikov. How good n resolution sed ST-solver e? ST-2003, LNCS 2919, pp

5 Equivlene Cheking Uses Forml Verifition Prove whether low level implementtion mthes high level, or mthemtil, speifition Verifying Compiler Mintin the funtionlity of generted ode Version Control Use previous implementtions to mintin the orretness of future implementtions Funtionl Inversion Prove whether enode nd deode funtions re inverses of eh other

6

7 Given tht the input vriles (, B, C) re equivlent, verify output vriles (X, Y) re equivlent. 1. Conjoin speifition nd implementtion formuls, 2. dd the equivlene heking onstrint. Result This is lled miter formul. If unstisfile, the speifition nd implementtion re equivlent. ST solver n tell us this.

8 Exmple: re These Ciruits Equivlent? #1 C x #2 O 1 2 O 3 8 y

9 Exmple: Outline Rndom Simultion - Send rndom vetors through the two iruits, olleting pirs of ndidte equivlent nodes nd/inverter Grph Find more equivlent nodes y reting the IG of the iruits ST Sweeping Use ndidte equivlent nodes to guide ST serhes, merging IG nodes whih redues the omplexity of future ST serhes

10 Identifying Shred Struture n internl node in the first iruit my e equivlent to n internl node in the seond iruit Detet y using rndom simultion Perolte rndom vetors through oth iruits (fst trik - use 64-it words) Prtition nodes into equivlene lsses This n detet potentilly mny, high proility, ndidte equivlent nodes

11 Rndom Simultion #1 C x #2 O 1 2 O 3 8 y

12 Rndom Simultion #1 C 1 C 1 #2 O 0 O x y Bukets 1,4,7,8 0,2,3,5,6 Rndom Vetor: {=T, =T, =T}

13 Rndom Simultion #1 C 1 #2 O 0 O Rndom Vetor: {=F, =F, =F} x y Bukets 1,4 7,8 2,3,5,6 0

14 Rndom Simultion #1 C 1 #2 O 0 O Rndom Vetor: {=F, =F, =T} x y Bukets 1,4 7,8 2,6 3,5

15 Rndom Simultion #1 C x Bukets #2 O 1 2 O Rndom Vetor: {=T, =T, =F} 3 8 y 7,8 2,6 3,5

16 Exmple: Outline Rndom Simultion - Send rndom vetors through the two iruits, olleting pirs of ndidte equivlent nodes nd/inverter Grph Find more equivlent nodes y reting the IG of the iruits ST Sweeping Use ndidte equivlent nodes to guide ST serhes, merging IG nodes whih redues the omplexity of future ST serhes

17 Identifying Shred Struture Rndom simultion is proilisti nd/inverter Grph (IG) [2] Simple dt struture used to represent omintionl iruits Opertions re fst (dd node, merge nodes) 2.. Kuehlmnn, V. Pruthi, F. Krohm, nd M.K. Gni. Roust Boolen Resoning for Equivlene Cheking nd Funtionl Property Verifition. IEEE Trns. CD, Vol. 21, No. 12, pp (2002)

18 nd/inverter Grph #1 C x #2 O 1 2 O 3 8 y

19 nd/inverter Grph #2 O 1 2 O 3 8 y Use the IG dt struture to store iruits IG n quikly dd nodes nd merge equivlent nodes Struturl hshing is used Merging pir of equivlent nodes n use other nodes to e merged utomtilly, without need for ST proof

20 nd/inverter Grph #2 1 2 O 3 8 y Nodes represent ND gtes Edges represent inputs to n ND gte Edges my e inverted OR gtes must e onverted to ND gtes during IG retion

21 nd/inverter Grph # y

22 nd/inverter Grph # y

23 nd/inverter Grph # x 5 # y

24 nd/inverter Grph # x 5 # y

25 nd/inverter Grph # x 5 # y

26 nd/inverter Grph # x 5 # y

27 nd/inverter Grph # x 5 # y

28 Exmple: Outline Rndom Simultion - Send rndom vetors through the two iruits, olleting pirs of ndidte equivlent nodes nd/inverter Grph Find more equivlent nodes y reting the IG of the iruits ST Sweeping Use ndidte equivlent nodes to guide ST serhes, merging IG nodes whih redues the omplexity of future ST serhes

29 ST Sweeping Use ST to prove whether or not the ndidte equivlent nodes, from the rndom simultion phse, re equivlent The ndidte equivlent nodes re used s ut points Generte ST prolems tht re solved from inputs to outputs using the ndidte equivlent nodes s guide [3] 3.. Kuehlmnn. Dynmi Trnsition Reltion Simplifition for Bounded Property Cheking. In ICCD, 2004

30 ST Instnes Crete one ST instne for one (or more) pir of ndidte equivlent nodes ST instne enodes miter iruit Eh ST serh n result in the merger of equivlent IG nodes, reduing the omplexity of the IG

31 nd/inverter Grph # x 5 # y

32 Equivlenes x y Bukets 7?= 8 2?= 6 3?= 5

33 ST Solver Sys 3 = x y Bukets 7?= 8 2?= 6 3 = 5

34 Merge 3 nd x y Bukets 7?= 8 2?= 6 3 = 5

35 ST Solver Sys 2 = x y Bukets 7?= 8 2 = 6 3 = 5

36 Merge 6 nd x y Bukets 7?= 8 2 = 6 3 = 5

37 7 Struturlly Hshes to x y Bukets 7 = 8 2 = 6 3 = 5

38 x nd y Verified Equivlent x y Bukets 7 = 8 2 = 6 3 = 5

39 Exmple: Outline Rndom Simultion - Send rndom vetors through the two iruits, olleting pirs of ndidte equivlent nodes nd/inverter Grph Find more equivlent nodes y reting the IG of the iruits ST Sweeping Use ndidte equivlent nodes to guide ST serhes, merging IG nodes whih redues the omplexity of future ST serhes

40 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

41 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

42 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

43 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

44 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

45 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

46 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

47 Slides tken from. Biere. ST in Forml Hrdwre Verifition.

48 Cryptol Cryptol is Hskell sed speifition lnguge for writing rypto-lgorithms Creted y Glois Connetions In. with support from NS ryptogrphers Cryptol speifitions n e trnsformed into IGs Cryptol lso hs uilt in equivlene heker (jig) Cryptol speifitions n e used to verify vrious implementtions C ode, VHDL, et.

49 Results - ES Verified Cryptol speifition of full rnk ES-128 funtionlly equivlent to NIST ompetition optimized C-ode Cryptol-ES IG hs 934,000 nodes NIST-ES IG hs 1,482,000 nodes 190,000 equivlent nodes found Using tehniques desried here plus speil ST heuristis < 1 minute on 2 GHz Pentium III

50 Results - VdW Vn der Werden numers W(k,r)=n Ple numers 1... n into k ukets so tht no rithmeti progression of length r exists in ny uket ssertion y Dr. Mihl Kouril W(2,6) = 1132 This is quite fet euse now only 6 numers re known nd no new ones hd een found sine 1979

51 Results VdW Dr. Kouril's solver is written in VHDL, runs on luster of FPGs t UC The solver hs exhusted the serh spe How to give onfidene tht VHDL ode is orret? Use equivlene heking!

52 Results VdW Wrote Cryptol speifitions for the three min VHDL funtions used Used Xilinx tools nd Cryptol to generte IGs from the VHDL ode Used the Cryptol equivlene heker (jig) to verify the VHDL ode Eh funtion hs possile inputs Totl time for ll three heks < 30 minutes

53 Referenes. Biere. Invited tlk - ST in Forml Hrdwre Verifition. 8th Intl. Conf; on Theory nd pplitions of Stisfiility Testing (ST'05), St. ndrews, Sotlnd, (2005). D. Brnd. Verifition of Lrge Synthesized Designs. Pro. Intl Conf. Computer-ided Design pp (1993). E. Golderg, Y. Novikov. How good n resolution sed ST-solver e? ST-2003, LNCS 2919, pp F. Krohm,. Kuehlmnn, nd. Mets. The Use of Rndom Simultion in Forml Verifition. Pro. of Int'l Conf. on Computer Design, Ot (1996).. Kuehlmnn, F. Krohm. Equivlene Cheking Using Cuts nd Heps. In Design utomtion Conferene (1997).. Kuehlmnn, V. Pruthi, F. Krohm, nd M. K. Gni. Roust Boolen Resoning for Equivlene Cheking nd Funtion Property Verifition. IEEE Trns. CD, Vol. 21, No. 12, pp (2002).. Kuehlmnn. Dynmi Trnsition Reltion Simplifition for Bounded Property Cheking. In ICCD (2004). J. Lewis. Cryptol, Domin Speifi Lnguge for Cryptogrphy. (2002).

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