ENVIRONMENT FOR SIGNAL PROCESSING APPLICATIONS DEVELOPMENT AND PROTOTYPING Brigitte SAGET, MBDA
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1 ENVIRONMENT FOR SIGNAL PROCESSING APPLICATIONS DEVELOPMENT AND PROTOTYPING Brigitt SAGET, MBDA Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
2 ESPADON objctivs Dfin an advancd dvlopmnt mthodology and spcify a Dsign Environmnt to support this mthodology Slct th commrcial tools to b intgratd in th ESPADON Dsign Environmnt Implmnt th ESPADON Dsign Environmnt with its slctd tools Bnchmark th ESPADON mthodology and Dsign Environmnt with Signal Procssing Tst Applications Dmonstrat th bnfit in trms of dvlopmnt cost and dvlopmnt tim rduction. Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
3 Military systms dvlopmnt contxt YEARS Billions of FF USA Billions of ECUs GFlops/s 10 GFlops/s 100 FRANCE A fw mods PROCESSING POWER UK 10 Multimods Extndd Multimods FUNCTIONS NETHERLANDS INCREASED COMPLEXITY SHRINKING BUDGETS CHANGES IN ELECTRONIC INDUSTRY INCREASED COMPETITION (USA, WORLDWIDE) DEVELOPMENT OF NEW MILITARY SYSTEMS Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
4 Tchnology insrtion concpt Prformanc "log" scal Convntional Dvlopmnt Mthod : P: Expctd lvl of prformanc of th final product Prototyp Final product MOORE S LAW : Elctronics Prformanc Improvmnt : 2 X vry 2 yars 1 rst Prototyp 2 nd Prototyp T nd of dvlopmnt Final product Itrativ Dvlopmnt Mthod : Rtrofit Rtrofit Programm Start Tim Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
5 Virtual Prototyping & Tchnology Insrtion FUNCTIONAL DESIGN CODE FUNCTIONAL SIMULATION Modls FUNCTIONAL REFERENCE MODEL PERFORMANCE/ BEHAVIOURAL SIMULATION Modls HARDWARE / SOFTWARE ARCHITECTURAL DESIGN HARDWARE/SOFTWARE COSIMULATION Modls HARD/SOFT CODEVELOPMENT HARDWARE SOFTWARE VIRTUAL PROTOTYPE NEW SOFTWARE RE-USED SOFTWARE AUTO-GEN CODE NEW HARDWARE RE-USED HARDWARE COTS Tchnology insrtion, Manufactur, Intgration & Tst Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
6 Th ESPADON Mthodology Plan SP Dvlopmnt Risk drivn dvlopmnt lif cycl «Modl Yar» approach Rus and capitalisation Support for: Trac-ability cost prformanc trad off From Prvious Procss From Systm Dvlopmnt R q u i r m n t s R i s k R g i s t r D v l o p m n t P l a n Spcification Functional Dsign Architctural Dsign Implmntation Systm Rviw Rquirmnts Risk Analysis Dfinition Dvlopmnt Validation Dvlopmnt Plan Rviw To Systm Dvlopmnt Risk Rgistr To Nxt/Prvious Procss Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
7 From Prvious Procss From Systm Dvlopmnt Rquirmnts Spiral Modl Rprsntation Risk Analysis Dfinition Dvlopmnt Validation Risk Rgistr Risk drivn dvlopmnt lif cycl «Modl Yar» approach Rus and capitalisation Support for: Trac-ability Cost prformanc trad off Th ESPADON Mthodology R q u i r m n t s Phas 1: Analysis and Slction of th rquirmnts allocatd to SP Subsystm R i s k R g i s t r Plan SP Dvlopmnt D v l o p m n t Dvlopmnt Exampl Plan of risk: Softwar dvlopmnt Rviw SP production GO/NO GO To Nxt/Prvious Procss P l a n Phas 4: Validation of SP Subsystm Exampl of risk: Ral tim prformanc Exampl of risk: Computing powr Exampl of risk: SP algorithms,... Choic validation Validation of prformanc modl Validation of virtual prototyp Validation of manufacturd computr Simulation Spcification Functional Dsign SP Functional dfinition Architctural Dsign Implmntation Systm Rviw To Systm Dvlopmnt Phas 2: Dfinition of SP Subsystm INCREASING LEVEL OF REFINEMENT Rfinmnt of architctur choic Computr architctur choic Hardwar/Softwar dscription Mapping dscription Functional modlling Placmnt of functions Dvlopmnt of prformanc modl Softwar/Hardwar dvlopmnt (synthsis) Production Intgration Phas 3: Dvlopmnt of SP Subsystm Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
8 Tool List Projct Planning: ARTEMIS - KUB Sistm SDN. BHD. Rquirmnts Analysis: RTM - Marconi Systms Tchnology Inc. RDD100 - Ascnt Logic (US) DOORS - Quality Systms Softwar Ltd. Cost Estimation: PRICE - Lockhd (US) KNOWLEDGE - Softwar Productivity Rsarch Prformanc Simulation: BONES - Cadnc Dsign Systms Inc (US) SES/WORKBENCH - SES (US) OPNET - MIL 3 (US) COSMOS - Omniviw (US) MODLINE - Simulog (Fr) High Lvl Simulation: SPW - Cadnc Dsign Systms (US) RIPPEN - Orincon (US) SYSTEMVIEW - Elanx Inc (US) GEDAE - Lockhd Martin ATL (US) PTOLEMY - UCB (US) MATLAB - Th Math Works Inc (US) MATLAB/SIMULINK - Th Math Works Inc (US) COSSAP - Synopsys Inc (US) HP ESOF - HP Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002 High Lvl Simulation (continud): DSP STATION - Mntor (US) DSP CANVAS - Angls Dsign Systm (US) HYPERSIGNAL BLOCK DIAGRAM - Hyprcption (US) MUSTIG - Grsilog (Fr) PEAKWARE - Matra Systms t Information Control Simulation/FSM: STATEMATE- I-Logix Inc. MATRIXX - Intgratd Systms Inc. SYNCCHART/ESTEREL - Simulog (Fr) OBJECTGEODE - Vrilog (Fr) Co-dsign/co-simulation: FELIX/VCC - Cadnc Dsign Systms Inc (US) EAGLEI - Synopsys (US) Samlss - Mntor (US) COWARE - CoWar N2C (US) AREXSYS - Arxsys (Fr) Configuration Managmnt: CLEARCASE - Rational (US) RCS/CCS - Frwar Miscllanous: 02 - Ardnt softwar (US) OBJECTSTORE - Objct Dsign (US) VERSANT - Vrsant (US) RATIONAL ROSE - Rational Softwar Corp.
9 Tools Slctd - Rapid Prototyping Rquirmnts Analysis (RDD100, DOORS) COST ESTIMATION (PRICE) Extrnal Tools EDE Framwork Configuration Mgmnt (CVS, Clarcas) Ptolmy Matlab Simulink/RTW Targt- Porting Kit VSIP GEDAE MPI-RT Algorithm Prototyping Functional Dsign Architctural Dsign Implmntation (Rapid Prototyping) Libraris Standards Rang of Targt H/W Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
10 Tools Slctd - Virtual Prototyping Functional Dsign/Simulation.g. Ptolmy/GEDAE Currnt proposition Partitioning/Mapping Procss Procssors FPGA IP authoring tool g Handl C/ ART DSP Libs Linking Opt. Libs Rang of Targt H/W Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
11 Plannd Solution for Virtual Prototyping Functional Simulation Architctur Charactrisation Data books, IP Systm Bhaviour Architctur Dfinition Bhavioural Libraris Mapping Prformanc Simulation Architctur Libraris Communication Rfinmnt Softwar Dsign Links to Implmntation Hardwar Dsign OS, drivrs & Lgacy cod «C» Co Vrification HDL IP Libraris Systm C, VHDL, VERILOG ESPADON Platform Intgration Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
12 Rsults Dfinition of a procss and a mthodology addrssing obsolscnc and COTS insrtion issus through rapid and virtual prototyping, for Signal Procssing applications Ovrviw of th rquird tchniqus and availabl tchnologis and tools Dmonstration of rsulting productivity gains through rprsntativ radar & sonar bnchmarks (adaptiv bamforming) Dmonstratd x1.4 to x 16 Productivity (V0) Bnchmark of th procss, stimatd productivity of x7.5 (V1) Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
13 ESPADON Dmonstratd Bnfits Rduction of dvlopmnt cost and tim productivity improvmnt : cod gnration rduction of rrors : arly validation by simulation daling with lat changs: dlaying th nd for hardwar prototyps Rduction of programm risks risk drivn procss incrmntal approach : simulation and prototyping Mitigation of obsolscnc problms / Rtrofit tchnology insrtion through rapid prototyping procss basd on a functional modl and cod gnration facilitat th porting of an application on diffrnt architcturs : PPC => FPGA Facilitation of collaborativ dvlopmnts complxity managmnt rus libraris opn, modular architcturs and standards Atlir CNES «Composants commrciaux pour l informatiqu mbarqué», Toulous, 12 Juin 2002
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