Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and

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1 Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and Simulink targeting ASIC/FGPA. Previously Worked as logic design engineer in RAFAEL-Leshem and Extricom Ltd., on design for XILINX/Altera FPGAs.

2 Implementing HW/SW Model Based Design In MATLAB And Simulink Targeting XILINX Zynq-7000 Soc Eli Levi, B.Sc.EE. MATLAB & Simulink Application Engineering HDL Code Generation and Verification, FPGA workflow Systematics Limited

3 Agenda: Sneak-peek into the Demo ZYNQ design challenges Making ZYNQ programming easier Model-Based Design Integrated HW / SW design flow Live Demo

4 Sneak Peek into the Demo So, what are we going to have by the end of this session? An FPGA fabric based shifting L.E.D s, controlled by an Embedded ARM core via the AXI interface FPGA In the Loop, Processor in the loop. Configurable from a Laptop connected with the TCP/IP protocol

5 Agenda: Sneak-peek into the Demo Zynq design challenges Making Zynq programming easier Model-Based Design Integrated HW / SW design flow Live Demo

6 Zynq Design Challenge ARM Processor C-Code Software Interface FPGA HDL Code Hardware

7 Zynq Design Challenge - ARM ARM Processor C-Code Software Properties: Typically programmed in C Often runs a Linux-based operating system Well-established workflows exist Challenges: FPGA Designers are not familiar with processor programming What should run on the processor vs. the FPGA?

8 Zynq Design Challenge - FPGA FPGA HDL Code Hardware Properties: Typically programmed in VHDL/Verilog Established workflows exist Challenges: DSP/Processor programmers are not familiar with FPGA Design What should run on the FPGA vs. the processor?

9 Zynq Design Challenge - Interface Interface Properties: Zynq uses standard AXI interface between FPGA and ARM Challenges: No established rules for hooking up the interface Different flavors of AXI for different bandwidth requirements

10 Zynq Design Challenge Solution? So, how can we address these challenges and get our project onto Zynq quickly? Model-Based Design provides a single environment from requirements to prototype A guided workflow for hardware and software development RESEARCH REQUIREMENTS DESIGN Environment Models Physical Components Algorithms IMPLEMENTATION C, C++ VHDL, Verilog ARM FPGA INTEGRATION TEST & VERIFICATION

11 Agenda: Sneak-peek into the Demo Zynq design challenges Making Zynq programming easier Model-Based Design Integrated HW / SW design flow Live Demo

12 Traditional Design of a HW/SW System Research & Requirements Hardware Requirements Design Realization Testing Software Requirements Design Realization Testing Integration, Test & Certification The problem: The testing of the HW/SW integration is performed in the late stage

13 Model-Based Design RESEARCH REQUIREMENTS DESIGN Environment Models Physical Components Algorithms IMPLEMENTATION TEST & VERIFICATION Model multi-domain systems Explore and optimize system behavior in floating point and fixed point Collaborate across teams and continents Generate efficient code Explore and optimize implementation tradeoffs C, C++ ARM INTEGRATION VHDL, Verilog FPGA Automate regression testing Detect design errors Support certification and standards

14 Zynq Design Challenges ARM Processor C-Code Software Interface FPGA HDL Code Hardware FPGA Designers not familiar with programming processors DSP/Processor programmers not familiar with FPGAs What should run on the FPGA vs. what should run on the ARM? No established rules for hooking up the interface between FPGA and ARM processor

15 High-Level Zynq Design Flow RESEARCH REQUIREMENTS DESIGN User defines partitioning Environment Models Physical Components Algorithms IMPLEMENTATION TEST & VERIFICATION MathWorks automates code and interface-model generation C, C++ ARM INTEGRATION VHDL, Verilog FPGA MathWorks automates the build and download through the Xilinx tools

16 Agenda: Sneak-peek into the Demo Zynq design challenges Making Zynq programming easier Model-Based Design Integrated HW / SW design flow Live Demo

17 Integrated HW / SW design flow MATLAB and Simulink Algorithm and System Design HW HDL IP Core Generation SW HDL IP Core Generation Simulink Model AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Programmable Logic IP Core

18 A X I 4 - L i t e Integrated HW / SW design flow MATLAB and Simulink Algorithm and System Design AXI Lite Accessible Registers HDL IP Core Generation AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Embedded System Integration Programmable Logic IP Core Embedded System Integration FPGA Bitstream Zynq Platform Processing System AXI Video DMA AXI Lite Accessible Registers AXI 4 - Stream Video In AXI 4 - Stream Video Out Algorithm from MATLAB / Simulink External Ports Programmable Logic IP Core Xilinx Embedded System Project

19 Integrated HW / SW design flow MATLAB and Simulink Algorithm and System Design HDL IP Core Generation HW SW Embedded System Integration SW Interface Model Generation SW Simulink Interface Model Model Generation FPGA Bitstream Zynq Platform SW Build SW I/O Driver Blocks SW SW Interface Model

20 Integrated HW / SW design flow HDL IP Core Generation Embedded System Integration MATLAB and Simulink Algorithm and System Design SW Interface Model Generation Real-time Parameter Tuning and Verification External Mode Processor-in-the-loop More probe and debug capability in the future FPGA Bitstream SW Build Zynq Platform External Mode PIL

21 A X I 4 - L i t e B u s Embedded System Integration Zynq HW/SW Co-design Workflow Summary HW Design IP Core Generation AXI Lite Accessible Registers Algorithm from MATLAB / Simulink External Ports FPGA IP Core SW Hardware System Project Simulink Model SW I / O Driver Blocks Generate SW Interface Model Processor AXI Lite Accessible Registers Algorithm from MATLAB / Simulink External Ports SW FPGA IP Core SW Interface Model Embedded System Project SW Build FPGA Bitstream

22 Agenda: Sneak-peek into the Demo Zynq design challenges Making Zynq programming easier Model-Based Design Integrated HW / SW design flow Live Demo

23 Live Demo L.E.D Shift

24 Questions? Group: MATLAB & Simulink users in Israel Event announcements Q&A Consulting Job opportunities

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