Practical Embedded Systems Engineering Syllabus for Graduate Students with Multidisciplinary Backgrounds

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1 lctur or tal. Do iz or o not ry gth: l. Do or o not r of d of th: g dr l. Practical Embddd Systms Enginring Syllabus for Graduat Studnts with Multidisciplin ounds Bastian Hatzr Grt Schly Rauf Salimi Khaligh Martin Radtzi Embddd Systms Enginring / CSEE / U Stuttgart logo. Chang whit o gry if ITI log mov!

2 Ovrviw mov! thn 1. Contxt 2. Embddd systms courss 3. Practical (lab) cours 4. Exprincs 5. Conclusion chang s no 2

3 Univrsitat Stuttgart Intrnational Studnts Faculty 5 (CS, EE & IT) Intrnational Study Programs Dgr Non-Dgr Crdit-Transfr (ECTS) (typ. Erasmus) Mastr Doubl / Joint Dgr Programs

4 INFOTECH Mastr Ø INFOTECH is a multidisciplin (EE & CS) intrnational mastr program On top of a qualifying Bachlor dgr Lading to a Mastr of Scinc Dgr (M.Sc.) in Information Tchnology With a rgular study tim of 4 trms (3 taching + 1 Mastr Thsis) Ø Is truly intrnational Ø Is multidisciplin Ø 4 spcializations (majors) can b slctd Communication Enginring and Mdia Tchnology Embddd Systms Micro- and Optolctronics Computr Hardwar/Softwar Enginring

5 History and Facts has bn st up in 1999 (is in its 12 th yar) Attractd som 9500 applications Had applications from graduats of mor than 1000 diffrnt univrsitis From 116 diffrnt countris Admittd som 600 studnts Confrrd 310 Mastr Dgrs Offrs 4 majors Is supportd by som 20 profssors of th faculty (faculty total of 30), 10 profssors from othr facultis and som 5 industry lcturrs Som 55 Lctur Courss Som 10 Lab Courss Som 10 Sminars Currntly admits 80 studnts / yr from > 1200 applicants

6 Admission Slction Ø Svral Comptition Groups (.g. World, Partnr, tc.) Ø Slction mainly on GPA basis Within group / Univrsity/ Country/ World Basd on comprhnsiv xprinc and rfrnc data from prvious applications With wightd GPA (Itc Prformanc Factor) And basd on Raning of applicant And basd on Rputation of Univrsity (Mdia, Own xprinc) Part-viw of Applicants Databas

7 Old Program - OSER Introductory Smstr INFOTECH th intrnational Mastr s program in Information Tchnology Qualifyin g Exams Trm 1 and 2 Intrnship Mastr Thsis Projct Nw Program - NSER - ½ yr Intrnship Trm 1 Trm 2 and 3 Mastr Thsis Projct Tim 0 yr ½ yr 1 yr 1½ yr 2 yr

8 Th Curriculum INFOTECH Mastr 30 Crdit Points 9 Crdit Points 9 Crdit Points 3 Crdit Points 12 Crdit Points Mastr Thsis Projct Intrnship Non-Tchnical Moduls 1 Lab, 1 Sminar Supplmnt Moduls(SM) Group 3 (3 CP) Supplmnt Moduls (SM) 4 th (5 th )Trm (4 th) Trm 2 nd and 3 rd trm 2 (2.5) Yars 30 Crdit Points Cor Moduls (CM) 6 CP ach 27 Crdit Points Basic Moduls (BM) 1 st Trm Total 120 Crdit Points Conditions: Intrnship, Grman Proficincy Crtificat

9 Ø Ø Ø Basic Moduls (1 st Trm) Basic Moduls (BM) Advancd Highr Mathmatics (AHM) Containr Elctronics and Communication (EC) with Communications (Com) Systm and Signal Thory (SST) Radio Frquncy Tchnology (RF) Elctronic Circuits (ElC) Containr Computr Scinc (CS) with Programming Languags (PL) Computr Architctur and Organization (CAO) Data Structurs and Algorithms (DSA) Oprating Systms (OS) Counsling Mtings

10 Embddd Systms Cor Moduls Cor Moduls (CM): 5 out of 12 Ø Advancd Procssor Architctur Ø Communication Ntwors I Ø Communications III Ø Dsign and Tst of Systms-on-a-Chip Ø Distributd Systms Ø Embddd Systms Enginring Ø Industrial Automation Systms Ø Intllignt Snsors and Actors Ø Modlling, Simulation and Spcification Ø Ral-Tim Programming Ø Softwar Enginring for Ral-Tim Systms Ø Statistical and Adaptiv Signal Procssing

11 Syllabus dsign mov! thn s no high-lvl goals (hw/sw codsign tc.) low-lvl goals (hw dsign, crosscompiling) Univrsity Environmnt (studis program,infrastructur, staff, ECTS) Taching Tchniqus xrciss vs. laboratory group wor vs. individual wor big projct vs. small xrciss prdtrmind vs. slf-slctd assignmnt Studnts (multidisciplin bacground, woring styl) ESE Lctur 4.5 CP ESE Exrciss 1.5 CP ES Lab. 6 CP chang 11

12 ES syllabus focus aras mov! Systms-orintd Systm spcification Modlling Simulation Prformanc stimation Platform architctur Lctur with xrciss chang thn s no Hardwar-orintd Systm spcification Modlling Simulation Prformanc stimation Platform architctur Lab Softwar-orintd Ral-tim analysis RT programming, RTOS Cross compilation Rmot dbugging Application-orintd Multimdia Automotiv Robotics 12

13 thn s no ESE lctur with xrciss Thory (xrciss on papr, with ILP): High-lvl synthsis: from algorithm to RTL, Piplind data paths and controllrs, Softwar schduling: priodic and sporadic, Softwar on bar CPU vs. RTOS, schdulability tsts, Systm architctur, storag and communication, HW/SW intgration Practic (xrciss in lab): Tas 1 Tas 2 Tas 3 Sssion 1 Sssion 2 Homwor Procssor-priphral communication with mmory-mappd I/O Implmntation of th intrrupt handlr Dsign of a fram-basd schdulr mov! chang Tas 4 Sssion 3 Sssion 4 Implmntation of a framd-basd schdulr 13

14 Embddd Systms Lab mov! chang thn s no 14

15 Lab dsign trad-offs mov! thn Lab xprimnts Structurd lab assignmnt Larg projct + guidanc (+) motivation + focus Ex Lab + ovrviw no big pictur gtting lost Woring individually Woring in groups Ex Projct tam + grading + larn from ach othr + ral-world + focus Lab on dos all th wor + soft sills + individual advic + highr admission possibl taching costs chang s no Fixd assignmnt Individual assignmnts Slf-assignmnt + costs + adaptation to intrsts (+) motivation + focus both arbitration ncss ris invits plagiarism taching costs taching costs 15

16 Dsign flow mov! Canonical mbddd systms dsign flow spcification partitioning Dsign flow in lab spc. from papr: intrsct. tst algorithm manual partitioning chang thn hardwar dsign intrfac dsign softwar dsign hw impl. (VHDL) coproc unschd. coproc schd. simulation FSL sw impl. (C) 1st itration: algorithm 2nd itration: coproc. drivr s no intgration FPGA platform vrification tst / prf. masur on board 16

17 FPGA platform mov! thn 64 KB On-chip Mmory Instruction Data MicroBlaz Procssor Local Mmory Buss (LMBs) Fast Simplx Lin (FSL) Bus Procssor Local Bus (PLB) Only usd in Embddd Systms Lab cours Coprocssor FSL Intrfac Intrsction Tst (Data Path) Initial try: ARM 7/9 + FPGA Xilinx Univ. Programm boards chang s no UART Worstaion Running a Trminal Program (for dbugging) TIMER Output Scrn (only usd in Embddd Systms Lab cours) VGA Out old: XUPV2P Virtx-II nw: XUPV5 Virtx-5 17

18 Lab assignmnt (old) mov! Part 1 Sssion 1 Sssion 2,3 Introduction to XPS + platform building and basic I/O Softwar Implmntation of algorithm + prformanc masurmnt chang thn s no Part 2 Sssion 4-11 Dataflow graph of algorithm Unschduld implmntation of oprators Schduling of oprators Datapath with schduld oprators FSL-intrfac dsign Intgration of coprocssor into platform Drivr implmntation Prformanc masurmnt Many studnts got lost in part 2 du to - lac of ovrviw, unstructurd woring styl - lac of basic nowldg, in particular in VHDL 18

19 Lab assignmnt (nw) Admission rquirs ntry tst in C and VHDL Part 1 Sssion 1 Sssion 2 Sssion 3 Sssion 4,5 XPS Tutorial (Platform building + basic I/O) Softwar impl. of algorithm + prformanc masurmnt VHDL crash cours (simpl traffic light) Dataflow graph of algorithm, unschduld implmntation + datapath tstbnch mov! chang thn Part 2 Sssion 6 Sssion 7 Schduling of oprators.g. cross product Datapath with schduld oprators, simulation s no Sssion 8,9 Sssion 10 FSL-intrfac dsign (stat machin) + intgration of coprocssor into platform Drivr implmntation + prformanc masurmnt Part 3 Sssion 11 Sssion 12 Systm simulation + softwar nhancmnt (assmblr) Piplining of FSL communication 19

20 Dlivrabls mov! Softwar cod, structurd and with commnts VHDL cod, structurd and with commnts chang Dmo - sals prsntation of th rsults: spdup, FPGA ara - vrbal xamination, qustioning of dsign dcisions thn Writtn documntation (datasht) - data path documntation: IFs, structur, schdul s no - controllr documntation: IFs, FSM diagram - SW intgration documntation: FSL intrfac, rgistr map - masurmnts documntation 20

21 Fraction of points mov! 1 0,9 prvious smstrs wintr trm 2010/11 chang 0,8 0,7 0,6 thn 0,5 0,4 0,3 s no 0,2 0,1 0 Softwar Part Data Path Coprocssor Ray Tracr Adaption Dmo Rport 21

22 Rsarch: mbddd architcturs mov! Hardwar/softwar architctur Many-cor computing systms Systm communication - Bus subsystms chang - Ntwors-on-Chip thn Rconfigurabl architcturs s no Fault-tolrant architcturs Sampl dsign (lft): MPEG-4 H.264 vido codc with ARM9 CPU and Xilinx Virtx5 FPGA to implmnt hardwar acclrators 22

23 Rsarch: dsign mthods mov! Modlling and simulation chang Systm-lvl fault simulation Analysis of proprtis such as thn rliability and robustnss s no 23

24 Conclusion mov! Embddd HW/SW dsign fundamntals, valid for any application chang Htrognity of studnts capabilits and bacgrounds thn Monitoring rsults by qualitativ and quantitativ valuation s no Monitoring th mbddd mart Continuous improvmnt of syllabus, courss 24

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