DG201. CMOS Quad SPST Analog Switch. Features. itle G20. b- t MO uad ST a- Part Number Information. Applications. itch.

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1 OBSOLETEPRODUCT POSSIBLESUBSTITUTEPRODUCT DG44, DG444 Data Sheet May 200 DG20 File Number 35.5 itle G20 b- t MO uad ST a- itch CMOS Quad SPST Analog Switch The DG20 solid state analog switch is designed using an improved, high voltage CMOS monolithic technology. It provides ease-of-use and performance advantages not previously available from solid state switches. Destructive latch-up of solid state analog gates have been eliminated by Intersil s CMOS technology. The DG20 is completely specification and pinout compatible with the industry standard devices. Part Number Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. DG20CJ 0 to 70 6 Ld PDIP E6.3 Features Switches Greater than 28V P-P Signals with ±5V Supplies Break-Before-Make Switching - t OFF...250ns - t ON...700ns TTL, DTL, CMOS, PMOS Compatible Non-Latching with Supply Turn-Off Complete Monolithic Construction Industry Standard (DG20) Applications Data Acquisition utho ) eyrds ter- Functional Diagram IN N P S Sample and Hold Circuits Operational Amplifier Gain Switching Networks Pinout DG20 (PDIP) TOP VIEW rpo- ion, i- n- ctor, itch OS PST, DT, ST, DT, eo, ET, alog itch, anl) rer() OCI DG20 SWITCH CELL TRUTH TABLE DG20 0 ON OFF D IN D S V- GND S 4 D 4 IN IN 2 D 2 S 2 V+(SUBSTRATE) V REF S 3 D 3 IN 3 SWITCHES SHOWN FOR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil and Design is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 200

2 Functional Diagram ( / 4 DG20) V+ V- Q 3 Q 7 Q 5 Q 4 Q 8 Q 5 Q V REF Q 0 V+ Q2 Q 3 Q 2 GATE PROTECTION RESISTOR Q 9 S Q D Q 4 Q 6 V- Pin Descriptions PIN SYMBOL DESCRIPTION IN Logic Control for Switch 2 D Drain (Output) Terminal for Switch 3 S Source (Input) Terminal for Switch 4 V- Negative Power Supply Terminal 5 GND Ground Terminal (Logic Common) 6 S 4 Source (Input) Terminal for Switch 4 7 D 4 Drain (Output) Terminal for Switch 4 8 IN 4 Logic Control for Switch 4 9 IN 3 Logic Control for Switch 3 0 D 3 Drain (Output) Terminal for Switch 3 S 3 Source (Input) Terminal for Switch 3 2 V REF Logic Reference Voltage 3 V+ Positive Power Supply Terminal (Substrate) 4 S 2 Source (Input) Terminal for Switch 2 5 D 2 Drain (Output) Terminal for Switch 2 6 IN 2 Logic Control for Switch 2 2

3 Absolute Maximum Ratings V+toV V V+ to V D... 30V V D tov V V D to V S... 28V V REF tov V V REF to V IN... 30V V REF tognd... 20V V IN tognd... 20V Current(AnyTerminal)...30mA Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIPPackage N/A Maximum Junction Temperature PlasticPackage...50 o C MaximumStorageTemperatureRange o Cto50 o C Maximum Lead Temperature (Soldering 0s) o C Operating Conditions Temperature Range C Suffix...0 o Cto70 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A =25 o C,V+=+5V,V-=-5V C SUFFIX PARAMETER TEST CONDITIONS 0 o C (NOTE 2) 25 o C 70 o C UNITS DYNAMIC CHARACTERISTICS Turn-ON Time (Note 3), t ON R L =kω, V ANALOG = -0V to +0V (Figure ) µs Turn-OFF Time (Note 3), t OFF R L =kω, V ANALOG = -0V to +0V (Figure ) µs Charge Injection, Q Figure 2-20 (Typ) - mv Off Isolation Rejection Ratio, OIRR f = MHz, R L =00Ω, C L 5pF, (Figure 3) - 50 (Typ) - db Crosstalk (Channel-to-Channel), CCRR One Channel Off (Typ) - db DIGITAL CHARACTERISTICS Input Logic Current, I IN(ON) V IN = 0.8V (Note 3) ± ± ±0 µa Input Logic Current, I N(OFF) V IN = 2.4V (Note 3) ± ± ±0 µa ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V ANALOG - ±5 (Typ) - V Drain-Source ON Resistance, r DS(ON) I S =0mA,V ANALOG = ±0V Ω Channel-to-Channel - 30 (Typ) - Ω r DS(ON) Match, r DS(ON) Drain OFF Leakage Current, I D(OFF) V ANALOG = -4V to +4V - ±5 00 na Source OFF Leakage Current, I S(OFF) V ANALOG = -4V to +4V - ±5 00 na Channel ON Leakage V D =V S = -4V to +4V - ±5 200 na Current, I D(ON) +I S(ON) POWER SUPPLY CHARACTERISTICS Supply Current, I+ Positive V IN =0VorV IN = 5V µa Supply Current, I- Negative µa NOTES: 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. All channels are turned off by high logic inputs and all channels are turned on by low 0 inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -20µA. 3

4 Test Circuits 3V ANALOG 0V 3V ANALOG 0V 0V 0pF V OUT kω 0V 0nF V OUT FIGURE. t ON AND t OFF TEST CIRCUIT FIGURE 2. CHARGE INJECTION TEST CIRCUIT 3V ANALOG 2V P-P AT MHz V OUT 00Ω 5Ω FIGURE 3. OFF ISOLATION TEST CIRCUIT Typical Applications V+ Using the V REF Terminal The DG20 has an internal voltage divider setting the TTL threshold on the input control lines for V+ equal to +5V. The schematic shown in Figure 4 with nominal resistor values, gives approximately 2.4V on the V REF pin. As the TTL input signal goes from +0.8V to +2.4V, Q and Q 2 switch states to turn the switch ON and OFF. If the power supply voltage is less than +5V, then a resistor (R EXT ) must be added between V+ and the V REF pin, to restore +2.4V at V REF. The table shows the value of this resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels with a +5V supply are being used, the threshold shifts are less critical, but a separate column of suitable values is given in the table. For logic swings of -5V to + 5V, no resistor is needed. Q 8kΩ 23kΩ V REF GATE PROTECTION RESISTOR FIGURE 4. R EXT Q 2 In general, the low logic level should be <0.8V to prevent Q and Q 2 from both being ON together (this will cause incorrect switch function). TABLE. V+ SUPPLY (V) R EXT FOR TTL LEVELS (kω) R EXT FOR CMOS LEVELS (kω)

5 Typical Performance Curves DRAIN-SOURCE ON RESISTANCE (Ω) o C 25 o C -55 o C V+=+5V V- = -5V DRAIN-SOURCE ON RESISTANCE (Ω) D C B A A: V+=+5V,V-=-5V B: V+=+2V,V-=-2V C: V+=+0V,V-=-0V D: V+=+8V, V-=-8V DRAIN VOLTAGE (V) DRAIN VOLTAGE (V) FIGURE 5. r DS(ON) vs V D AND TEMPERATURE FIGURE 6. r DS(ON) vs V D AND POWER SUPPLY VOLTAGE CHANNEL ON LEAKAGE CURRENT (na) TEMPERATURE ( o C) SOURCE OR DRAIN OFF LEAKAGE CURRENT (na) TEMPERATURE ( o C) FIGURE 7. I D(ON) vs TEMPERATURE FIGURE 8. I S(OFF) OR I D(OFF) vs TEMPERATURE 5

6 Die Characteristics DIE DIMENSIONS: 94 mils x 0 mils x 4 mils METALLIZATION: Type: Al Thickness: 0kÅ PASSIVATION: Type: SiO 2 /Si 3 N 4 SiO 2 Thickness: 7kÅ Si 3 N 4 Thickness: 8kÅ WORST CASE CURRENT DENSITY: x0 5 A/cm 2 Metallization Mask Layout DG20 D (2) IN () IN 2 (6) D 2 (5) S (3) (4) S 2 V- (4) (3) V+ (SUBSTRATE) GND (5) (2) V REF S 4 (6) () S 3 (7) (8) (9) (0) D 4 IN 4 IN 3 D 3 BACKSIDE OF CHIP IS V+ 6

7 Dual-In-Line Plastic Packages (PDIP) INDEX AREA N 2 3 N/2 -B- -A- D E BASE PLANE A2 -C- A SEATING PLANE L C L D A e D A B e e C C B e B 0.00 (0.25) M C A BS NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y4.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions A, A and L are measured with the package seated in JE- DEC seating plane gauge GS D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.25mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/2 and N/2 + ) for E8.3, E6.3, E8.3, E28.3, E42.6 will have a B dimension of inch ( mm). E E6.3 (JEDEC MS-00-BB ISSUE D) 6 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , 0 C D D E E e 0.00 BSC 2.54 BSC - e A BSC 7.62 BSC 6 e B L N Rev. 0 2/93 All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at website Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site Sales Office Headquarters NORTH AMERICA Intersil Corporation 240 Palm Bay Rd. Palm Bay, FL TEL: (32) FAX: (32) EUROPE Intersil SA Mercure Center 00,RuedelaFusee 30 Brussels, Belgium TEL: (32) FAX: (32) ASIA Intersil Ltd. 8F-2, 96, Sec., Chien-kuo North, Taipei, Taiwan 04 Republic of China TEL: FAX: