EECS 141 S02 Lecture 11. Digital Integrated Circuits Combinational Logic. Administrivia. Project Phase 1 launch today

Transcription

1 EECS 141 S02 Lecture 11 Combinational Logic dministrivia Project Phase 1 launch today» due Friday March 15. Labs next week HWs this week:» HW5 due Friday March 1st, 5pm;» HW6 assigned today, due Friday March 7 1

2 PROJECT Design of Clock Driver Network Goal: Design a set of clock buffers for» minimum power dissipation» timing (skew) constraints Clk 1 Clk2 750 C u 1500 C u Clk in C u Clk 4 Clk Cu 500 C u 2

3 Project Goals and Constraints Design to meet goal under following constraints Timing» Skew t skew < 50 ps» Rise and fall times t rise and t fall < 1000 ps Design parameters:» V supply = 2.5 V» f clk = 250 MHz» t rise and t fall of Clk in = 0.5 ns Technology» 0.25 micron CMOS (g25.mod) w/ 4 metal layers Ignore wiring capacitance The Clock Skew Problem Clock Rates as High as 2 GHz in CMOS! φ tφ tφ tφ In CL1 R1 CL2 R2 CL3 R3 t i Out t l,min t l,max t r,min t r,max Clock Edge Timing Depends upon Position 3

4 Delay of Clock Wire R S r c C L r = 0.07 Ω/q, c = 0.04 ff/µm 2 (Tungsten wire) Clock Skew 4

5 Constraints on Skew φ δ φ t φ t φ = t φ + δ t r,min + t l,min + t i R1 data R2 (a) Race between clock and data. φ t φ δ t r,max + t l,max + t i φ φ + T t φ + T = t φ + T + δ R1 R2 data (b) Data should be stable before clock pulse is applied. Clock Constraints in Edge-Triggered Logic T δ t rmin, t rmax, + t i + + t i + t l, min t l, max δ Maximum Clock Skew Determined by Minimum Delay between Latches Minimum Clock Period Determined by Maximum Delay between Latches 5

6 Clock Distribution CLOCK H-Tree Network Observe: Only Relative Skew is Important Clock Network with Distributed uffering Local rea Module Module secondary clock drivers Module Module Module Module main clock driver CLOCK Reduces absolute delay, and makes Power-Down easier Sensitive to variations in uffer Delay 6

7 Clock Skew in lpha Processor The importance of the project report Limit of 4 pages to convince us that your project should get a Nobel prize (or at least a major award) e concise and to the point Demonstrate clearly that your claims are true Express your motivations and your reasoning. Make sure to make it quantitative e honest we will check your spice files and run them! 7

8 Other recommendations Do not start with optimization by simulation. Think through the problem first and build a first-order analytical model to start» provide quantitative estimates of performance. Comment on approach and important design decisions. Include sized transistor schematics. Explain why simulated results may differ from estimates. Recommended Reading Chapter 5 (new version) Chapter 9 (old version)» study the relevant sections 8

9 Grading Results: 30% Correctness: 30% pproach and Report: 40% COMINTIONL LOGIC 9

10 Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic Circuit Out In Logic Circuit Out State (a) Combinational (b) Sequential Output = f(in) Output = f(in, Previous In) 10

11 Static CMOS Circuit t every point in time (except during the switching transients) each gate output is connected to either or V ss via a low-resistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static Complementary CMOS In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks 11

12 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high Y Y = if and Y Y = if OR NMOS Transistors pass a strong 0 but a weak 1 PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low Y Y = if ND = + Y Y = if OR = PMOS Transistors pass a strong 1 but a weak 0 12

13 Threshold Drops PUN S D D 0 V GS S 0 - V Tn C L C L PDN D C L 0 V GS S C L V Tp S D Complementary CMOS Logic Style Construction 13

14 Example Gate: NND Example Gate: NOR 14

15 Complex CMOS Gate C D D C OUT = (D + ( + C)) 4-input NND Gate Vdd In 1 In 2 In 3 In 4 In 1 Out In 2 Out In 3 In 4 GND In1 In2 In3 In4 15

16 Example j C Logic Graph C PUN =!(C ( + )) i C i j C GND PDN Consistent Euler Path C i j GND C 16

17 Two Versions of!(c ( + )) C C GND GND 17