Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. TingTing Hwang Tsing Hua University, Hsin-Chu

Size: px
Start display at page:

Download "Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. TingTing Hwang Tsing Hua University, Hsin-Chu"

Transcription

1 Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization TingTing Hwang Tsing Hua University, Hsin-Chu 1

2 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions 2

3 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions 3

4 Engineering Change Order (ECO) Incremental change of a design To fix bugs To meet timing constraint To meet small change of functionality Small modification instead of redesign a circuit To save the reiteration of design flow To reduce the cost of mask-making 5

5 Spare Cells in ECO Spare cells (NOT, NOR, NAND) are placed evenly in layout at physical design Spare cells are then used for modification in ECO flow 6

6 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions 7

7 Voltage Drop Power source fluctuations become serious High performance Lower supply voltage VDD/GND variations Chip speed Noise margin Adding decoupling capacitance (decap) is an effective way to reduce power noise [Sachin, TCAD 2003] 8

8 New ECO Design Flow A new reconfigurable (RECON) cell structure Served as spare cell and decoupling capacitor Leakage reduction Free selecting of function type Demonstration of RECON cell by an ECO algorithm for timing closure and IR drop minimization 11

9 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions 12

10 RECON Base Cell Two PMOS transistor with same transistor width Two NMOS transistor with same transistor width Eight CONTACTs VDD and GND implemented by layer of metal-1 13

11 DECAP Cell VDD VDD GND GND Schematic of cell Configured from RECON base cell Use Metal-1 connection 15

12 Functional Cell (a) Inverter (b) 2-Input NAND (c) 2-Input NOR Configured from RECON base cell 16

13 Comparisons Between RECON Cells and Standard Cells Setup of experiment Cell layouts created with TSMC 0.13um process SPICE net-lists extracted by RCextractor Delay, leakage, internal power and input pin capacitance by SPICE simulation 17

14 As Decoupling Cells Less flexibility of layout 16%-39% capacitance 9%-34% leakage 18

15 As Functional Cells Area Delay Leakage w/o tie-cell w/i tie-cell Recon w/o tie-cell w/i tie-cell Recon Power Pin cap INVX INVX INVX INVX INVX ND2X ND2X NR2X NR2X BUFX BUFX BUFX BUFX Average

16 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions 21

17 Model of Power Supply Analysis Cycle-based time frame 22

18 Model of Power Supply Analysis (cont.) Metal layer of VDD and GND modeled as a power-grid resistance Standard cells modeled as time-varying current source RECON DECAP cells modeled as capacitors connected between VDD and GND 23

19 Model of Power Supply Analysis (cont.) Supply voltage variation can be derived as following Clock cycle is divided into many time slots Switching gate are derived from static timing analysis Maximum current consumption are calculated in each time slot. 24

20 IR Drop Analysis of Whole Chip 26

21 Leakage Analysis of Whole Chip 27

22 Outline Introduction Engineering Change Order (ECO) Voltage Drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental result Conclusion 28

23 Differences Between RECON and Traditional ECO Flows RECON DECAP instead of spare cells are pre-placed RECON DECAP cells are reconfigured to RECON functional cells when RECON ECO flow is performed Unselected RECON DECAP cells are kept as decoupling capacitors 29

24 Problem Formulation An ECO path is a path that violates the timing constraint Given a set of placed gate level net-list, ECO paths and timing constraint, perform gate sizing or buffer insertion on ECO paths Timing constraint is met IR drop is minimized 30

25 RECON ECO Algorithm Input: a set of ECO paths to be optimized For each ECO path Find the critical gates in ECO paths and put in ECO_gate_list While (timing is not satisfy) Choose the gate from ECO_gate_list with most output loading Perform gate sizing or buffer insertion List_A = search_region(gate_sizing) List_B = search_region(buffer_insertion) For all configurable cell Rg in List_A or List_B If IRdrop(Rg) > threshold Remove Rg in List_A or List_B Candidate_list = List_A + List_B Compute path delay gain for all Rg in Candidate_list Select the best Rg corresponding to the best delay gain Update the ECO path delay End while 32

26 Search Region for Gate Sizing D1 D2 G5 G1 G3 G4 G7 G2 D4 D3 D5 G6 D6 Search_region(G4) = Bounding_Box(G3 U G4 U G5 U G6) 33

27 Search Region for Buffer Insertion D1 D2 G5 G1 G3 D3 G4 D5 G7 G2 D4 G6 D6 Search_region(G4) = Bounding_Box(G4 U G5 U G6) 34

28 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions 35

29 Experimental Setup ITC99 benchmarks Benchmarks synthesized to gate-level net-list using TSMC 0.13um process Standard cells and RECON DECAP cells placed by SOCEncounter 20% area used to place RECON DECAP cells 36

30 Experimental Flow 37

31 Statistics of Benchmarking Circuits Timing constraint is set to 90% of critical path delay in the original circuit 38

32 Leakage (na) Leakage Comparisons Before ECO Leakage comparison with traditional spare cells with RECON DECAP cells 0 b14 b15 b20 b21 b22 benchmark set 39

33 Performance Comparisons Before ECO Trad: traditional spare cells RECON: RECON decap cells 40

34 Performance Comparisons After ECO Trad: traditional spare cells RECON: RECON decap cells 41

35 Number of Unsolved Paths After ECO Trad: traditional spare cells RECON: RECON decap cell 42

36 Conclusions A new cell structure Decoupling capacitor cell ECO spare cell A reconfigurable ECO flow 20% IR drop reduction 44% leakage reduction 43

37 44

Power Distribution and Decap Design. Overview

Power Distribution and Decap Design. Overview Lecture 4 Power Distribution and Decap Design Xiongfei Meng Dept. of ECE University of British Columbia xmeng@ece.ubc.ca 1 Overview Reading HJS - Chapter 11 Power Grid and Clock Design Introduction Power

More information

Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects Junxia Ma, Member, IEEE, and Mohammad Tehranipoor, Senior Member, IEEE

Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects Junxia Ma, Member, IEEE, and Mohammad Tehranipoor, Senior Member, IEEE IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 12, DECEMBER 2011 1923 Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects Junxia

More information

CADENCE LAYOUT TUTORIAL

CADENCE LAYOUT TUTORIAL CADENCE LAYOUT TUTORIAL Creating Layout of an inverter from a Schematic: Open the existing Schematic Page 1 From the schematic editor window Tools >Design Synthesis >Layout XL A window for startup Options

More information

Standard cell libraries are required by almost all CAD tools for chip design

Standard cell libraries are required by almost all CAD tools for chip design Standard Cell Libraries Standard cell libraries are required by almost all CAD tools for chip design Standard cell libraries contain primitive cells required for digital design However, more complex cells

More information

Spezielle Anwendungen des VLSI Entwurfs Applied VLSI design (IEF170)

Spezielle Anwendungen des VLSI Entwurfs Applied VLSI design (IEF170) Spezielle Anwendungen des VLSI Entwurfs Applied VLSI design (IEF170) Course and contest Intermediate meeting 3 Prof. Dirk Timmermann, Claas Cornelius, Hagen Sämrow, Andreas Tockhorn, Philipp Gorski, Martin

More information

Lab 5: Design Layout With Cadence Virtuoso 9/28/99 to 10/4/99

Lab 5: Design Layout With Cadence Virtuoso 9/28/99 to 10/4/99 18-322 Lab 5: Design Layout With Cadence Virtuoso 9/28/99 to 10/4/99 I. Objective To use Cadence Virtuoso to create a CMOS layout, and use the Cadence tools to verify this layout. Specifically, in this

More information

Jos Sulistyo VTVT Group Virginia Information Systems Center

Jos Sulistyo VTVT Group Virginia Information Systems Center Development of CMOS Standard Cell Library Jos Sulistyo VTVT Group Virginia Information Systems Center 1 Why Create Cell Library? Complexity of design continue to increase Full-custom design is no longer

More information

ECE 3060 VLSI and Advanced Digital Design

ECE 3060 VLSI and Advanced Digital Design ECE 3060 VLSI and Advanced Digital Design Lecture 1 Introduction You will need: Text: Modern VLSI Design Wolf Text: Logical Effort Sutherland et. al. Reference: Your previous digital design text Colored

More information

Slides adapted from: N. Weste, D. Harris, CMOS VLSI Design, Addison-Wesley, 3/e, 2004

Slides adapted from: N. Weste, D. Harris, CMOS VLSI Design, Addison-Wesley, 3/e, 2004 The CMOS Inverter Slides adapted from: N. Weste, D. Harris, CMOS VLSI Design, Addison-Wesley, 3/e, 2004 1 Outline Robustness of CMOS Inverter The Static Behavior Switching threshold Noise Margins Performance

More information

Synchronous 16x8 SRAM Design

Synchronous 16x8 SRAM Design Synchronous 16x8 SRAM Design Bhavya Daya, Shu Jiang, Piotr Nowak, Jaffer Sharief Electrical Engineering Department, University of Florida Abstract Memory arrays are an essential building block in any digital

More information

Digital System Need Timing Conventions

Digital System Need Timing Conventions Physical Design 2: and Power R P R W C d C W /2 C W /2 C g Arvind Computer Science & Artificial Intelligence Lab Massachusetts Institute of Technology March 17, 2008 http://csg.csail.mit.edu/6.375/ L16-1

More information

8 Bit Digital-to-Analog Converter

8 Bit Digital-to-Analog Converter 8 Bit Digital-to-Analog Converter Tim Adams ttexastim@hotmail.com Richard Wingfield wingfiel@cs.utah.edu 8 Bit DAC Project Description: For this project, an 8 bit digital-to-analog converter was designed.

More information

University of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design

University of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design University of Texas at Dallas Department of Electrical Engineering EEDG 6306 - Application Specific Integrated Circuit Design Synopsys Tools Tutorial By Zhaori Bi Minghua Li Fall 2014 Table of Contents

More information

Alpha CPU and Clock Design Evolution

Alpha CPU and Clock Design Evolution Alpha CPU and Clock Design Evolution This lecture uses two papers that discuss the evolution of the Alpha CPU and clocking strategy over three CPU generations Gronowski, Paul E., et.al., High Performance

More information

MOS LOGIC FAMILIES. Simple and cheap to fabricate Consume very little power More circuit elements are possible.

MOS LOGIC FAMILIES. Simple and cheap to fabricate Consume very little power More circuit elements are possible. MOS LOGIC FAMILIES In our last lecture, we were introduced to digital logic. We saw that the building blocks of digital circuitry are logic gates. We now take on the task of investigating how MOSFETs are

More information

CS/ECE 5710/6710 Digital VLSI Design CAD Assignment #3 Due Monday September 29 th, 5:00pm

CS/ECE 5710/6710 Digital VLSI Design CAD Assignment #3 Due Monday September 29 th, 5:00pm Overview CS/ECE 5710/6710 Digital VLSI Design CAD Assignment #3 Due Monday September 29 th, 5:00pm In this assignment you will design a register cell. This cell should be a single-bit edgetriggered D-type

More information

International Journal of Electronics and Computer Science Engineering 1482

International Journal of Electronics and Computer Science Engineering 1482 International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant

More information

Expanding the Synopsys PrimeTime Solution with Power Analysis

Expanding the Synopsys PrimeTime Solution with Power Analysis Expanding the Synopsys PrimeTime Solution with Analysis Gordon Yip, Product Marketing Manager, Synopsys, Inc. June 2006 Introduction Design closure in today s advanced designs requires a delicate balance

More information

Semiconductor Memories

Semiconductor Memories Chapter 8 Semiconductor Memories (based on Kang, Leblebici. CMOS Digital Integrated Circuits 8.1 General concepts Data storage capacity available on a single integrated circuit grows exponentially being

More information

ALBERT-LUDWIGS-UNIVERSITÄT FREIBURG. FÜR INFORMATIK Lehrstuhl für Rechnerarchitektur Prof. Dr. Bernd Becker

ALBERT-LUDWIGS-UNIVERSITÄT FREIBURG. FÜR INFORMATIK Lehrstuhl für Rechnerarchitektur Prof. Dr. Bernd Becker ALBERT-LUDWIGS-UNIVERSITÄT FREIBURG INSTITUT FÜR INFORMATIK Lehrstuhl für Rechnerarchitektur Prof. Dr. Bernd Becker STUDIENARBEIT Automatic Test Pattern Generation for Power Droop Testing Alejandro Czutro

More information

Accurate Thermal Analysis of Chip/Package Systems

Accurate Thermal Analysis of Chip/Package Systems Accurate Thermal Analysis of Chip/Package Systems Ting-Yuan Wang and Margaret Schmitt, Apache Design Solutions - March 15, 2007 Introduction With the increasing complexity and power dissipation of modern

More information

Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No #15 Synthesis: Part I So from this class we would

More information

Document Contents Introduction Layout Extraction with Parasitic Capacitances Timing Analysis DC Analysis

Document Contents Introduction Layout Extraction with Parasitic Capacitances Timing Analysis DC Analysis Cadence Tutorial C: Simulating DC and Timing Characteristics Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group rev S06 (convert to spectre simulator) Document Contents Introduction

More information

Noise Margin and Gate Delay. Debdeep Mukhpadhyay IIT Madras

Noise Margin and Gate Delay. Debdeep Mukhpadhyay IIT Madras Noise Margin and Gate Delay Debdeep Mukhpadhyay IIT Madras Logic levels Solid logic 0/1 defined by V SS /V DD. Inner bounds of logic values V L /V H are not directly determined by circuit properties, as

More information

Parasitic Back Annotation for Post Layout Simulation

Parasitic Back Annotation for Post Layout Simulation Application Note Parasitic Back Annotation for Post Layout Simulation Introduction: Layout designers have different layout approaches to try to minimize the parasitic effects created by the physical layout.

More information

TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN

TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN USING DIFFERENT FOUNDRIES Priyanka Sharma 1 and Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department

More information

Guide to Power Measurement A Cadence EDA Tools Help Document

Guide to Power Measurement A Cadence EDA Tools Help Document Document Contents Introduction General Steps Static Power Dynamic and Average Power Peak Power Energy Measuring Power using Voltage and Current Guide to Power Measurement A Cadence EDA Tools Help Document

More information

Document Contents Introduction Layout Extraction with Parasitic Capacitances Timing Analysis DC Analysis

Document Contents Introduction Layout Extraction with Parasitic Capacitances Timing Analysis DC Analysis Cadence Tutorial C: Simulating DC and Timing Characteristics Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group Last updated by Waqar A Qureshi FS08 (convert to spectre simulator)

More information

32-bit Adder for Low Voltage Operation with Level Converters

32-bit Adder for Low Voltage Operation with Level Converters 32-bit Adder for Low Voltage Operation with Level Converters Bhargav Yelamanchili Abstract The purpose of this project is to lower the power consumption by reducing the operating voltage of a 32-bit adder,

More information

Power Delivery Network (PDN) Analysis

Power Delivery Network (PDN) Analysis Power Delivery Network (PDN) Analysis Edoardo Genovese Importance of PDN Design Ensure clean power Power Deliver Network (PDN) Signal Integrity EMC Limit Power Delivery Network (PDN) VRM Bulk caps MB caps

More information

An Advanced Behavioral Buffer Model With Over-Clocking Solution. Yingxin Sun, Joy Li, Joshua Luo IBIS Summit Santa Clara, CA Jan.

An Advanced Behavioral Buffer Model With Over-Clocking Solution. Yingxin Sun, Joy Li, Joshua Luo IBIS Summit Santa Clara, CA Jan. An Advanced Behavioral Buffer Model With Over-Clocking Solution Yingxin Sun, Joy Li, Joshua Luo IBIS Summit Santa Clara, CA Jan. 31, 2014 Agenda 1. SPICE Model and Behavioral Buffer Model 2. Over-Clocking

More information

Pass-Transistor Logic. Topics. NMOS-Only Logic. Pass-Transistor Logic. Resistance of Transmission Gate. Pass-Transistor Logic.

Pass-Transistor Logic. Topics. NMOS-Only Logic. Pass-Transistor Logic. Resistance of Transmission Gate. Pass-Transistor Logic. Topics Transmission Gate Pass-transistor Logic 3 March 2009 1 3 March 2009 2 NMOS-Only Logic Example: AND Gate 3 March 2009 3 3 March 2009 4 Resistance of Transmission Gate XOR 3 March 2009 5 3 March 2009

More information

Digital Phase Locked Loop Design and Layout

Digital Phase Locked Loop Design and Layout Digital Phase Locked Loop Design and Layout Dali Wang Fan Yang 12/21/2001 Contents 1. Intoduction 1 1.1 Project Overview 1 1.2 Objective Of The Project 2 1.3 Table Listing Of Specifications 2 1.3.1 The

More information

LSI Noise Model for Power Integrity Analysis and Its Application

LSI Noise Model for Power Integrity Analysis and Its Application LSI Noise Model for Power Integrity Analysis and Its Application V Tomio Sato V Tetsutaro Hashimoto V Ryuhei Sasagawa (Manuscript received October 5, 2005) Semiconductor scaling is making power integrity

More information

Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group.

Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Document Contents Introduction Create Layout Cellview Design Rule Checking

More information

Hands-on Homework 3: Reflections on Finite Length Lines

Hands-on Homework 3: Reflections on Finite Length Lines Hands-on Homework 3: Reflections on Finite Length Lines Introduction Reflections that occur on transmission lines can be used to help create proper signaling conditions at a receiver or can disrupt the

More information

IL2225 Physical Design

IL2225 Physical Design IL2225 Physical Design Nasim Farahini farahini@kth.se Outline Physical Implementation Styles ASIC physical design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification

More information

System on Chip Design. Michael Nydegger

System on Chip Design. Michael Nydegger Short Questions, 26. February 2015 What is meant by the term n-well process? What does this mean for the n-type MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What

More information

THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design

THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design CHAPTER 5 THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Exercises and Design Problems 5.2 The Static CMOS Inverter

More information

1. Design of a Programmable Functional Unit Background

1. Design of a Programmable Functional Unit Background UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on October 22, 2009. Elad Alon FALL 2009 TERM PROJECT PHASE I EECS 141 1. Design

More information

TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING

TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation

More information

Class 11: Transmission Gates, Latches

Class 11: Transmission Gates, Latches Topics: 1. Intro 2. Transmission Gate Logic Design 3. X-Gate 2-to-1 MUX 4. X-Gate XOR 5. X-Gate 8-to-1 MUX 6. X-Gate Logic Latch 7. Voltage Drop of n-ch X-Gates 8. n-ch Pass Transistors vs. CMOS X-Gates

More information

RING Designer. VLSI Power Distribution Ring Design Tool. OEA International, Inc. 155 East Main Ave, Suite 110 Morgan Hill, CA

RING Designer. VLSI Power Distribution Ring Design Tool. OEA International, Inc. 155 East Main Ave, Suite 110 Morgan Hill, CA RING Designer VLSI Power Distribution Ring Design Tool OEA International, Inc. 155 East Main Ave, Suite 110 Morgan Hill, CA 95037 www.oea.com Solves the problem of generating accurate Spice decks to analyze

More information

Note that none of the above MAY be a VALID ANSWER.

Note that none of the above MAY be a VALID ANSWER. ECE 270 Learning Outcome 1-1 - Practice Exam / Solution LEARNING OUTCOME #1: an ability to analyze and design CMOS logic gates. Multiple Choice select the single most appropriate response for each question.

More information

1. Design of a 32x64-bit SRAM Background

1. Design of a 32x64-bit SRAM Background UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on October 27, 2008. Elad Alon FALL 2008 TERM PROJECT PHASE I EECS 141 1. Design

More information

Cadence Tips (not complete)

Cadence Tips (not complete) How to run Layout XL Cadence Tips (not complete) In the schematic view go to: Tools Design Synthesis Layout XL (click ok on the two pop-up windows) Now you should have the Virtuoso layout window popping

More information

An On-chip, 100-GHz Sampling Rate, 8-channel Sampling Oscilloscope Macro with Embedded Sampling Clock Generator

An On-chip, 100-GHz Sampling Rate, 8-channel Sampling Oscilloscope Macro with Embedded Sampling Clock Generator An On-chip, 100-GHz Sampling Rate, 8-channel Sampling Oscilloscope Macro with Embedded Sampling Clock Generator M. Takamiya, M. Mizuno, and K. Nakamura NEC Outline Background Sampling Oscilloscope Macro

More information

EE 434 Lecture 5. Improved Device Model Stick Diagrams Technology Files

EE 434 Lecture 5. Improved Device Model Stick Diagrams Technology Files EE 434 Lecture 5 Improved Device Model Stick Diagrams Technology Files Quiz 3 How many transistors are required to realize the function F = A B + A C in a basic CMOS process if static NAND and NOR gates

More information

Simulation with Cadence Analog Design Environment

Simulation with Cadence Analog Design Environment Simulation with Cadence Analog Design Environment Analog Design Environment (ADE) is integrated on Cadence Custom IC Design software. You can simulate your design (schematic, extracted layout, vhdl, etc.)

More information

The Ohio State University EE Senior Design (II)

The Ohio State University EE Senior Design (II) VLSI Scarlet Letters Final Design Report Report Due Date: Monday June 5 th 2006 The Ohio State University EE 683 - Senior Design (II) VLSI Scarlet Letters Team Members: -David W. Adams II -Steve Jocke

More information

Datasheet Mixed-Signal Gate Array

Datasheet Mixed-Signal Gate Array Mixed-Signal Gate Array Institut für Mikroelektronik Stuttgart Allmandring 30 a 70569 Stuttgart This document describes the internal structure of the IMS CHIPS 0.5 µm Mixed Signal Gate Array Family. It

More information

Lab 4: Timing Analysis of Logic Gates Due: Friday February 26th, 2009

Lab 4: Timing Analysis of Logic Gates Due: Friday February 26th, 2009 Lab 4: Timing Analysis of Logic Gates Due: Friday February 26th, 2009 Summary: Lab 4 introduces post-layout simulation using extracted parameters from the cell layout and allows students to observe the

More information

Thermometer to Binary MUX

Thermometer to Binary MUX UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on October 21, 2010. Elad Alon FALL 2010 TERM PROJECT PHASE I EECS 141 1. Design

More information

Lecture 2: Logical Effort & Sizing

Lecture 2: Logical Effort & Sizing High Speed CMOS VLSI Design Lecture : Logical Effort & Sizing (c) 1997 David Harris 1.0 P/N Ratios Static CMOS gates are a ratioless circuit family, meaning that the gates will work correctly for any ratio

More information

Digital Integrated Circuits

Digital Integrated Circuits Chapter 6 The CMOS Inverter 1 Contents Introduction MOST simulation models The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter : The dynamic

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 13: Designing for Low Power

CMPEN 411 VLSI Digital Circuits Spring Lecture 13: Designing for Low Power CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 13: Designing for Low Power [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN

More information

EE 584: Introduction to VLSI. Project Report. ET Ring Oscillator NAND

EE 584: Introduction to VLSI. Project Report. ET Ring Oscillator NAND EE 584: Introduction to VLSI Project Report ET Ring Oscillator NAND Group Members: Abhishika Fatehpuria Venkata Satyapriya Gunupudi Neelima Mandava Gayatri Sagi EE 584 VLSI Project Report 1 Table of Contents

More information

This use case demonstrates the process of mode #1, in which user adds AND2 gate, and the tool maps it to one inverter and one NAND gate.

This use case demonstrates the process of mode #1, in which user adds AND2 gate, and the tool maps it to one inverter and one NAND gate. GUI Mode Metal ECO Random type gates mapping to spare type gates Introduction Start up Gates On the Fly Generate spare list file and load spare list file Locate and setup ECO Do ECO on partial schematic

More information

Chapter 6 PROBLEMS. 1 Chapter 6 Problem Set

Chapter 6 PROBLEMS. 1 Chapter 6 Problem Set 1 hapter 6 Problem Set hapter 6 PROLEMS 1. [E, None,.2] Implement the equation X = (( + ) ( + D + E) + ) G using complementary MOS. Size the devices so that the output resistance is the same as that of

More information

4-Bit Counter. Shanthan Mudhasani, ECE 533, University of Tennessee, Knoxville

4-Bit Counter. Shanthan Mudhasani, ECE 533, University of Tennessee, Knoxville 4-Bit Counter Shanthan Mudhasani, ECE 533, University of Tennessee, Knoxville Abstract This paper presents a report on the design of a 4-bit Up Counter using J-K flipflop that has a clocked input with

More information

Status of the design of the TDC for the GTK TDCpix ASIC

Status of the design of the TDC for the GTK TDCpix ASIC Status of the design of the TDC for the GTK TDCpix ASIC Gianluca Aglieri Rinella, Lukas Perktold DLL design review meeting, 16 03 2011 Outline Introduction Purpose and objectives Reminder Challenges of

More information

Circuit and System Representation. IC Designers must juggle several different problems

Circuit and System Representation. IC Designers must juggle several different problems Circuit and System Representation IC Designers must juggle several different problems Multiple levels of abstraction IC designs requires refining an idea through many levels of detail, specification ->

More information

A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation David Bull 1, Shidhartha Das 1, Karthik Shivashankar 1,

More information

Generalized ASIC Design Flow

Generalized ASIC Design Flow Generalized ASIC Design Flow High Level Design Specification Capture Design Capture in C, C++, SystemC or SystemVerilog HW/SW partitioning and IP selection RTL Design Verilog/VHDL System, Timing and Logic

More information

FPGAs 1. CMPE691/491: Advanced FPGA Design

FPGAs 1. CMPE691/491: Advanced FPGA Design FPGAs 1 CMPE691/491: Advanced FPGA Design FPGAs Large array of configurable logic blocks (CLB) connected via programmable interconnects Features and Specifications of FPGAs Basic Programmable Devices Features

More information

EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell

EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell Mat Binggeli October 24 th, 2014 Overview Binggeli Page 2 The objective of this report is to describe the design and implementation of a 6-transistor

More information

1. Designing a 32-bit atithmetic-logic unit Background

1. Designing a 32-bit atithmetic-logic unit Background UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on October 16, 2001. Borivoje Nikolić FALL 2001 TERM PROJECT PHASE I EECS 141 Phase

More information

Lecture 3-1. Inverters and Combinational Logic

Lecture 3-1. Inverters and Combinational Logic Lecture 3 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@imperial.ac.uk Lecture 3-1 Based on slides/material

More information

CPE/EE 427, CPE 527, VLSI Design I: Power Analysis Using Cadence Encounter

CPE/EE 427, CPE 527, VLSI Design I: Power Analysis Using Cadence Encounter CPE/EE 427, CPE 527, VLSI Design I: Power Analysis Using Cadence Encounter Ashkan Ashrafi, Joel Wilder and Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville 1. INTRODUCTION In this

More information

Royal Military College of Canada

Royal Military College of Canada Microelectronics Lab Cadence Tutorials Layout Design and Simulation (Using Virtuoso / Diva / Analog Artist) Department of Electrical & Computer Engineering Royal Military College of Canada Cadence University

More information

Index i xi xv xxvi. Abstract List of Tables List of Figures Glossary. Page.No CHAPTER 1 INTRODUCTION

Index i xi xv xxvi. Abstract List of Tables List of Figures Glossary. Page.No CHAPTER 1 INTRODUCTION iv Abstract List of Tables List of Figures Glossary Index i xi xv xxvi CHAPTER 1 INTRODUCTION 1.1 Introduction 1.2 Formulation of the problem 1.3 Objectives 1.4 Methodology 1.5 Contribution of the Thesis

More information

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1 ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

More information

Low Power Design. in CMOS. Digital Integrated Circuits Low Power Design

Low Power Design. in CMOS. Digital Integrated Circuits Low Power Design Low Power Design in CMOS Why worry about power? -- Heat Dissipation source : arpa-esto microprocessor power dissipation DEC 21164 Evolution in Power Dissipation Why worry about power Portability BATTERY

More information

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Sheng Li, Junh Ho Ahn, Richard Strong, Jay B. Brockman, Dean M Tullsen, Norman Jouppi MICRO 2009

More information

EECS 141 S02 Lecture 11. Digital Integrated Circuits Combinational Logic. Administrivia. Project Phase 1 launch today

EECS 141 S02 Lecture 11. Digital Integrated Circuits Combinational Logic. Administrivia. Project Phase 1 launch today EECS 141 S02 Lecture 11 Combinational Logic dministrivia Project Phase 1 launch today» due Friday March 15. Labs next week HWs this week:» HW5 due Friday March 1st, 5pm;» HW6 assigned today, due Friday

More information

CHAPTER 3 METHODOLOGY

CHAPTER 3 METHODOLOGY CHAPTER 3 METHODOLOGY The methodology is undertaken of this project are divided into two main parts. The first part is designing the switching pulse using VHDL programming and the second part is developing

More information

Characterization of Flip-Flop Designs at Subthreshold Voltages

Characterization of Flip-Flop Designs at Subthreshold Voltages Characterization of Flip-Flop Designs at Subthreshold Voltages Jeff Butera, Matthew Guthaus Department of Computer Engineering University of California Santa Cruz Santa Cruz, CA 95064 {jbutera, mrg}@soe.ucsc.edu

More information

Three-Phase Dual-Rail Pre-Charge Logic

Three-Phase Dual-Rail Pre-Charge Logic Infineon Page 1 CHES 2006 - Yokohama Three-Phase Dual-Rail Pre-Charge Logic L. Giancane, R. Luzzi, A. Trifiletti {marco.bucci, raimondo.luzzi}@infineon.com {giancane, trifiletti}@die.mail.uniroma1.it Summary

More information

COMBINATIONAL LOGIC Digital Integrated Circuits Combinational Logic Prentice Hall 1995

COMBINATIONAL LOGIC Digital Integrated Circuits Combinational Logic Prentice Hall 1995 COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

More information

Application Note. Maximizing DAC Performance for Every Budget

Application Note. Maximizing DAC Performance for Every Budget Application Note Maximizing DAC Performance for Every Budget Abstract This application note discusses several factors that affect the audio performance of the Sabre digital audio converters. This article

More information

Lab 1: Schematic Capture Using Virtuoso Schematic Editor (VSE)

Lab 1: Schematic Capture Using Virtuoso Schematic Editor (VSE) Lab 1: Schematic Capture Using Virtuoso Schematic Editor (VSE) This Lab will go over: 1. Logging in 2. Setting up your account 3. Design Entry through schematic capture 4. Compiling a new project directory

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey Homework #1: Circuit Simulation EECS 141 Due Friday, January 30, 5pm, box in 240

More information

The CB-55L a Low Power Consumption 55nm Cell-Based IC Product

The CB-55L a Low Power Consumption 55nm Cell-Based IC Product The CB-55L a Low Power Consumption 55nm Cell-Based IC Product NAKAYASU Tetsumasa Abstract The CB-55L is a cell-based IC product based on a 55nm process that adopts various techniques for reducing the lead

More information

Introduction to Digital VLSI Design מבוא לתכנון VLSIספרתי

Introduction to Digital VLSI Design מבוא לתכנון VLSIספרתי Introduction to Digital VLSI Design מבוא לתכנון VLSIספרתי Routing Lecturer: Gil Rahav Semester B, EE Dept. BGU. Freescale Semiconductors Israel Routing :- Making real Point to Point connections. Metal

More information

Cadence Virtuoso Tutorial

Cadence Virtuoso Tutorial Cadence Virtuoso Tutorial version 6.1 University of Southern California Last Update: Oct, 2015 EE209 Fall 2015 Table of Contents System Setup... 3 1. Basic setup... 3 2. Cadence setup... 3 Basic Design

More information

NAME AND SURNAME. TIME: 1 hour 30 minutes 1/6

NAME AND SURNAME. TIME: 1 hour 30 minutes 1/6 E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 2005-2006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June

More information

Lecture 12: MOS Decoders, Gate Sizing

Lecture 12: MOS Decoders, Gate Sizing Lecture 12: MOS Decoders, Gate Sizing MAH, AEN EE271 Lecture 12 1 Memory Reading W&E 8.3.1-8.3.2 - Memory Design Introduction Memories are one of the most useful VLSI building blocks. One reason for their

More information

DESIGN AND TUNING OF A TREE-MESH CLOCK DISTRIBUTION

DESIGN AND TUNING OF A TREE-MESH CLOCK DISTRIBUTION DESIGN AND TUNING OF A TREE-MESH CLOCK DISTRIBUTION Nikhil Jayakumar, Dave Murata, Valery Kugel { nikhilj, dmurata, valery } @juniper.net Juniper Networks OVERVIEW Comparison of Clock trees vs Clock Grids/Mesh

More information

CMOS Power Consumption

CMOS Power Consumption CMOS Power Consumption Lecture 13 18-322 Fall 2003 Textbook: [Sections 5.5 5.6 6.2 (p. 257-263) 11.7.1 ] Overview Low-power design Motivation Sources of power dissipation in CMOS Power modeling Optimization

More information

DESIGN OF FLIPFLOP FOR POWER REDUCTION USING CLOCK PAIRING TECHNIQUE

DESIGN OF FLIPFLOP FOR POWER REDUCTION USING CLOCK PAIRING TECHNIQUE INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 DESIGN OF FLIPFLOP FOR POWER REDUCTION USING CLOCK PAIRING TECHNIQUE R.Balakumaresan Assistant Professor Department

More information

Basic Concepts in VLSI Physical Design Automation

Basic Concepts in VLSI Physical Design Automation VLSI Design Styles Basic Concepts in VLSI Physical Design Automation VLSI Design Cycle Large number of devices Optimization requirements for high performance Time-to-market competition Cost Manual System

More information

Introduction to CMOS Design. CMOS Transistors

Introduction to CMOS Design. CMOS Transistors Introduction to CMOS Design Dr. Paul D. Franzon Outline 1. CMOS Transistors 2. CMOS cell design 3. Transistor Sizing 4. Low Power Design References l Smith and Franzon, Chapter 11 l Weste and Eshraghian,

More information

Design Verification with LasiCkt

Design Verification with LasiCkt Chapter 8 Design Verification with LasiCkt An important step in the design process is verifying that the layout of an integrated circuit matches the schematics of the integrated circuit. From either the

More information

Low Power AMD Athlon 64 and AMD Opteron Processors

Low Power AMD Athlon 64 and AMD Opteron Processors Low Power AMD Athlon 64 and AMD Opteron Processors Hot Chips 2004 Presenter: Marius Evers Block Diagram of AMD Athlon 64 and AMD Opteron Based on AMD s 8 th generation architecture AMD Athlon 64 and AMD

More information

EECS 141: SPRING 10 MIDTERM 1

EECS 141: SPRING 10 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences J. Rabaey WeFr 2-3:30pm Fr, February 19, 6:30-8:00pm EECS 141: SPRING 10 MIDTERM 1 NAME Last First

More information

CMOS, the Ideal Logic Family

CMOS, the Ideal Logic Family CMOS, the Ideal Logic Family INTRODUCTION Let s talk about the characteristics of an ideal logic family. It should dissipate no power, have zero propagation delay, controlled rise and fall times, and have

More information

Power Integrity and Ground Bounce Simulation of High Speed PCBs. Presentation #11

Power Integrity and Ground Bounce Simulation of High Speed PCBs. Presentation #11 1 Power Integrity and Ground Bounce Simulation of High Speed PCBs Presentation #11 Agenda 2 Power Integrity (PI) Design Flow xdsm Board for Fiber Optic/Broadband Wireless Network - Resonances on Power/Ground

More information

Computer Systems Lab 1. Basic Logic Gates

Computer Systems Lab 1. Basic Logic Gates Computer Systems Lab Basic Logic Gates Object To investigate the properties of the various types of logic gates, and construct some useful combinations of these gates. Parts () 700 Quad -input NAND gate

More information

IBIS for SSO Analysis

IBIS for SSO Analysis IBIS for SSO Analysis Asian IBIS Summit, November 15, 2010 (Presented previously at Asian IBIS Summits, Nov. 9 & 12, 2010) Haisan Wang Joshua Luo Jack Lin Zhangmin Zhong Contents Traditional I/O SSO Analysis

More information

Advanced VLSI Design CMOS Inverter

Advanced VLSI Design CMOS Inverter Propagation Delay Several observations can be made from the analysis: PMOS was widened to match resistance of NMOS by 3-3.5. This was done to provide symmetrical H-to-L and L-to-H propagation delays. This

More information