HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

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1 DESCRIPTION The, /6 single-channel and /6 dual-channel optocouplers consist of a 5 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -4 C to +5 C. A maximum input signal of 5 ma will provide a minimum output sink current of ma (fan out of ). An internal noise shield provides superior common mode rejection of typically kv/µs. The HCPL- 6 and HCPL- 6 has a minimum CMR of 5 kv/µs. The has a minimum CMR of kv/µs. FEATURES Very high speed- MBit/s Superior CMR- kv/µs Double working voltage-4v Fan-out of over -4 C to +5 C Logic gate output Strobable output Wired OR-open collector U.L. recognized (File # E97) N/C + V F _ V CC 7 V E 6 V O + V F V CC 7 V 6 V V F APPLICATIONS Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Switching power supplies Pulse transformer replacement Computer-peripheral interface TRUTH TABLE (Positive Logic) N/C 4 5 GND GND Input Enable H H L L H H H L H L L H H NC L L NC H A. µf bypass capacitor must be connected between pins and 5. (See note ) Fairchild Semiconductor Corporation DS 7/9/ OF

2 ABSOLUTE MAXIMUM RATINGS (No derating required up to 5 C) Parameter Symbol Value Units Storage Temperature T STG -55 to +5 C Operating Temperature T OPR -4 to +5 C Lead Solder Temperature T SOL 6 for sec C EMITTER 5 DC/Average Forward Single channel I F ma Input Current Dual channel (Each channel) Enable Input Voltage Single channel V E 5.5 V Not to exceed V CC by more than 5 mv Reverse Input Voltage Each channel V R 5. V Power Dissipation DETECTOR Supply Voltage Current RECOMMENDED OPERATING CONDITIONS Single channel P Dual channel (Each channel) I 45 Parameter Symbol Min Max Units Input Current, Low Level I FL 5 µa Input Current, High Level I FH *6. 5 ma Supply Voltage, V CC V Enable Voltage, Low Level V EL. V Enable Voltage, High Level V EH. V CC V Low Level Supply Current T A C Fan Out (TTL load) N mw V CC 7. V ( minute max) Single channel 5 I Dual channel (Each channel) O 5 Voltage Each channel V O 7. V Collector Single channel 5 P Power Dissipation Dual channel (Each channel) O 6 * 6. ma is a guard banded value which allows for at least % CTR degradation. Initial input current threshold value is 5. ma or less ma mw OF 7/9/ DS

3 ELECTRICAL CHARACTERISTICS (T A = -4 C to +5 C Unless otherwise specified.) INDIVIDUAL COMPONENT CHARACTERISTICS Parameter Test Conditions Symbol Min Typ** Max Unit EMITTER (I F = ma). Input Forward Voltage T V F A =5 C.4.75 V Input Reverse Breakdown Voltage (I R = µa) B VR 5. V Input Capacitance (V F =, f = MHz) C IN 6 pf Input Diode Temperature Coefficient (I F = ma) V F / T A -.4 mv/ C DETECTOR High Level Supply Current Single Channel (V 7 CC = 5.5 V, I F = ma) I CCH ma Dual Channel (V E =.5 V) 5 Low Level Supply Current Single Channel (V CC = 5.5 V, I F = ma) 9 Dual Channel (V I CCL E =.5 V) 4 ma Low Level Enable Current (V CC = 5.5 V, V E =.5 V) I EL ma High Level Enable Current (V CC = 5.5 V, V E =. V) I EH ma High Level Enable Voltage (V CC = 5.5 V, I F = ma) V EH. V Low Level Enable Voltage (V CC = 5.5 V, I F = ma) (Note ) V EL. V SWITCHING CHARACTERISTICS (T A = -4 C to +5 C, V CC = 5 V, I F = 7.5 ma Unless otherwise specified.) AC Characteristics Test Conditions Symbol Min Typ** Max Unit Propagation Delay Time (Note 4) (T A =5 C) to High Level (R T PLH L = 5, C L = 5 pf) (Fig. ) ns Propagation Delay Time (Note 5) (T A =5 C) to Low Level (R T PHL L = 5, C L = 5 pf) (Fig. ) ns Pulse Width Distortion (R L = 5, C L = 5 pf) (Fig. ) T PHL -T PLH 5 ns Rise Time (-9%) (R L = 5, C L = 5 pf) (Note 6) (Fig. ) t r 5 ns Fall Time (9-%) (R L = 5, C L = 5 pf) (Note 7) (Fig. ) t f ns Enable Propagation Delay Time (I F = 7.5 ma, V EH =.5 V) to High Level (R L = 5, C L = 5 pf) (Note ) (Fig. ) t ELH ns Enable Propagation Delay Time (I F = 7.5 ma, V EH =.5 V) to Low Level (R L = 5, C L = 5 pf) (Note 9) (Fig. ) t EHL ns Common Mode Transient Immunity (T A =5 C) V CM = 5 V, (Peak) (at High Level) (I F = ma, V OH (Min.) =. V), (R CM H L = 5 ) (Note ), V/µs, (Fig. 4) 5, V CM = 4 V, 5, (R L = 5 ) (I F = 7.5 ma, V OL (Max.) =. V) Common Mode, V, CM = 5 V (Peak) CM Transient Immunity, (T L A =5 C) (at Low Level) (Note ) (Fig. 4) 5, V/µs (T A =5 C) V CM = 4 V, 5, DS 7/9/ OF

4 TRANSFER CHARACTERISTICS (T A = -4 C to +5 C Unless otherwise specified.) DC Characteristics Test Conditions Symbol Min Typ** Max Unit High Level Current (V CC = 5.5 V, V O = 5.5 V) I OH µa (I F = 5 µa, V E =. V) (Note ) Low Level Current Input Threshold Current ISOLATION CHARACTERISTICS (T A = -4 C to +5 C Unless otherwise specified.) Characteristics Test Conditions Symbol Min Typ** Max Unit Input- (Relative humidity = 45%) Insulation Leakage Current (T A = 5 C, t = 5 s) Withstand Insulation Test Voltage (V I-O = VDC) (Note ) (RH < 5%, T A = 5 C) (Note ) ( t = min.) I I-O.* µa V ISO 5 V RMS Resistance (Input to ) (V I-O = 5 V) (Note ) R I-O Capacitance (Input to ) (f = MHz) (Note ) C I-O.6 pf ** All typical values are at V CC = 5 V, T A = 5 C NOTES (V CC = 5.5 V, I F = 5 ma) (V E =. V, I CL = ma) (Note ) (V CC = 5.5 V, V O =.6 V, V E =. V, I OL = ma) V OL.5.6 V I FT 5 ma. The V CC supply to each optoisolator must be bypassed by a.µf capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V CC and GND pins of each device.. Each channel.. Enable Input - No pull up resistor required as the device has an internal pull up resistor. 4. t PLH - Propagation delay is measured from the.75 ma level on the HIGH to LOW transition of the input current pulse to the.5 V level on the LOW to HIGH transition of the output voltage pulse. 5. t PHL - Propagation delay is measured from the.75 ma level on the LOW to HIGH transition of the input current pulse to the.5 V level on the HIGH to LOW transition of the output voltage pulse. 6. t r - Rise time is measured from the 9% to the % levels on the LOW to HIGH transition of the output pulse. 7. t f - Fall time is measured from the % to the 9% levels on the HIGH to LOW transition of the output pulse.. t ELH - Enable input propagation delay is measured from the.5 V level on the HIGH to LOW transition of the input voltage pulse to the.5 V level on the LOW to HIGH transition of the output voltage pulse. 9. t EHL - Enable input propagation delay is measured from the.5 V level on the LOW to HIGH transition of the input voltage pulse to the.5 V level on the HIGH to LOW transition of the output voltage pulse.. CM H - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., V OUT >. V). Measured in volts per microsecond (V/µs).. CM L - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e., V OUT <. V). Measured in volts per microsecond (V/µs).. Device considered a two-terminal device: Pins,, and 4 shorted together, and Pins 5,6,7 and shorted together. 4 OF 7/9/ DS

5 VOL-Low Level Voltage (V) HIGH SPEED- MBit/s TYPICAL PERFORMANCE CURVES Fig. Low Level Voltage vs. Ambient Temperature I F = 5 ma V E = V V CC = 5.5V I OL =. ma I OL = 6.4 ma I OL = 6 ma I OL = 9.6 ma T A - Ambient Temperature ( C) IF = Forward Current (ma) 6... Fig. Input Diode Forward Voltage vs. Forward Current V F - Forward Voltage (V) TP - Propagation Delay (ns) 6 4 V CC = 5 V Fig. Switching Time vs. Forward Current R L = 4 k (T PLH ) R L = k R L = k (T PLH ) R L = 4 k (T PHL ) R L = 5 (T PLH ) R L = 5 k I F - Forward Current (ma) IOL - Low Level Current (ma) Fig. 4 Low Level Current vs. Ambient Temperature I F = 5 ma I F = ma I F = 5 ma T A - Ambient Temperature ( C) V CC = 5 V V E = V V OL =.6 V 4 Fig. 5 Input Threshold Current vs. Ambient Temperature 6 Fig. 6 Voltage vs. Input Forward Current IFT - Input Threshold Current (ma) V CC = 5. V V O =.6 V R L = 5 R L = k R L = 4k VO - Voltage (V) 5 R L = 5 4 R L =4k R L = k T A - Ambient Temperature ( C) I F - Forward Current (ma) DS 7/9/ 5 OF

6 IOH-High Level Current (µa) TE-Enable Propagation Delay (ns) TP-Propagation Delay (ns) PWD - Pulse Width Distortion (ns) Tr/Tf - Rise and Fall Time (ns) HIGH SPEED- MBit/s Fig. 7 Pulse Width Distortion vs. Temperature Fig. Rise and Fall Time vs. Temperature I F = 7.5 ma VCC = 5 V RL = 4 k RL = k RL = IF = 7.5 ma VCC = 5 V RL = k (tr) R L = 4 k (tr) RL = 5 (tr) T A - Temperature ( C) RL = k RL = 4 k (tf) RL = T A - Temperature ( C) ] Fig. 9 Enable Propagation Delay vs. Temperature Fig. Switching Time vs. Temperature RL = 4 k (TELH) 6 4 RL = k (TELH) RL = 5 (TELH) 6 RL = k TPLH RL = 4 k TPLH RL = 5 TPLH RL = 5 RL = k RL = 4 k ] (TEHL) TA-Temperature ( C) 4 RL = k RL = 4 k TPHL RL = TA-Temperature ( C) ] Fig. High Level Current vs. Temperature 5 VCC = 5.5 V VO = 5.5 V VE =. V IF = 5 µa T A-Temperature ( C) 6 OF 7/9/ DS

7 Pulse Generator tr = 5ns Z O = 5 +5V I F = 7.5 ma V CC Input (I ) F I =.75 ma F t PHL t PLH Input Monitor (I F) GND 5. f bypass R L C L (V ) O (V O) (V ) O tf 9% % tr.5 V Fig. Test Circuit and Waveforms for t PLH, t PHL, t r and t f. Pulse Generator Input tr = 5ns Monitor Z O = 5 (V E) +5V V CC Input (V ) E. V.5 V 7.5 ma 7 6. f bypass R L (V O) tehl (V O) t ELH.5 V C L 4 GND 5 Fig. Test Circuit t EHL and t ELH. DS 7/9/ 7 OF

8 V CC +5V V FF B A I F 7 6. f bypass 5 (V O) 4 GND 5 V CM Pulse Gen Peak VCM V 5V VO Switching Pos. (A), I = F V O (Min) CM H V O (Max) VO.5 V Switching Pos. (B), I = 7.5 ma F CM L Fig. 4 Test Circuit Common Mode Transient Immunity OF 7/9/ DS

9 Package Dimensions (Through Hole) Package Dimensions (Surface Mount).9 (9.9).7 (9.4) PIN ID. 4 PIN ID. 4.7 (6.6).5 (6.5).7 (6.6).5 (6.5) SEATING PLANE. (5.).4 (.55).9 (9.9).7 (9.4).7 (.7).45 (.4). (.5) MIN (.7).45 (.4). (.5) MIN. (7.6) TYP.6 (.4). (.). (.56).6 (.4).54 (.9 ). (.5).6 (.4). (.). (.54) TYP 5 MAX. (7.6) TYP. (.54) TYP. (.56).6 (.4).45 [.4].5 (.) MIN.45 (.) MIN Lead Coplanarity :.4 (.) MAX Package Dimensions (.4 Lead Spacing) 4 PIN ID..7 (6.6).5 (6.5) (9.9).7 (9.4) SEATING PLANE. (5.).4 (.55).7 (.7).45 (.4).4 (.) MIN.54 (.9). (.5) NOTE All dimensions are in inches (millimeters). (.56).6 (.4).6 (.4). (.). (.54) TYP.4 (.6) TYP to5 DS 7/9/ 9 OF

10 ORDERING INFORMATION Order Entry Option Identifier Description S.S Surface Mount Lead Bend SD.SD Surface Mount; Tape and reel W.W.4 Lead Spacing QT Carrier Tape Specifications ( D Taping Orientation) 4.9 ±.. ±.5 4. ±.. ±. 4. ±. Ø.55 ±.5.75 ±.. ±. 7.5 ±. 6. ±.. ±.. MAX. ±. Ø.6 ±. User Direction of Feed OF 7/9/ DS

11 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HERE- IN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in labeling, can be reasonably expected to result in a significant injury of the user.. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. DS 7/9/ OF

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