Pass Transistor Logic
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1 COMP 13 Lecture 7 Pass Transistor Logic [ll lecture notes are adapted from Mary Jane Irwin, Penn tate, which were adapted from Rabaey s Digital Integrated Circuits, 22, J. Rabaey et al.] Comp13-L7.1 Review: tatic Complementary CMO High noise margins In1 In2 InN In1 In2 InN Comp13-L7.2 V DD PUN PDN PUN and PDN are dual logic networks V OH and V OL are at V DD and GND, respectively Low output impedance, high input impedance No static power consumption (In1,In2, InN) Never a direct path between V DD and GND in steady state Delay a function of load capacitance and transistor on resistance Comparable rise and fall times (under the appropriate relative transistor sizing conditions)
2 NMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals NMO switch closes when the gate input is high X Y X = Y if and X Y X = Y if or Remember - NMO transistors pass a strong but a weak 1 Comp13-L7.3 PMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals PMO switch closes when the gate input is low X Y X = Y if and = + X Y X = Y if or = Remember - PMO transistors pass a strong 1 but a weak Comp13-L7.4
3 Pass Transistor (PT) Logic = Gate is static a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless idirectional (versus undirectional) Comp13-L7.5 VTC of PT ND Gate 1.5/ /.25.5/.25.5/.25 = V out, V 1 =V DD, = V DD =V DD, = V DD == V DD 1 2 V in, V Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMO inverter insertion) Comp13-L7.6
4 Differential PT Logic (CPL) PT Network Inverse PT Network = =+ = ND/NND = OR/NOR =+ XOR/XNOR = Comp13-L7.7 CPL Properties Differential so complementary data inputs and outputs are always available (so don t need extra inverters) till static, since the output defining nodes are always tied to V DD or GND through a low resistance path Design is modular; all gates use the same topology, only the inputs are permuted. imple XOR makes it attractive for structures like adders ast (assuming number of transistors in series is small) dditional routing overhead for complementary signals till have static power dissipation problems Comp13-L7.8
5 CPL ull dder!um um!c out C out Comp13-L7.9 NMO Only PT Driving an Inverter In = V DD V x = V G = V V DD DD -V Tn D M 2 M 1 V x does not pull up to V DD, but V DD V Tn Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from V DD to GND) Notice V Tn increases of pass transistor due to body effect (V ) Comp13-L7.1
6 Voltage wing of PT Driving an Inverter V DD In = V DD D.5/.25 x 1.5/.25.5/.25 Out Voltage, V ody effect large V at x - when pulling high ( is tied to GND and charged up close to V DD ) o the voltage drop is even worse V x = V DD -(V Tn + γ( ( 2φ f + V x ) - 2φ f )) Out In x = 1.8V Time, ns Comp13-L7.11 Cascaded NMO Only PTs = V DD = V DD G M 1 C = V DD x = V DD -V Tn1 G y M 2 = V DD Out = V DD C = V DD M 1 x M 2 y Out wing on y = V DD -V Tn1 -V Tn2 wing on y = V DD -V Tn1 Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins Comp13-L7.12
7 olution 1: Level Restorer Level Restorer on =1 M 2 Out= = M n M r off x= 1 M 1 Out =1 ull swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high or correct operation M r must be sized correctly (ratioed) Comp13-L7.13 Transient Level Restorer Circuit Response 3 W/L 2 =1.5/.25 W/L n =.5/.25 W/L 1 =.5/.25 Voltage, V 2 1 W/L r =1.75/.25 W/L r =1.5/.25 node x never goes below V M of inverter so output never switches Comp13-L7.14 W/L r =1./.25 W/L r =1.25/ Time, ps Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f )
8 olution 2: Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMO PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD ) low V T transistors In 2 = V = 2.5V on Out In 1 = 2.5V off but leaking = V sneak path Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V G is below V T ) Comp13-L7.15 olution 3: Transmission Gates (TGs) Most widely used C solution C C C C = GND C = GND = V DD = GND C = V DD C = V DD ull swing bidirectional switch controlled by the gate signal C, = if C = 1 Comp13-L7.16
9 Resistance of TG 3 25 R n W/L p =.5/.25 V R p 2 2.5V V out Resistance, kω R p R n 2.5V R eq W/L n =.5/ V out, V Comp13-L7.17 TG Multiplexer V DD In 2 In 1 =!(In 1 + In 2 ) GND In 1 In 2 Comp13-L7.18
10 Transmission Gate XOR Comp13-L7.19 TG ull dder um C out Comp13-L7.2
11 Differential TG Logic (DPL) GND = = GND V DD = = V DD ND/NND XOR/XNOR Comp13-L7.21
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