Digital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5

Transcription

1 igital Integrated Circuit (IC) Layout and esign - Week 3, Lecture 5! EE134 1 Reading and Prelab " Week 1 - Read Chapter 1 of text. " Week - Read Chapter of text. " Week 3 - Read Chapter 3 of text. " Prelab - Lab 1.! Read insert A of text, pp ! The lab will make more sense if you read this before lab.! There is nothing to turn in. EE134 1

2 Agenda " Last Lecture! esign rules! Layout and esign! Ties to V and GN! Padframes! Pin Packages " Today s Lecture! Contacts! Basic MO transistor operation! Large-signal MO model for manual analysis! The CMO inverter EE134 3 Course Emphasis / esign tyles " Physical design of CMO digital ICs " Application pecific IC (AIC)! Full Custom (What we are doing) Most flexible approach Higher speed maller designs Expensive Requires device-level (i.e. transistor level) knowledge Push limits of a technology - must understand parasitics: stray C, L, pn jns., BJTs, breakdown, stored charge, latch-up, etc. Used for high-volume chips - µ processors & memory EE134 4

3 esign tyles (cont.) " AIC (cont.)! tandard Cell Logic gate level Low volume Quick turnaround Lower density! Gate Array (FPGA) Lowest density - speed - cost. EE134 5 efine circuit specs Circuit chematic Flowchart Circuit imulation Meet pecs? No Layout Parasitic Extraction (R,C) Re-simulate with Parasitics No Meet pecs? No Prototype Fabrication Test and Evaluate Meet pecs? Production EE134 6 Yes 3

4 Tie n-well n to V and ubstrate to Ground GN In V A A Out (a) Layout V V A A n p-substrate Field n + p + n Oxide p+ n + + EE134 7 Reason for GN and V Ties Parasitic iodes V out V p + p-substrate n + n + n p + n + p-substrate EE

5 Contacts to ilicon " Ohmic Contacts! Metal on highly doped n + or p + i.! What you want to pin the substrate to ground or the n-well to V. " chottky Contacts (we won t use these)! Metal on lightly doped n or p i.! Creates a chottky diode which has an I-V curve similar to a p-n junction diode. EE134 9 Ohmic contact " Metal on n + or p + i. " imple picture: " Need heavy doping to get the ultra short screening length needed for an OHMIC contact. EE

6 chottky Contact " Metal on n or p i. " imple picture: " Light n or p doping gives long screening length giving chottky Barrier. EE Ohmic Contacts for Voltage Pinning " Ohmic contact to the n-well " You need the! Active and elect to define the n+ region.! Contact to put hole in thick passivation ide / nitride so that the metal contacts the i. EE

7 Ohmic Contacts for Voltage Pinning " Ohmic contact to the p-substrate " You need the! Active and elect to define the p+ region.! Contact to put hole in thick passivation ide / nitride so that the metal contacts the i. EE Pin n-well n to V and p-substrate p to GN n+ p+ V M1 Power Bus PMO p+ n-well NMO n+ n+ p+ M1 GN Ground Bus EE

8 The Active Layer " Cut in the Field Oxide (FOX) to get down to the i. EE Active and elect Layers EE

9 Active and elect Layers (cont) EE Concepts to Remember: " Need to put down an n+ region on the n-well to make an ohmic contact to the n-well. " Need to put down a p+ region on the p- substrate to make an ohmic contact to the p-substrate. " These are your active / select layers. " Finally, you need a contact layer to drill through the thick ide / nitride passivation. EE

10 BA MO Layout " O NOT O THI!!!!!!! poly-gate active - hole cut in FOX n+ select elf-aligned process The Poly gate serves as an implant mask during the n+ implant. There is no gap between the source/gate and drain/gate. EE Outline Ch. 3 " MO Transistor! Basic Operation! Modes of Operation! eep sub-micron MO " CMO Inverter EE

11 What is a Transistor? An MO Transistor A witch! V G G V G V T Ron EE134 1 witch Model of CMO Transistor V G G V G < V T R on V G > V T EE134 11

12 Transistor Circuit ymbols " NMO rain We always want Gate Body (p-i substrate) G B ource G B = # G Body tied to ource EE134 3 NMO Body Terminal (B) A transistor is a 4 terminal device. n+ V p+ M1 Circuit chematic Layout PMO NMO p+ n+ n-well G B = = GN n+ M1 B p+ GN EE

13 Transistor Circuit ymbols " PMO ource We always want V Gate Body (n-well) G B rain G G B = # Body tied to ource EE134 5 PMO Body Terminal (B) = V n+ V M1 G B = = V p+ Layout PMO p+ n-well NMO n+ B n+ p+ M1 GN EE

14 NMO and PMO " PMO is complementary to NMO " Turn it upside down and switch all signs of voltages, V # V, V G # V G. NMO PMO + V G > 0 + G - G V G > 0 - EE134 7 Outline Ch. 3 " MO Transistor! Basic Operation! Modes of Operation! eep sub-micron MO " CMO Inverter EE

15 Threshold Voltage: Concept EE134 9 The Threshold Voltage Fermi Potential φ φ F T N = -φt ln n k B T = q A i φ F -0.6V for p-type substrates γ is the body factor V T0 = 0.76 V (NMO) 0.95 V (PMO) AMI C5 process EE

16 The Body Effect V T (V) reverse body bias V TO V B EE The rain Current " Charge in the channel is controlled by the gate voltage: i [ V V ( x V ] Q ( x) = C ) G " rain current is proportional to charge x velocity: I v n = v n dv ( x) = µ n ξ ( x) = µ n dx T ( x) Q ( x) W i C ε = t v n = velocity; W = channel width; ξ = electric field; µ n = mobility EE

17 The rain Current " Combining velocity and charge: I dx = µ C W ( V V V ) dv n " Integrating along the length of the channel from source to drain: L G V 0 I k n dx = I = µ C n = µ C n µ n 0 C W L µ n ε = t W G ( V V V ) G EE T T dv V ( VG VT ) V n + V G V(x) G + L V x n + I Outline Ch. 3 " MO Transistor! Basic Operation! Modes of Operation! eep sub-micron MO " CMO Inverter EE

18 Transistor in Linear Mode V G > V + V T evice turned on (V G > V T ) V < V G -V T V G G V I n + V(x) + n + L x I = µ C n W L p-substrate B V ( VG VT ) V EE Transistor in aturation V T < V G < V + V T V > V G -V T V G G V > V G - V T n+ - V G - V T + n+ I = µ C I n n C = µ W L W L V ( VG VT ) V ( V V ) G T Pinch-off EE

19 aturation " For V > V G -V T, the drain current 6 saturates: x I n C = µ W L ( V V ) G T I (A) V (V) " Including channel-length modulation: I µ n C W = G T 1 L ( V V ) ( + λv ) slope = λ V = V /V A V A = 1/λ = Early voltage EE Modes of Operation " Cutoff: V G < V T I = 0 " Resistive or Linear: V < V G -V T & V G > V T " aturation I = µ C n W L V ( VG VT ) V V > V G -V T C = µ W L n V G > V I ( VG VT ) T EE

20 Current-Voltage Relations A good ol Transistor -4 x 10 6 VG=.5 V I (A) Resistive aturation VG=.0 V V = V G -V T VG= 1.5 V Quadratic Relationship 1 VG= 1.0 V V (V) EE A model for manual analysis EE

21 Outline Ch. 3 " MO Transistor! Basic Operation! Modes of Operation! eep sub-micron MO " CMO Inverter EE Current-Voltage Relations The eep-ubmicron Era -4.5 x 10 Early aturation VG=.5 V I (A) VG=.0 V VG= 1.5 V Linear Relationship 0.5 VG= 1.0 V V (V) EE

22 Velocity aturation υ n (m/s) υ sat = 10 5 Constant velocity Constant mobility (slope = µ) ξ c = 1.5 ξ (V/µm) EE Velocity aturation I Long-channel device V G = V hort-channel device aturates sooner V AT V G -V T V EE134 44

23 I versus V G EE I versus V EE

24 Including Velocity aturation µ n chosen empirically so that µ n ξc = v sat # µ n depends on the PICE model. EE imple Cheesy erivation for Velocity aturation and Linear ependence on V G dv I = W µ C ( V V V ( x) ) I n velocity = W v ρ By definition, I I G TH dx ρ v µ ξ n = vsat dv = W C dv dx dx = W v C (charge density) v dv dx ( V V V ) G TH,sat ( V V ) sat G TH V,sat EE

25 I versus V EE Regions of Operation EE

26 A Unified Model for Manual Analysis EE imple Model versus PICE -4 x 10.5 V =V AT I (A) Linear Velocity aturated 0.5 V AT =V GT V =V GT aturated V (V) EE

27 A PMO Transistor 0 x 10-4 VG = -1.0V -0. VG = -1.5V -0.4 I (A) -0.6 VG = -.0V Assume all variables negative! -0.8 VG = -.5V V (V) EE ub-threshold Conduction (Cut-off) I (A) V = V Linear Quadratic I The lope Factor I ~ 0 e qvg nkt C n = 1 + C is V G for I /I 1 =10, Exponential V T V G (V) Typical values for : mv/decade = inverse subtheshold slope EE

28 ubthreshold " Inverse sub-threshold slope ()! Ideal T=300K, n=1, kbt = ln = 60 q ( 10)! For each 60 mv of V G, the current drops by a factor of 10. This is the best that you can do.! For V = 0.4V, the maximum on-off current ratio that you can have at T=300K is! At 373K, the ratio is mv decade = =.3 10 EE ubthreshold " Current in subthreshold I = I e VG nk T / q B e 1 V k T / q B ( 1+ λv ) " Inverse subthreshold slope definition ( I ) d log 10 dvg nkbt = ln 10 q 1 1 = ln 10 1 I di dv G 1 EE

29 ubthreshold Concepts " FETs turn off exponentially. " Inverse subthreshold slope, (mv/dec), is the figure of merit that tells how well they = ( ) = { o shut off. nkbt 60 7 C ln 10 q o n= C n 1 and typically 1.5 " The maximum possible on-off current ratio is Ion V I off = 10 max " 018 ITR node has V = 0.4V - hence the static power problem. Know this if you are in an interview with a semiconductor co. EE Transistor Model for Manual Analysis EE