1 ISL89E, ISL9E ata Sheet pril 8, 6 FN67. ±kv ES Protected, /8 Unit Load, V, Low Power, High Speed and Slew ate Limited, Full uplex, S-8/S- Transceivers The ISL89E, ISL9E are ES protected, fractional unit load, icmos, V powered, single transceivers that meet both the S-8 and S- standards for balanced communication. Each driver output and receiver input is protected against ±kv ES strikes, without latch-up. Unlike competitive versions, these Intersil devices are specified for % tolerance supplies (.V to.v). x inputs and Tx outputs present a /8 unit load to the S-8 bus, which allows a total of 6 transmitters and receivers on the network for large node count systems. These devices are configured for full duplex (separate x input and Tx output pins) applications, so they are ideal for S- networks requiring high ES tolerance on the bus pins. The ISL89E utilizes a slew rate limited driver which reduces EMI, and minimizes reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. ata rates up to Mbps are achievable by using the ISL9E, which features higher slew rates. eceiver (x) inputs feature a fail-safe if open design, which ensures a logic high x output if x inputs are floating. river (Tx) outputs are short circuit protected, even for voltages exceeding the power supply voltage. dditionally, on-chip thermal shutdown circuitry disables the Tx outputs to prevent damage if power dissipation becomes excessive. Features Pb-free vailable as an Option (ohs Compliant) (See Ordering Info) S-8 I/O Pin ES Protection ±kv HM - Class ES Level on all Other Pins >7kV HM /8 Unit Load llows up to 6 evices on the us High ata ates (ISL9E) up to Mbps Slew ate Limited Version for Error Free ata Transmission (ISL89E) Very Low Quiescent Current: - μ (ISL89E) - 7μ (ISL9E) -7V to +V Common Mode Input Voltage ange Three-State x and Tx Outputs Full uplex Pinout Operates from a Single +V Supply (% Tolerance) Current Limiting and Thermal Shutdown for driver Overload Protection pplications Factory utomation Security Networks uilding Environmental Control Systems Industrial/Process Control Networks Level Translators (e.g., S- to S-) S- Extension Cords TLE. SUMM OF FETUS PT NUME HLF/FULL UPLEX HIGH ES? NO. OF VICES LLOWE ON US T TE (Mbps) SLEW-TE LIMITE? CEIVE/ IVE ENLE? QUIESCENT I CC (μ) PIN COUNT ISL89E Full es 6. es es ISL9E Full es 6 No es 7 CUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTESIL or -7-7 Intersil (and design) is a registered trademark of Intersil mericas Inc. Copyright Intersil mericas Inc., 6. ll ights eserved. ll other trademarks mentioned are the property of their respective owners.
2 Ordering Information Pinout PT NUME PT MKING TEMP. NGE ( C) PCKGE PKG. WG. # ISL89E, ISL9E (SOIC) TOP VIEW ISL89EI ISL89EI - to 8 Ld SOIC M. ISL89EI (Note) 89EI - to 8 Ld SOIC (Pb-free) M. ISL9EI ISL9EI - to 8 Ld SOIC M. NC NC ISL9EI (Note) 9EI - to 8 Ld SOIC (Pb-free) M. dd -T suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are ohs compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEC J ST NC Truth Tables TNSMITTING CEIVING INPUTS OUTPUTS INPUTS OUTPUT X X X X High- High- - X +.V X -.V X Inputs Open X X High- Pin escriptions PIN NC FUNCTION eceiver output: If > by at least.v, is high; If < by.v or more, is low; = High if and are unconnected (floating). eceiver output enable. is enabled when is low; is high impedance when is high. river output enable. The driver outputs, and, are enabled by bringing high. They are high impedance when is low. river input. low on forces output low and output high. Similarly, a high on forces output high and output low. Ground connection. ±kv HM ES Protected, Noninverting receiver input. ±kv HM ES Protected, Inverting receiver input. ±kv HM ES Protected, Noninverting driver output. ±kv HM ES Protected, Inverting driver output. System power supply input (.V to.v). No Connection. FN67.
3 Typical Operating Circuit +V ISL89E, ISL9E +V +.µf.µf + T 9 9 T 6, 7 6, 7 FN67.
4 bsolute Maximum atings to Ground V Input Voltages,, V to ( +.V) Input/Output Voltages,,, V to +.V V to ( +.V) Short Circuit uration, Continuous ES ating See Specification Table Thermal Information Thermal esistance (Typical, Note ) θ J ( C/W) Ld SOIC Package Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature ange C to C Maximum Lead Temperature (Soldering s) C (Lead Tips Only) Operating Conditions Temperature ange C to 8 C CUTION: Stresses above those listed in bsolute Maximum atings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ J is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech rief T79 for details. Electrical Specifications Test Conditions: =.V to.v; Unless Otherwise Specified. Typicals are at = V, T = C, Note PMETE SMOL TEST CONTIONS TEMP ( C) MIN TP MX UNITS C CHCTEISTICS river ifferential V OUT (no load) V O Full - - V river ifferential V OUT (with load) V O = Ω (S-) (Figure ) Full - V = 7Ω (S-8) (Figure ) Full.. V Change in Magnitude of river ifferential V OUT for Complementary Output States ΔV O = 7Ω or Ω (Figure ) Full -.. V river Common-Mode V OUT V OC = 7Ω or Ω (Figure ) Full - - V Change in Magnitude of river Common-Mode V OUT for Complementary Output States ΔV OC = 7Ω or Ω (Figure ) Full -.. V Logic Input High Voltage V IH,, Full - - V Logic Input Low Voltage V IL,, Full V Logic Input Current I IN Full - - μ, Full - - μ Input Current (, ) (Note ) I IN = V, = V or. to.v V IN = V Full - - μ V IN = -7V Full μ river Three-State (high impedance) Output Current (, ) eceiver ifferential Threshold Voltage I O -7V V O V Full - - μ V TH -7V V CM V Full V eceiver Input Hysteresis ΔV TH V CM = V mv eceiver Output High Voltage V OH I O = -m, V I = mv Full. - - V eceiver Output Low Voltage V OL I O = -m, V I = mv Full - -. V Three-State (high impedance) eceiver Output Current I O.V V O.V Full - - ± μ eceiver Input esistance IN -7V V CM V Full 9 - kω No-Load Supply Current (Note ) I CC ISL89E,,, = V or Full - 9 μ ISL9E,,, = V or Full μ river Short-Circuit Current, V O = High or Low I OS =, -7V V or V V (Note ) Full - m eceiver Short-Circuit Current I OS V V O Full 7-8 m FN67.
5 Electrical Specifications Test Conditions: =.V to.v; Unless Otherwise Specified. Typicals are at = V, T = C, Note (Continued) PMETE SMOL TEST CONTIONS TEMP ( C) MIN TP MX UNITS SWITCHING CHCTEISTICS (ISL89E) river Input to Output elay t PLH, t PHL FF = Ω, C L = pf (Figure ) Full ns river Output Skew t SKEW FF = Ω, C L = pf (Figure ) Full ns river ifferential ise or Fall Time t, t F FF = Ω, C L = pf (Figure ) Full 6 ns river Enable to Output High t H C L = pf, SW = (Figure ) Full ns river Enable to Output Low t L C L = pf, SW = (Figure ) Full 86 ns river isable from Output High t H C L = pf, SW = (Figure ) Full 66 ns river isable from Output Low t L C L = pf, SW = (Figure ) Full 6 ns eceiver Input to Output elay t PLH, t PHL Figure Full ns eceiver Skew t PLH - t PHL t SK Figure ns eceiver Enable to Output High t H C L = pf, SW = (Figure ) Full - ns eceiver Enable to Output Low t L C L = pf, SW = (Figure ) Full - ns eceiver isable from Output High t H C L = pf, SW = (Figure ) Full - ns eceiver isable from Output Low t L C L = pf, SW = (Figure ) Full - ns Maximum ata ate f MX Full - - kbps SWITCHING CHCTEISTICS (ISL9E) river Input to Output elay t PLH, t PHL FF = Ω, C L = pf (Figure ) Full ns river Output Skew t SKEW FF = Ω, C L = pf (Figure ) Full - ns river ifferential ise or Fall Time t, t F FF = Ω, C L = pf (Figure ) Full ns river Enable to Output High t H C L = pf, SW = (Figure ) Full - 7 ns river Enable to Output Low t L C L = pf, SW = (Figure ) Full - 7 ns river isable from Output High t H C L = pf, SW = (Figure ) Full - 7 ns river isable from Output Low t L C L = pf, SW = (Figure ) Full - 7 ns eceiver Input to Output elay t PLH, t PHL (Figure ) Full 9 ns eceiver Skew t PLH - t PHL t SK (Figure ) - - ns eceiver Enable to Output High t H C L = pf, SW = (Figure ) Full - 9 ns eceiver Enable to Output Low t L C L = pf, SW = (Figure ) Full - 9 ns eceiver isable from Output High t H C L = pf, SW = (Figure ) Full - 9 ns eceiver isable from Output Low t L C L = pf, SW = (Figure ) Full - 9 ns Maximum ata ate f MX Full - - Mbps ES PEFOMNCE S-8 Pins (,,, ) Human ody Model - ± - kv ll Other Pins - >±7 - kv NOTES:. ll currents into device pins are positive; all currents out of device pins are negative. ll voltages are referenced to device ground unless otherwise specified.. Supply current specification is valid for loaded drivers when = V.. pplies to peak current. See Typical Performance Curves for more information.. evices meeting these limits are denoted as /8 unit load (/8 UL) transceivers. The S-8 standard allows up to Unit Loads on the bus, so there can be 6 /8 UL devices on a bus. FN67.
6 Test Circuits and Waveforms V O V OC FIGU. IVE V O N V OC.V.V V V t PLH t PHL SIGNL GENETO FF C L = pf C L = pf OUT () OUT () t PHL % % t PLH % % V OH V OL VOH V OL FF OUT ( - ) 9% 9% % % t t F +V O -V O SKEW = t PLH ( or ) - t PHL ( or ) FIGU. TEST CICUIT FIGU. MESUMENT POINTS FIGU. IVE PPGTION L N FFENTIL TNSITION TIMES 6 FN67.
7 Test Circuits and Waveforms (Continued) SIGNL GENETO C L Ω SW PMETE OUTPUT SW C L (pf) t H / X / t L / X / t H / X / t L / X / t H OUT (, ) t L OUT (, ) V.V.V V t H OUTPUT HIGH V V OH OH -.V.V V t L.V V OL +.V V OL OUTPUT LOW FIGU. TEST CICUIT FIGU. MESUMENT POINTS FIGU. IVE ENLE N SLE TIMES +.V pf.v.v V V t PLH t PHL SIGNL GENETO % % V FIGU. TEST CICUIT FIGU. MESUMENT POINTS FIGU. CEIVE PPGTION L SIGNL GENETO kω pf SW PMETE SW t H X +.V t L X -.V t H X +.V t L X -.V t H t L V.V.V V t H OUTPUT HIGH V V OH OH -.V.V V t L.V V OL +.VV OL OUTPUT LOW FIGU. TEST CICUIT FIGU. MESUMENT POINTS FIGU. CEIVE ENLE N SLE TIMES 7 FN67.
8 pplication Information S-8 and S- are differential (balanced) data transmission standards for use in long haul or noisy environments. S- is a subset of S-8, so S-8 transceivers are also S- compliant. S- is a pointto-multipoint (multidrop) standard, which allows only one driver and up to (assuming one unit load devices) receivers on each bus. S-8 is a true multipoint standard, which allows up to one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the S-8 spec requires that drivers must handle bus contention without sustaining any damage. nother important advantage of S-8 is the extended common mode range (CM), which specifies that the driver outputs and receiver inputs withstand signals that range from +V to -7V. S- and S-8 are intended for runs as long as, so the wide CM is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. eceiver Features These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is ±mv, as required by the S- and S-8 specifications. eceiver input resistance of kω surpasses the S- spec of kω, and is more than eight times the S-8 Unit Load requirement of kω. Thus, these products are known as one-eighth UL transceivers, and there can be up to 6 of these devices on a network while still complying with the S-8 loading spec. eceiver inputs function with common mode voltages as great as ±7V outside the power supplies (i.e., +V and -7V), making them ideal for long networks where induced voltages are a realistic concern. ll the receivers include a fail-safe if open function that guarantees a high level receiver output if the receiver inputs are unconnected (floating). eceivers easily meet the data rate supported by the corresponding driver, and receiver outputs are three-statable via the active low input. river Features The S-8/ driver is a differential output device that delivers at least.v across a Ω load (S-8), and at least V across a Ω load (S-). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI, and driver outputs are three-statable via the active high input. The ISL89E driver outputs are slew rate limited to further reduce EMI, and to minimize reflections in unterminated or improperly terminated networks. ata rates on these slew rate limited versions are a maximum of kbps. Outputs of ISL9E drivers are not limited, so faster output transition times allow data rates of at least Mbps. ata ate, Cables, and Terminations Twisted pair is the cable of choice for S-8/ networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. S-8/ are intended for network lengths up to, but the maximum system data rate decreases as the transmission length increases. evices operating at Mbps are limited to lengths of a few hundred feet, while the kbps versions can operate at full data rates with lengths in excess of. Proper termination is imperative, when using the Mbps devices, to minimize reflections. Short networks using the kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. uilt-in river Overload Protection s stated previously, the S-8 spec requires that drivers survive worst case bus contentions undamaged. The ISLXXE devices meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never exceeds the S-8 spec, even at the common mode voltage range extremes. dditionally, these devices utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. In the event of a major short circuit condition, ISLXXE devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically reenable after the die temperature drops about degrees. If the contention persists, the thermal shutdown/reenable cycle repeats until the fault is cleared. eceivers stay operational during thermal shutdown. 8 FN67.
9 ES Protection ll pins on these devices include class Human ody Model (HM) ES protection structures, but the S-8 pins (driver outputs and receiver inputs) incorporate advanced structures allowing them to survive ES events in excess of ±kv HM. The S-8 pins are particularly vulnerable to ES damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ES event that might destroy unprotected ICs. These new ES structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and without degrading the S-8 common mode range of -7V to +V. This built-in ES protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. Typical Performance Curves = V, T = C; Unless Otherwise Specified 9.6 IVE OUTPUT CUNT (m) FFENTIL OUTPUT VOLTGE (V).. FF = Ω.8.6. FF = Ω FFENTIL OUTPUT VOLTGE (V) TEMPETU ( C) FIGU 6. IVE OUTPUT CUNT vs FFENTIL OUTPUT VOLTGE FIGU 7. IVE FFENTIL OUTPUT VOLTGE vs TEMPETU OUTPUT CUNT (m) ISL89E - O = LOW ISL9E ISL9E ISL89E O = HIGH OUTPUT VOLTGE (V) FIGU 8. IVE OUTPUT CUNT vs SHOT CICUIT VOLTGE I CC (µ) ISL9E, = X, = X ISL89E, = X, = X TEMPETU ( C) FIGU 9. SUPPL CUNT vs TEMPETU 9 FN67.
10 Typical Performance Curves = V, T = C; Unless Otherwise Specified (Continued) 7 PPGTION L (ns) t PLH t PLH t PHL t PHL SKEW (ns) t PLH - t PHL t PHL - t PLH CSS PT. OF & - CSS PT. OF & TEMPETU ( C) FIGU. IVE PPGTION L vs TEMPETU (ISL89E) TEMPETU ( C) FIGU. IVE SKEW vs TEMPETU (ISL89E) PPGTION L (ns) t PLH t PLH t PHL t PHL TEMPETU ( C) FIGU. IVE PPGTION L vs TEMPETU (ISL9E) SKEW (ns) TEMPETU ( C) t PHL - t PLH t PLH - t PHL CSSING PT. OF & - CSSING PT. OF & FIGU. IVE SKEW vs TEMPETU (ISL9E) CEIVE OUTPUT (V) FF = Ω, C L = pf IVE INPUT (V) CEIVE OUTPUT (V) FF = Ω, C L = pf IVE INPUT (V) IVE OUTPUT (V) TIME (ns/v) FIGU. IVE N CEIVE WVEFOMS, LOW TO HIGH (ISL89E) IVE OUTPUT (V) TIME (ns/v) FIGU. IVE N CEIVE WVEFOMS, HIGH TO LOW (ISL89E) FN67.
11 Typical Performance Curves = V, T = C; Unless Otherwise Specified (Continued) CEIVE OUTPUT (V) FF = Ω, C L = pf IVE INPUT (V) CEIVE OUTPUT (V) FF = Ω, C L = pf IVE INPUT (V) IVE OUTPUT (V) TIME (ns/v) FIGU 6. IVE N CEIVE WVEFOMS, LOW TO HIGH (ISL9E) IVE OUTPUT (V) TIME (ns/v) FIGU 7. IVE N CEIVE WVEFOMS, HIGH TO LOW (ISL9E) ie Characteristics SUSTTE POTENTIL (POWE UP): TNSISTO COUNT: 8 PCESS: Si Gate icmos FN67.
12 Small Outline Plastic Packages (SOIC) ISL89E, ISL9E N INX e.(.) M C M E C- SETING PLNE S H.(.) M.(.) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. imensioning and tolerancing per NSI.M-98.. imension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side.. imension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width, as measured.6mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (. inch).. Controlling dimension: MILLIMETE. Converted inch dimensions are not necessarily exact. α L M h x o C M. (JEC MS-- ISSUE C) LE NW O SMLL OUTLINE PLSTIC PCKGE INCHES MILLIMETES SMOL MIN MX MIN MX NOTES C E e. SC.7 SC - H h L N 7 α o 8 o o 8 o - ev. /9 ll Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN67.
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Last Time Buy This part is in production but has been determined to be LAST TIME BUY. This classification indicates that the product is obsolete and notice has been given. Sale of this device is currently
The is a quad array of transient voltage clamping circuits designed to suppress ESD and other transient over-voltage events. The is used to help protect sensitive digital or analog input circuits on data,
a FEATURES High CMRR: db Typ Low Nonlinearity:.% Max Low Distortion:.% Typ Wide Bandwidth: MHz Typ Fast Slew Rate: 9.5 V/ s Typ Fast Settling (.%): s Typ Low Cost APPLICATIONS Summing Amplifiers Instrumentation
G48, G49 ata Sheet FN3283.8 Single 8-Channel/ifferential 4-Channel, CMOS Analog Multiplexers The G48 Single 8-Channel, and G49 ifferential 4-Channel monolithic CMOS analog multiplexers are drop-in replacements
Data Sheet 5 kv rms Signal Isolated High Speed CAN Transceiver with Bus Protection FEATURES 5 kv rms signal isolated CAN transceiver 5 V or 3.3 V operation on V DD1 5 V operation on V DD2 V DD2SENSE to
Low Capacitance Surface Mount TVS for High-Speed Data terfaces The LC3- transient voltage suppressor is designed to protect equipment attached to high speed communication lines from ESD, EFT, and lighting.
September 1986 Revised April 2000 DM74LS157 DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description These data selectors/multiplexers contain inverters and drivers to supply full
inc. High Speed, Four Channel MOSFET Driver with Non-Inverting Outputs Features Non-inverting, four channel MOSFET driver.0ns rise and fall time 2.0A peak output source/sink current 1. to 5.0V input CMOS
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
3-Channel Supervisor IC for Power Supply Features Over-voltage protection and lockout Under-voltage protection and lockout Open drain power good output signal Built-in 300mS delay for power good 38mS de-bounce
- RailClamp Description RailClamp TS diodes are specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage caused by ESD (electrostatic
ISL9204 Data Sheet FN9207.0 High Input Voltage Charger The ISL9204 is a cost-effective, fully integrated high input voltage single-cell Li-ion battery charger. This charger performs the CC/CV charge function
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated
CD4013BC Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors.
- RailClamp Description The RClamp 582BQ transient voltage suppressor is specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage
RS-485 Transceiver Tutorial Introduction TIA/EIA-485 and TIA/EIA-422 (also known as RS-485 and RS-422) are wired communication standards published by the Telecommunications Industry Association/Electronic
Data Sheet FN3158.8 4-Digit, LCD Display Driver The device is a non-multiplexed four-digit seven-segment CMOS LCD display decoder-driver. This device is configured to drive conventional LCD displays by
Features Functional Schematic High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost 4x4 mm, 20-lead PQFN Package 100% Matte
19-0426; Rev 0; 8/95 ±15k ES-rotected, Quad, General escription The 1489E quad, low-power line receiver is designed for EIA/TIA-232, EIA/TIA-562, and CCITT.28 communications in harsh environments. Each
October 1987 Revised March 2002 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits
Dual P-Channel Enhancement Mode MOSFET Features Pin Description -30V/-4.9, R DS(ON) =53mW(typ.) @ V GS =-10V R DS(ON) =80mW(typ.) @ V GS =-4.5V Reliable and Rugged Lead Free and Green Device vailable (RoHS
HFBR-0600Z Series SERCOS Fiber Optic Transmitters and Receivers Data Sheet SERCOS SERCOS is a SErial Realtime COmmunication System, a standard digital interface for communication between controls and drives
Data Sheet June 1999 File Number 2253.2 3A, 5V,.4 Ohm, N-Channel Power MOSFET This is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching
DATASHEET ICS7152 Description The ICS7152-01, -02, -11, and -12 are clock generators for EMI (Electro Magnetic Interference) reduction (see below for frequency ranges and multiplier ratios). Spectral peaks
DATASHEET ICS571 Description The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques.
DATASHEET ICS672-01/02 Description The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90 intervals. Based on IDT s proprietary low jitter Phase-Locked Loop
Quad Low Power RS85 Driver Features n Very Low Power: I CC = 0µA Typ n Designed for RS85 or RS Applications n Single 5V Supply n 7V to V Bus Common Mode Range Permits ±7V GND Difference Between Devices
3.3 V Zero Delay Clock Buffer The NB304A is a versatile, 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It
- RailClamp Description RailClamp TS diodes are specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage caused by ESD (electrostatic
- RailClamp Description RailClamps are ultra low capacitance TS arrays designed to protect high speed data interfaces. This series has been specifically designed to protect sensitive components which are
Use and Application of Output Limiting Amplifiers (HFA111, HFA110, HFA11) Application Note November 1996 AN96 Introduction Amplifiers with internal voltage clamps, also known as limiting amplifiers, have
INTEGRATED CIRCUITS IC24 Data Handbook 1997 Jun 30 FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5 V CMOS low power consumption
CMOS Phase Lock Loop General Description The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and
DATASHEET ICS650-44 Description The ICS650-44 is a spread spectrum clock synthesizer intended for video projector and digital TV applications. It generates three copies of an EMI optimized 50 MHz clock
MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise