DESCRIPTIO FEATURES APPLICATIO S TYPICAL APPLICATIO. LT1180A/LT1181A Low Power 5V RS232 Dual Driver/Receiver with 0.1µF Capacitors

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1 FEATRES APPLICATIO S ESD Protection over ±kv ses Small Capacitors: kbaud Operation for R L = k, C L = pf kbaud Operation for R L = k, C L = pf Outputs Withstand ±V Without Damage CMOS Comparable Low Power: mw Operates from a Single V Supply Rugged Bipolar Design Outputs Assume a High Impedance State When Off or Powered Down Meets All RS Specifications Available With or Without Shutdown Absolutely No Latch-up Available in SO Package Portable Computers Battery-Powered Systems Power Supply Generator Terminals DESCRIPTIO LTA/LT1A Low Power V RS Dual Driver/Receiver with Capacitors The LT A/LT1A are dual RS driver/receiver pairs with integral charge pump to generate RS voltage levels from a single V supply. These circuits feature rugged bipolar design to provide operating fault tolerance and ESD protection unmatched by competing CMOS designs. sing only external capacitors, these circuits consume only mw of power, and can operate to k baud even while driving heavy capacitive loads. New ESD structures on the chip allow the LTA/LT1A to survive multiple ±kv strikes, eliminating the need for costly TransZorbs on the RS line pins. The LTA/ LT1A are fully compliant with EIA RS standards. Driver outputs are protected from overload, and can be shorted to ground or up to ±V without damage. During shutdown or power-off conditions, driver and receiver outputs are in a high impedance state, allowing line sharing. The LT1A is available in 1-pin DIP and SO packages. The LTA is supplied in 1-pin DIP and SO packages for applications which require shutdown. Modems, LTC and LT are registered trademarks of Linear Technology Corporation. TransZorb is a registered trademark of General Instruments, GSI TYPICAL APPLICATIO LTA V INPT V OT V OT DRIVER OTPT R L = k C L = pf Output Waveforms LOGIC INPTS 1 RS OTPT RS OTPT RECEIVER OTPT R C L = pf LOGIC OTPTS k 1 RS INPT RS INPT INPT LTA TA ON/OFF 1 k 1 LTA TA1 1

2 LTA/LT1A ABSOLTE AXI RATI GS W W W Supply Voltage (V CC )... V V....V V....V Input Voltage Driver... V to V Receiver... V to V ON/OFF....V to V Output Voltage Driver... V V to V V Receiver....V to V CC.V (Note 1) Short-Circuit Duration V... sec V... sec Driver Output... Indefinite Receiver Output... Indefinite Operating Temperature Range LTAI/LT1AI... C to C LTAC/LT1AC... C to C Storage Temperature Range... C to 1 C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR NC C1 V C1 C C V TR OT REC IN 1 TOP VIEW ON/OFF V CC GND TR1 OT REC1 IN REC1 OT TR1 IN TR IN REC OT N PACKAGE SW PACKAGE 1-LEAD PDIP 1-LEAD PLASTIC SO (WIDE) T JMAX = C, θ JA = C/ W, θ JC = C/W (N) T JMAX = C, θ JA = C/ W, θ JC = C/W (SW) W J PACKAGE 1-LEAD CERDIP T JMAX = 1 C, θ JA = C/W, θ JC = C/W (J) OBSOLETE PACKAGE Consider N Package for Alternate Source ATIO ORDER PART NMBER LTACN LTACSW LTAIN LTAISW LTAMJ Consult LTC Marketing for parts specified with wider operating temperature ranges. C1 V C1 C C V TR OT REC IN 1 TOP VIEW 1 V CC 1 GND 1 TR1 OT REC1 IN REC1 OT TR1 IN TR IN REC OT N PACKAGE SW PACKAGE 1-LEAD PDIP 1-LEAD PLASTIC SO (WIDE) T JMAX = C, θ JA = C/ W, θ JC = C/W (N) T JMAX = C, θ JA = C/ W, θ JC = C/W (SW) J PACKAGE 1-LEAD CERDIP T JMAX = 1 C, θ JA = C/W, θ JC = C/W (J) OBSOLETE PACKAGE Consider N Package for Alternate Source ORDER PART NMBER LT1ACN LT1ACSW LT1AIN LT1AISW LT1AMJ ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the operating temperature range ( C T A C for commercial grade, and C T A C for industrial grade. (Note ) PARAMETER CONDITIONS TYP MAX NITS Power Supply Generator V Output. V V Output. V Supply Current (V CC ) (Note ), T A = C ma 1 ma Supply Current When OFF (V CC ) Shutdown (Note ) LTA Only 1 µa Supply Rise Time C1 = C = C = C =. ms Shutdown to Turn-On LTA Only. ms ON/OFF Pin Thresholds Input Low Level (Device Shutdown). 1. V Input High Level (Device Enabled) 1.. V

3 LTA/LT1A ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the operating temperature range ( C T A C for commercial grade, and C T A C for industrial grade. (Note ) PARAMETER CONDITIONS TYP MAX NITS ON/OFF Pin Current V V ON/OFF V 1 µa Oscillator Frequency khz Driver Output Voltage Swing Load = k to GND Positive.. V Negative.. V Logic Input Voltage Level Input Low Level (V OT = High) 1.. V Input High Level (V OT = Low). 1. V Logic Input Current.V V IN.V µa Output Short-Circuit Current V OT = V ± ma Output Leakage Current Shutdown V OT = ±V (Note ) µa Date Rate (Note ) R L = k, C L = pf kbaud R L = k, C L = pf kbaud Slew Rate R L = k, C L = 1pF 1 V/µs R L = k, C L = pf V/µs Propagation Delay Output Transition t HL High-to-Low (Note ). 1. µs Output Transition t LH Low-to-High. 1. µs Receiver Input Voltage Thresholds Input Low Threshold (V OT = High) C Grade. 1. V Input High Threshold (V OT = Low) C Grade 1.. V Input LowI, M Grade. 1. V Input HighI, M Grade 1.. V Hysteresis V Input Resistance V IN = ±V kω Output Leakage Current Shutdown (Note ) V OT V CC 1 µa Output Voltage Output Low, I OT = 1.mA.. V Output High, I OT = 1µA (V CC = V).. V Output Short-Circuit Current Sinking Current, V OT = V CC ma Sourcing Current, V OT = V ma Propagation Delay Output Transition t HL High-to-Low (Note ) ns Output Transition t LH Low-to-High ns Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note : Testing done at V CC = V and V ON/OFF = V, unless otherwise specified. Note : Supply current is measured as the average over several charge pump cycles. C = C = C1 = C =. All outputs are open, with all driver inputs tied high. Note : Supply current measurements in SHTDOWN are performed with V ON/OFF.1V. Note : For driver delay measurements, R L = k and C L = 1pF. Trigger points are set between the driver s input logic threshold and the output transition to the zero crossing (t HL = 1.V to V and t LH = 1.V to V). Note : For receiver delay measurements, C L = 1pF. Trigger points are set between the receiver s input logic threshold and the output transition to standard TTL/CMOS logic threshold (t HL = 1.V to.v and t LH = 1.V to.v). Note : Data rate operation guaranteed by slew rate, short-circuit current and propagation delay tests.

4 LTA/LT1A TYPICAL PERFOR A W CE CHARACTERISTICS PEAK OTPT VOLTAGE (V) Driver Maximum Output Voltage vs Load Capacitance kbad kbad kbad PEAK OTPT VOLTAGE (V) Driver Minimum Output Voltage vs Load Capacitance kbad kbad kbad DRIVER OTPT VOLTAGE (V) Driver Output Voltage R L = k V CC =.V V CC = V V CC =.V OTPT HIGH OTPT LOW V CC =.V V CC = V V CC =.V. 1 LOAD CAPACITANCE (nf). 1 LOAD CAPACITANCE (nf) TEMPERATRE ( C) LTA TPC1 LTA TPC LTA TPC THRESHOLD VOLTAGE (V) Receiver Input Thresholds INPT HIGH INPT LOW SPPLY CRRENT (ma) Supply Current vs Data Rate DRIVERS ACTIVE R L = k C L = pf THRESHOLD VOLTAGE (V) ON/OFF Thresholds... ON THRESHOLD OFF THRESHOLD.. TEMPERATRE ( C) DATA RATE (kbad) 1 TEMPERATRE ( C) LTA TPC LTA TPC LTA TPC Supply Current Driver Leakage in Shutdown Driver Short-Circuit Current SPPLY CRRENT (ma) 1 DRIVERS LOADED R L = k 1 DRIVER LOADED R L = k NO LOAD LEAKAGE CRRENT (µa) 1 V OT = V V OT = V SHORT-CIRCIT CRRENT (ma) 1 I SC I SC TEMPERATRE ( C).1 TEMPERATRE ( C) TEMPERATRE ( C) LTA TPC LTA TPC LTA TPC

5 LTA/LT1A TYPICAL PERFOR A W CE CHARACTERISTICS Receiver Short-Circuit Current 1 Slew Rate vs Load Capacitance SHORT-CIRCIT CRRENT (ma) RX I SC RX I SC SLEW RATE (V/µs) 1 SLEW SLEW TEMPERATRE ( C) LOAD CAPACITANCE (nf) LTA TPC LTA TPC DRIVER 1 OTPT DRIVER OTPT V V GND GND V V Shutdown to Driver Outputs DRIVER OTPT R L = k C L = pf DRIVER OTPT R L = k Driver Output Waveforms ON/OFF PIN INPT LTA TPC LTA TPC PI F CTIO S V CC : V Input Supply Pin. This pin should be decoupled with a ceramic capacitor close to the package pin. Insufficient supply bypassing can result in low output drive levels and erratic charge pump operation. GND: Ground Pin. ON/OFF: A TTL/CMOS Compatible Operating Mode Control. A logic low puts the LTA in shutdown mode. Supply current drops to zero and both driver and receiver outputs assume a high impedance state. A logic high fully enables the device. V : Positive Supply Output (RS Drivers). V V CC 1.V. This pin requires an external charge storage capacitor C, tied to ground or V CC. Larger value capacitors may be used to reduce supply ripple. With multiple transceivers, the V and V pins may be paralleled into common capacitors. V : Negative Supply Output (RS Drivers). V (V CC.V). This pin requires an external charge storage capacitor C. Larger value capacitors may be used to reduce supply ripple. With multiple transceivers, the V and V pins may be paralleled into common capacitors.

6 LTA/LT1A PI F CTIO S TR1 IN, TR IN: RS Driver Input Pins. These inputs are TTL/CMOS compatible. Inputs should not be allowed to float. Tie unused inputs to V CC. TR1 OT, TR OT: Driver Outputs at RS Voltage Levels. Driver output swing meets RS levels for loads up to k. Slew rates are controlled for lightly loaded lines. Output current capability is sufficient for load conditions up to pf. Outputs are in a high impedance state when in shutdown mode, V CC = V, or when the driver disable pin is active. Outputs are fully short-circuit protected from V V to V V. Applying higher voltages will not damage the device if the overdrive is moderately current limited. Short circuits on one output can load the power supply generator and may disrupt the signal levels of the other outputs. The driver outputs are protected against ESD to ±kv for human body model discharges. REC1 IN, REC IN: Receiver Inputs. These pins accept RS level signals (±V) into a protected k terminating resistor. The receiver inputs are protected against ESD to ±kv for human body model discharges. Each receiver provides.v of hysteresis for noise immunity. Open receiver inputs assume a logic low state. REC1 OT, REC OT: Receiver outputs with TTL/CMOS Voltage Levels. Outputs are in a high impedance state when in shutdown mode to allow data line sharing. Outputs are fully short-circuit protected to ground or V CC with the power on, off or in the shutdown mode. C1, C1, C, C : Commutating Capacitor Inputs. These pins require two external capacitors C : one from C1 to C1 and another from C to C. C1 should be deleted if a separate V supply is available and connected to pin C1. Similarly, C should be deleted if a separate V supply is connected to pin V. ESD PROTECTIO The RS line inputs of the LTA/LT1A have onchip protection from ESD transients up to ±kv. The protection structures act to divert the static discharge safely to system ground. In order for the ESD protection to function effectively, the power supply and ground pins of the circuit must be connected to ground through low impedances. The power supply decoupling capacitors and charge pump storage capacitors provide this low impedance in normal application of the circuit. The only constraint is that low ESR capacitors must be used for bypassing and charge storage. ESD testing must be done with pins V CC, V L, V, V, and GND shorted to ground or connected with low ESR capacitors. RS LINE PINS PROTECTED TO ±kv 1 ESD Test Circuit NC C1 LTA V C1 C C V DR OT RX IN ON/OFF V V CC GND DR1 OT RX1 IN RX1 OT DR1 IN DR IN RX OT RS LINE PINS PROTECTED TO ±kv LTA ESD TC

7 LTA/LT1A TYPICAL APPLICATI O Supporting an LT (Triple Driver/Receiver) SHTDOWN 1 ON/OFF V CC LTA TTL INPT RS OTPT TTL INPT 1 RS OTPT TTL OTPT 1 RS INPT k V 1 V CC ON/OFF LT 1 TTL INPT RS OTPT TTL INPT TTL INPT RS OTPT RS OTPT 1 TTL OTPT RS INPT k TTL OTPT 1µF 1µF C1 C1 C C k V V GND 1 1 RS INPT TTL OTPT TTL OTPT 1 1µF 1µF V V k k GND RS INPT RS INPT LTA TA

8 PACKAGE DESCRIPTIO LTA/LT1A CORNER LEADS OPTION ( PLCS) J Package 1-Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # --). (.). (1.) MAX (1. 1.) FLL LEAD OPTION. BSC (. BSC).. (. 1.) HALF LEAD OPTION. (.) RAD TYP 1.. (..). (.) MAX.1. (. 1.)..1 (..) 1 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS. (.).. (1. 1.1).1. (..). (.) BSC J1.. (1. 1.) FLL LEAD OPTION CORNER LEADS OPTION ( PLCS). BSC (. BSC).. (. 1.) HALF LEAD OPTION J Package 1-Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # --). (.). (.) RAD TYP.1. (. 1.) 1. (.) MAX (..). (.) MAX..1 (..) 1 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS. (.) OBSOLETE PACKAGES.. (1. 1.1).1. (..). (.) BSC J1

9 PACKAGE DESCRIPTIO LTA/LT1A N Package 1-Lead PDIP (Narrow. Inch) (Reference LTC DWG # --1).* (1.) MAX ±.1* (. ±.1) 1.. (..). ±. (. ±.).. (1. 1.1)..1 (..1) ( ). (.). (.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) BSC. (1.1) TYP.1 ±. (. ±.) N1 N Package 1-Lead PDIP (Narrow. Inch) (Reference LTC DWG # --1).* (.) MAX ±.1* (. ±.1).. (..). ±. (. ±.) 1.. (1. 1.1)..1 (..1). (.). (1.1) TYP ( ). (.). (.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) BSC.1 ±. (. ±.) N1

10 PACKAGE DESCRIPTIO LTA/LT1A SW Package 1-Lead Plastic Small Outline (Wide. Inch) (Reference LTC DWG # --1)..* (..) NOTE 1..1 (..).1.** (.1.).. (..).. (..) 1.. (. 1.) TYP.. (..). (1.) BSC.1.1 (..) TYP NOTE 1.1. (. 1.) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.1mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..) S1 (WIDE)

11 PACKAGE DESCRIPTIO LTA/LT1A SW Package 1-Lead Plastic Small Outline (Wide. Inch) (Reference LTC DWG # --1)..* (..) NOTE 1..1 (..).1.** (.1.).. (..).. (..) 1.. (. 1.) TYP.. (..) NOTE 1.1. (. 1.). (1.) BSC.1.1 (..) TYP NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.1mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..) S1 (WIDE) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

12 LTA/LT1A TYPICAL APPLICATI O Operation sing V and V Power Supplies V INPT V INPT LTA V OT 1 RS OTPT LOGIC INPTS RS OTPT LOGIC OTPTS k 1 RS INPT RS INPT k ON/OFF 1 1 LTA TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTA/LT1A V -Driver/-Receiver RS Transceivers Pin Compatible with LTA/LT1A, I CC = ma Max LT1 V -Driver/-Receiver RS Transceiver Narrow 1-Pin SO Package LT/LT1 V -Driver/-Receiver RS Transceivers IEC -- Level Compliance Linear Technology Corporation McCarthy Blvd., Milpitas, CA - () -1 FAX: () - LT/CPI /1 REV B 1.K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 1