5 V Low Power EIA RS-485 Transceiver ADM1485

Transcription

1 a FETUES Meets EI S-85 Standard 3 Mbps Data ate Single 5 V Supply 7 V to +2 V us Common-Mode ange High Speed, Low Power icmos Thermal Shutdown Protection Short-Circuit Protection Driver Propagation Delay: ns eceiver Propagation Delay: 5 ns High-Z Outputs with Power Off Superior Upgrade for LTC85 5 V Low Power EI S-85 Transceiver DM85 FUNCTIONL LOCK DIGM 8-Lead O E DE DM85 V CC PPLICTIONS Low Power S-85 Systems DTE-DCE Interface Packet Switching Local rea Networks Data Concentration Data Multiplexers Integrated Services Digital Network (ISDN) DI D GND GENEL DESCIPTION The DM85 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with both S-85 and S-22 EI Standards. The part contains a differential line driver and a differential line receiver. oth the driver and the receiver may be enabled independently. When disabled, the outputs are three-stated. The DM85 operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state if, during fault conditions, a significant temperature increase is detected in the internal driver circuitry. Up to 32 transceivers may be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the DM85 driver features high output impedance when disabled and also when powered down. This minimizes the loading effect when the transceiver is not being used. The high impedance driver output is maintained over the entire common-mode voltage range from 7 V to +2 V. The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The DM85 is fabricated on icmos, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. ll inputs and outputs contain protection against ESD; all driver outputs feature high source and sink current capability. n epitaxial layer is used to guard against latch-up. The DM85 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at typical data rates of 3 Mbps while low skew minimizes EMI interference. The part is fully specified over the commercial and industrial temperature range and is available in PDIP, SOIC, and small MSOP packages. EV. Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. ox 96, Norwood, M , U.S.. Tel: 78/ Fax: 78/ nalog Devices, Inc. ll rights reserved.

2 DM85 SPECIFICTIONS (V CC = 5 V 5%. ll specifications T MIN to T MX, unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments DIVE Differential Output Voltage, V OD 5. V =, Test Circuit V V CC = 5 V, = 5 Ω (S-22), Test Circuit.5 5. V = 27 Ω (S-85), Test Circuit V OD V V TST = 7 V to +2 V, Test Circuit 2 Δ V OD for Complementary Output States.2 V = 27 Ω or 5 Ω, Test Circuit Common-Mode Output Voltage V OC 3 V = 27 Ω or 5 Ω, Test Circuit Δ V OD for Complementary Output States.2 V = 27 Ω or 5 Ω Output Short-Circuit Current (V OUT = High) m 7 V V O +2 V Output Short-Circuit Current (V OUT = Low) m 7 V V O +2 V CMOS Input Logic Threshold Low, V INL.8 V CMOS Input Logic Threshold High, V INH 2. V Logic Input Current (DE, DI) ±. μ ECEIVE Differential Input Threshold Voltage, V TH V 7 V V CM +2 V Input Voltage Hysteresis, ΔV TH 7 mv V CM = V Input esistance 2 kω 7 V V CM +2 V Input Current (, ) m V IN = +2 V.8 m V IN = 7 V CMOS Input Logic Threshold Low, V INL.8 V CMOS Input Logic Threshold High, V INH 2. V Logic Enable Input Current (E) ± μ CMOS Output Voltage Low, V OL. V I OUT = +. m CMOS Output Voltage High, V OH. V I OUT =. m Short-Circuit Output Current 7 85 m V OUT = GND or V CC Three-State Output Leakage Current ±. μ. V V OUT 2. V POWE SUPPLY CUENT I CC (Outputs Enabled). 2.2 m Digital Inputs = GND or V CC I CC (Outputs Disabled).6 m Digital Inputs = GND or V CC Specifications subject to change without notice. TIMING SPECIFICTIONS Parameter Min Typ Max Unit Test Conditions/Comments DIVE Propagation Delay Input to Output t PLH, t PHL 2 5 ns LDIFF = 5 Ω, C L = C L2 = pf, Test Circuit 3 Driver O/P to O/P t SKEW 5 ns LDIFF = 5 Ω, C L = C L2 = pf, Test Circuit 3 Driver ise/fall Time t, t F 8 5 ns LDIFF = 5 Ω, C L = C L2 = pf, Test Circuit 3 Driver Enable to Output Valid 25 ns L = Ω, C L = 5 pf, Test Circuit Driver Disable Timing 25 ns L = Ω, C L = 5 pf, Test Circuit Matched Enable Switching 2 ns L = Ω, C L = 5 pf, Test Circuit * t ZH t ZL, t ZH t ZL Matched Disable Switching 2 ns L = Ω, C L = 5 pf, Test Circuit * t HZ t LZ, t HZ t LZ ECEIVE Propagation Delay Input to Output t PLH, t PHL ns C L = 5 pf, Test Circuit 5 Skew t PLH t PHL 5 ns C L = 5 pf, Test Circuit 5 eceiver Enable t EN 5 2 ns C L = 5 pf, L = kω, Test Circuit 6 eceiver Disable t EN2 5 2 ns C L = 5 pf, L = kω, Test Circuit 6 Tx Pulse Width Distortion ns x Pulse Width Distortion ns *Guaranteed by characterization. Specifications subject to change without notice. (V CC = 5 V 5%. ll specifications T MIN to T MX, unless otherwise noted.) 2 EV.

3 DM85 SOLUTE MXIMUM TINGS* (T = 25 C, unless otherwise noted.) V CC V to +7 V Inputs Driver Input (DI) V to V CC +.3 V Control Inputs (DE, E) V to V CC +.3 V eceiver Inputs (, ) V to + V Outputs Driver Outputs (, ) V to + V eceiver Output V to V CC +.5 V Power Dissipation 8-Lead MSOP mw θ J, Thermal Impedance C/W Power Dissipation 8-Lead PDIP mw θ J, Thermal Impedance C/W Power Dissipation 8-Lead SOIC mw θ J, Thermal Impedance C/W Operating Temperature ange Commercial (J Version) C to 7 C Industrial ( Version) C to +85 C Storage Temperature ange C to +5 C Lead Temperature (Soldering, sec) C Vapor Phase (6 sec) C Infrared (5 sec) C *Stresses above those listed under bsolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. PIN FUNCTION DESCIPTIONS Pin Mnemonic Function No. O eceiver Output. When enabled if > by 2 mv, then O = High. If < by 2 mv, then O = Low. 2 E eceiver Output Enable. low level enables the receiver output, O. high level places it in a high impedance state. 3 DE Driver Output Enable. high level enables the driver differential outputs, and. low level places it in a high impedance state. DI Driver Input. When the driver is enabled, a logic low on DI forces low and high while a logic high on DI forces high and low. 5 GND Ground Connection, V. 6 Noninverting eceiver Input /Driver Output. 7 Inverting eceiver Input /Driver Output 8 V CC Power Supply, 5 V ± 5%. PIN CONFIGUTION O E DE DI V CC GND Inputs Table I. Transmitting Outputs 2 3 DM85 TOP VIEW (Not to Scale) DE DI X Z Z Table II. eceiving Inputs Outputs E - O +.2 V.2 V Inputs Open X Z CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. lthough the DM85 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. EV. 3

4 DM85 Test Circuits V CC V OD V OC V O 3V DE S C L L V OUT S2 DE IN Test Circuit. Driver Voltage Measurement Test Circuit. Driver Enable/Disable 375 V OD3 6 V TST E V OUT 375 C L Test Circuit 2. Driver Voltage Measurement Test Circuit 5. eceiver Propagation Delay + V CC LDIFF C L C L2 E IN S E C L L V OUT S2 Test Circuit 3. Driver Propagation Delay Test Circuit 6. eceiver Enable/Disable Switching Characteristics 3V V /2VO t PLH t PHL, V V V O V O V V O 9% POINT % POINT t t SKEW = t PLH t PHL 9% POINT t F % POINT O t PLH t SKEW = t PLH t PHL t PHL V OH V OL Figure. Driver Propagation Delay, ise/fall Timing Figure 3. eceiver Propagation Delay 3V 3V DE E V V t ZL t LZ t ZL t LZ, 2.3V V OL +.5V V OL O/P LOW V OL +.5V V OL, t ZH 2.3V t HZ V OH.5V V OH V t ZH O/P HIGH t HZ V OH.5V V OH V Figure 2. Driver Enable/Disable Timing Figure. eceiver Enable/Disable Timing EV.

5 Typical Performance Characteristics DM I = 8m OUTPUT CUENT m OUTPUT VOLTGE V OUTPUT VOLTGE V TEMPETUE C TPC. Output Current vs. eceiver Output Low Voltage TPC. eceiver Output Low Voltage vs. Temperature OUTPUT CUENT m OUTPUT CUENT m OUTPUT VOLTGE V OUTPUT VOLTGE V TPC 2. Output Current vs. eceiver Output High Voltage TPC 5. Output Current vs. Driver Differential Output Voltage OUTPUT VOLTGE V I = 8m DIFFEENTIL VOLTGE V TEMPETUE C TEMPETUE C TPC 3. eceiver Output High Voltage vs. Temperature TPC 6. Driver Differential Output Voltage vs. Temperature, L = 26.8 Ω EV. 5

6 DM OUTPUT CUENT m TIME ns t PLH t PHL OUTPUT VOLTGE V TEMPETUE C TPC 7. Output Current vs. Driver Output Low Voltage TPC. x Skew vs. Temperature OUTPUT CUENT m TIME ns 3 2 t PHL t PHL t PLH t PLH OUTPUT VOLTGE V TEMPETUE C TPC 8. Output Current vs. Driver Output High Voltage TPC. Tx Skew vs. Temperature....2 SUPPLY CUENT m DIVE ENLED DIVE DISLED PWD t PLH t PHL TEMPETUE C TPC 9. Supply Current vs. Temperature TEMPETUE C TPC 2. Tx Pulse Width Distortion 5 6 EV.

7 DM85 DI, 2, 2 3 O TPC 3. Unloaded Driver Differential Outputs TPC 6. Driver/eceiver Propagation Delays High to Low, 2, 2 TPC. Loaded Driver Differential Outputs TPC 7. Driver Output at 3 Mbps DI, 2 O 3 TPC 5. Driver/eceiver Propagation Delays Low to High EV. 7

8 DM85 PPLICTION INFOMTION Differential Data Transmission Differential data transmission is used to reliably transmit data at high rates over long distances and through noisy environments. Differential transmission nullifies the effects of ground shifts and noise signals that appear as common-mode voltages on the line. There are two main standards approved by the Electronics Industries ssociation (EI) that specify the electrical characteristics of transceivers used in differential data transmission. The S-22 standard specifies data rates up to Maud and line lengths up to ft. single driver can drive a transmission line with up to receivers. In order to cater to true multipoint communications, the S-85 standard was defined. This standard meets or exceeds all the requirements of the S-22 but also allows for up to 32 drivers and 32 receivers to be connected to a single bus. n extended common-mode range of 7 V to +2 V is defined. The most significant difference between the S-22 and the S-85 is the fact that the drivers may be disabled, thereby allowing more than one (32 in fact) to be connected to a single line. Only one driver should be enabled at a time, but the S-85 standard contains additional specifications to guarantee device safety in the event of line contention. Table III. Comparison of S-22 and S-85 Interface Standards Specification S-22 S-85 Transmission Type Differential Differential Maximum Cable Length ft. ft. Minimum Driver Output Voltage ± 2 V ±.5 V Driver Load Impedance Ω 5 Ω eceiver Input esistance kω min 2 kω min eceiver Input Sensitivity ± 2 mv ± 2 mv eceiver Input Voltage ange 7 V to +7 V 7 V to +2 V No. of Drivers/eceivers per Line / 32/32 Cable and Data ate The transmission line of choice for S-85 communications is a twisted pair. Twisted pair cable tends to cancel common-mode noise and also causes cancellation of the magnetic fields generated by the current flowing through each wire, thereby reducing the effective inductance of the pair. The DM85 is designed for bidirectional data communications on multipoint transmission lines. typical application showing a multipoint transmission network is illustrated in Figure 5. n S-85 transmission line can have as many as 32 transceivers on the bus. Only one driver can transmit at a particular time, but multiple receivers may be enabled simultaneously. s with any transmission line, it is important that reflections are minimized. This can be achieved by terminating the extreme ends of the line using resistors equal to the characteristic impedance of the line. Stub lengths of the main line should also be kept as short as possible. properly terminated transmission line appears purely resistive to the driver. D T D Figure 5. Typical S-85 Network Thermal Shutdown The DM85 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature and disables the driver outputs. The thermal sensing circuitry is designed to disable the driver outputs when a die temperature of 5 C is reached. s the device cools, the drivers are re-enabled at C. Propagation Delay The DM85 features very low propagation delay, ensuring maximum baud rate operation. The driver is well balanced, ensuring distortion free transmission. nother important specification is a measure of the skew between the complementary outputs. Excessive skew impairs the noise immunity of the system and increases the amount of electromagnetic interference (EMI). eceiver Open-Circuit Fail-Safe The receiver input includes a fail-safe feature that guarantees a logic high on the receiver when the inputs are open circuit or floating. D T D 8 EV.

9 DM85 OUTLINE DIMENSIONS 5. (.968).8 (.89). (.57) 3.8 (.97) (.2) 5.8 (.228).25 (.98). (.) COPLNITY. SETING PLNE.27 (.5) SC.75 (.688).35 (.532).5 (.2).3 (.22) 8.25 (.98).7 (.67).5 (.96).25 (.99).27 (.5). (.57) 5 COMPLINT TO JEDEC STNDDS MS-2- CONTOLLING DIMENSIONS E IN MILLIMETES; INCH DIMENSIONS (IN PENTHESES) E OUNDED-OFF MILLIMETE EQUIVLENTS FO EFEENCE ONLY ND E NOT PPOPITE FO USE IN DESIGN. Figure 6. 8-Lead Standard Small Outline Package [SOIC_N] Narrow ody (-8) Dimensions shown in millimeters and (inches) PIN IDENTIFIE.65 SC COPLNITY MX 6 5 MX.23.9 COMPLINT TO JEDEC STNDDS MO-87- Figure 7. 8-Lead Mini Small Outline Package [MSOP] (M-8) Dimensions shown in millimeters EV. F 9

10 DM85. (.6).365 (9.27).355 (9.2).2 (5.33) MX.5 (3.8).3 (3.3).5 (2.92).22 (.56).8 (.6). (.36) 8. (2.5) SC 5.28 (7.).25 (6.35).2 (6.).5 (.38) MIN SETING PLNE.5 (.3) MIN.6 (.52) MX.5 (.38) GUGE PLNE.325 (8.26).3 (7.87).3 (7.62).3 (.92) MX.95 (.95).3 (3.3).5 (2.92). (.36). (.25).8 (.2).7 (.78).6 (.52).5 (.) COMPLINT TO JEDEC STNDDS MS- CONTOLLING DIMENSIONS E IN INCHES; MILLIMETE DIMENSIONS (IN PENTHESES) E OUNDED-OFF INCH EQUIVLENTS FO EFEENCE ONLY ND E NOT PPOPITE FO USE IN DESIGN. CONE LEDS MY E CONFIGUED S WHOLE O HLF LEDS. Figure 8. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow ody (N-8) Dimensions shown in inches and (millimeters) 766- ODEING GUIDE Model Temperature ange Package Description Package Option rand DM85JNZ C to 7 C 8-Lead PDIP N-8 DM85JZ C to 7 C 8-Lead SOIC_N -8 DM85J-EEL C to 7 C 8-Lead SOIC_N -8 DM85JZ-EEL C to 7 C 8-Lead SOIC_N -8 DM85NZ C to +85 C 8-Lead PDIP N-8 DM85MZ C to +85 C 8-Lead MSOP M-8 M2 DM85MZ-EEL C to +85 C 8-Lead MSOP M-8 M2 DM85MZ-EEL7 C to +85 C 8-Lead MSOP M-8 M2 DM85Z 8-Lead SOIC_N -8 DM85Z-EEL 8-Lead SOIC_N -8 DM85Z-EEL7 8-Lead SOIC_N -8 DM85JCHIPS Die Z = ohs Compliant Part. EV. F

11 DM85 EVISION HISTOY 8/2 ev. E to ev. F Changed Data ates of Up to 5 Mbps to Typical Data ates of 3 Mbps... Updated Outline Dimensions... 9 Changes to Ordering Guide... 9/3 Data Sheet changed from EV. D to EV. E. Change to SPECIFICTIONS... 2 Changes to ODEING GUIDE... 3 Updated OUTLINE DIMENSIONS /3 Data Sheet changed from EV. C to EV. D. Changes to SPECIFICTIONS... 2 Changes to SOLUTE MXIMUM TINGS... 3 Updated ODEING GUIDE... 3 /3 Data Sheet changed from EV. to EV. C. Change to SPECIFICTIONS... 2 Change to ODEING GUIDE /2 Data Sheet changed from EV. to EV.. Deleted Q-8 Package... Universal Edits to FETUES... Edits to GENEL DESCIPTION... Edits, additions to SPECIFICTIONS... 2 Edits, additions to SOLUTE MXIMUM TINGS... 3 dditions to ODEING GUIDE... 3 TPCs updated and reformatted... 5 ddition of 8-Lead MSOP Package... 9 Update to OUTLINE DIMENSIONS nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D63--8/2(F) EV. F