ELEN 468 Advanced Logic Design (Spring 2001) Lab #8 Timing Analysis using PrimeTime
|
|
- Gregory Melton
- 7 years ago
- Views:
Transcription
1 ELEN 468 Advanced Logic Design (Spring 2001) Lab #8 Timing Analysis using PrimeTime Introduction: PrimeTime is the Synopsys stand-alone full chip, gate-level static timing analyzer. It analyzes the timing of large, synchronous, digital ASIC s. PrimeTime works with designs at the gate level, providing a tight integration with other Synopsys tools. PrimeTime has features that make it suitable for analyzing large, system-on-a-chip (SOC) designs. Primetime is synthesis-compatible, and you can use it throughout your design process. Basic Features: The following timing checks can be performed on a design Setup and hold checks Recovery and removal checks Clock pulse width checks Clock gating checks The following design checks can be preformed with the help of PrimeTime Unclocked registers Unconstrained timing endpoints Master-Slave clock separation Multiple clocked registers Level-sensitive clocking Combinational feedback loops Design rule checks on maximum capacitance, transition time and fanout. Timing Analysis Flow and Methodology 1. setup the design environment - set the search path and the link path - read the design and the libraries - link the top design - set up the operating conditions, wireload models, port load, drive and transition time
2 2. Specify the timing assertions - define the clock period, waveform, uncertainty and latency - specify the input and output port delays 3. Specify the timing exceptions - set multicycle paths - set false paths - specify minimum and maximum delays, path segmentation and disabled arcs 4. Perform the analysis and create reports - Check timing - Generate constraint reports - Generate path timing reports Setup Information PrimeTime is capable of reading industry standard file formats including vhdl, verilog, EDIF and SDF. PrimeTime requires.synopsys_pt.setup file to be able to run. Make a new directory under tutorial, and create a.synopsys_pt.setup file in it. The file should contain the following:. synopsys_pt.setup set search_path ". /jumbo/synopsys/2000.5/libraries/syn" set link_path "* class.db" set sh_enable_page_mode true The variable search_path defines a list of directories to look into while searching for libraries and designs. The variable link_path defines a list of libraries containing cells to be used for linking the design. These libraries are searched in the directories specified in the search_path. By setting the sh_enable_page_mode as true, the output is paged each time you use Primetime. PrimeTime handles the following input files... Design files - in vhdl, db, verilog or in any industry standard file formats Technology library - in db format Timing model scripts -.pt formats Stamp data and models -.data and.mod files
3 Starting PrimeTime: Change to the new directory created above and type Primetime &. This opens the PrimeTime tool. At the bottom of the window, there is a small box (called the pt_shell) where you type all the commands. Getting Help: To get a basic summary of all the PrimeTime commands, enter Primetime> help Use the help verbose command to get command syntax information. Enter Primetime> help verbose <command > Use the man pages for detailed help for each command and variable. To access the man pages, enter man followed by the name of the command or variable. Reading the design: PrimeTime works on gate-level netlist files in any of the following formats: - Synopsys database files (.db) - Verilog netlist files - Electronic Data Interchange Format (EDIF) netlist files - VHDL netlist files So the verilog code has to be synthesized to gate-level netlist before using PrimeTime on the design. To generate the gate-level netlist file: 1. Open the design_analyzer & window. 2. Analyze & Elaborate the design. 3. The design has to be optimized using the tools->design optimization menu. 4. At the end of optimization, select the top module (in the hierarchy) and save the file. For reading the design, enter Primetime> read_verilog flip_flop. This command will read in the module flip_flop.
4 Linking the Design: The link process resolves the design references and connects the designs and components from the library. Primetime> link_design flip_flop This command will link all the libraries and designs linked to the design flip_flop. Performing Timing Analysis: 1. Setting up Operating conditions, wire models and drive and transition time Primetime> set_operating_conditions -library pt_lib -min BCCOM -max WCCOM Primetime> set_wire_load_mode top Primetime> set_wire_load_model -library pt_lib -name 05x05 -min Primetime> set_wire_load_model -library pt_lib -name 20x20 -max The above set of commands set up the operating conditions and wire models by linking to already existing models. PrimeTime uses - Maximum operating conditions and wire load model when it generates setup timing reports. - Minimum operating conditions and wire load model when it generates hold timing reports. 2. Setting Up the Basic Timing Assertions The following set of commands define the clock period, skew and latency (insertion delay) Primetime> create_clock -period 30 [get_ports CLOCK] Primetime> set clock [get_clock CLOCK] Primetime> set_clock_uncertainty 0.5 $clock Primetime> set_clock_latency -min 3.5 $clock Primetime> set_clock_latency -max 5.5 $clock for setting transition times Primetime> set_clock_transition -min 0.25 $clock Primetime> set_clock_transition -max 0.3 $clock The clock gating setup and hold values and a minimum pulse width are defined Primetime> set_clock_gating_check -setup 0.5 -hold 0.1 $clock Primetime> set_min_pulse_width 2.0 $clock
5 You can do all of the above-mentioned tasks by writing them all in a single script file. The file contains commands to read & link the design, setting up the various conditions. The file should have an extension.st, which is a TCL file. The file can be executed by typing Primetime> source flip_flop.st Where flip_flop.st is the file containing the various commands. After the execution, Primetime tells you if the file has been properly read and linked. The things to keep in mind when writing this script file is: - read_design: contains the design s gate-level netlist file - current_design: contains the design module name - link_design: contains the design module name. Running Basic Analysis: Constraint and timing reports are generated with the help of - report_constraint - report_timing commands. The report_constraint command reports the timing violations and constraints violations, whereas the report_timing command provides path-based timing reports. Reports: The following commands are used to generate basic reports - Primetime> report_design The report_design command shows the min-max operating condition and wire load models. - Primetime> report_reference The report_reference command shows each block and its area. More important, it identifies the extracted, Stamp, and quick timing models.
6 Example: The following example shows how to generate the timing analysis for a D-flipflop. 1) Write the Behavioral or structural code for D-flipflop (flipflop.v): module flip_flop(q,data_in,clk,rst); input data_in,clk,rst; output q; reg q; clk) begin if(rst==1) q=0; else q = data_in; end endmodule 2) Analyze and Elaborate the design using design_analyzer. 3) Optimize the design. Save the top model (in the hierarchy) as a verilog file. 4) Write a script file (flipflop_st.v) which contains the commands to read & link the design and setting the various conditions like operating environment, wire load, input drive strength etc.
7 #************************************************** #Define top design read_verilog "flipflop.v" current_design flip_flop link_design flip_flop #************************************************** #Design environment set_operating_conditions -library {class} -analysis_type single WCCOM set _wire_load_mode top set_driving_cell -lib_cell IBUF1 -library class [ all_inputs ] #************************************************** #************************************************* #Clock specification and design constraints create_clock -period waveform { } {clk} #set_propagated_clock [get_clocks clk] #set_clock_uncertainty 0.5 -setup [get_clocks clk] #************************************************ #Timing analysis commands #report_constraint -all_violators #report_timing -to [all_registers -data_pins] #report_timing -delay_type min_max -to comp1/u10/a #report_timing -delay_type min_max -to comp1/u10/b - Define top design defines the file to be read and linked. - Design Environment sets the operating conditions, wire load etc.. - Clock specification defines the clock period. - # indicate comments.
8 5) Execute the file by typing: Primetime> source flipflop_st.v 6) Write another script file (test.st), which does the timing analysis. set slack 0 foreach_selection cell [all_registers] { set cellname [get_attribute $cell full_name] } foreach_selection spin [get_pins "$cellname/*"] { set pinname [get_attribute $spin full_name -quiet] set curpath [get_timing_paths -delay_type max -to $pinname] set slack [get_attribute $curpath slack] if {$slack < 0} { report_timing -delay_type max -to $spin } } This file identifies the various pins where the timing is not met. Run this script by typing Primetime> source test.st Primetime identifies the pins where the timing conditions are not met. It prints out the pins where the slack (difference between the data required and arrival time) is negative and timing condition is violated. 7) Go back to the flipflop_st.v file and change the clock period to 3, also changing the waveform as { }. 8) Execute the script and you will notice that all the conditions are met. 9) The basic idea is to identify the minimum clock period, which satisfies the timing conditions. 10) Get constraint report and evaluate the violations. Enter Primetime> report_constraint all_violations
9 Lab assignment: 1. Try the example given above and get an idea of using Primetime. 2. Use the verilog code for MIPS processor and generate the timing results for the design. You will identify the clock period, which satisfies the timing conditions. The clock period is in ns, and so finding the inverse of the clock period will give the frequency you processor operates. Generate waveforms using signalscan in Synopsys: Include these lines in.cshrc file: setenv CDS_INST_DIR /jumbo/cadence/ic443/tools/ldv source /usr/local/bin/setup.signalscan And in the stimulus file of your design, include these statements initial begin $shm_open(); $shm_probe("ac"); end
STA - Static Timing Analysis. STA Lecturer: Gil Rahav Semester B, EE Dept. BGU. Freescale Semiconductors Israel
STA - Static Timing Analysis STA Lecturer: Gil Rahav Semester B, EE Dept. BGU. Freescale Semiconductors Israel Static Verification Flow RTL Domain Synthesis Functional Simulation Testbench Equivalence
More informationGetting the Most Out of Synthesis
Outline Getting the Most Out of Synthesis Dr. Paul D. Franzon 1. Timing Optimization Approaches 2. Area Optimization Approaches 3. Design Partitioning References 1. Smith and Franzon, Chapter 11 2. D.Smith,
More informationHigh Fanout Without High Stress: Synthesis and Optimization of High-fanout Nets Using Design Compiler 2000.11
High Fanout Without High Stress: Synthesis and Optimization of High-fanout Nets Using Design Compiler 2000.11 Rick Furtner Tensilica, Inc rfurtner@tensilica.com ABSTRACT High fanout nets, especially resets
More informationUniversity of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design
University of Texas at Dallas Department of Electrical Engineering EEDG 6306 - Application Specific Integrated Circuit Design Synopsys Tools Tutorial By Zhaori Bi Minghua Li Fall 2014 Table of Contents
More informationTraining Course of Design Compiler
Training Course of Design Compiler T. W. Tseng, ARES Lab 2008 Summer Training Course of Design Compiler REF: CIC Training Manual Logic Synthesis with Design Compiler, July, 2006 TSMC 0.18um Process 1.8-Volt
More informationModeling Registers and Counters
Lab Workbook Introduction When several flip-flops are grouped together, with a common clock, to hold related information the resulting circuit is called a register. Just like flip-flops, registers may
More informationChapter 13: Verification
Chapter 13: Verification Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010,
More informationHow To Design A Chip Layout
Spezielle Anwendungen des VLSI Entwurfs Applied VLSI design (IEF170) Course and contest Intermediate meeting 3 Prof. Dirk Timmermann, Claas Cornelius, Hagen Sämrow, Andreas Tockhorn, Philipp Gorski, Martin
More information2003 IC/CAD Contest Problem 5: Clock Tree Optimization for Useful Skew
2003 IC/CAD Contest Problem 5: Clock Tree Optimization for Useful Skew Source: Global UniChip Corp. February 11, 2003, revised on March 21, 2003 & April 22, 2003 1. Introduction There are two approaches
More informationChapter 7: Advanced Modeling Techniques
Chapter 7: Advanced Modeling Techniques Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL
More informationModeling Latches and Flip-flops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationAsynchronous & Synchronous Reset Design Techniques - Part Deux
Clifford E. Cummings Don Mills Steve Golson Sunburst Design, Inc. LCDM Engineering Trilobyte Systems cliffc@sunburst-design.com mills@lcdm-eng.com sgolson@trilobyte.com ABSTRACT This paper will investigate
More informationModeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationIMPLEMENTATION OF BACKEND SYNTHESIS AND STATIC TIMING ANALYSIS OF PROCESSOR LOCAL BUS(PLB) PERFORMANCE MONITOR
International Journal of Engineering & Science Research IMPLEMENTATION OF BACKEND SYNTHESIS AND STATIC TIMING ANALYSIS OF PROCESSOR LOCAL BUS(PLB) PERFORMANCE MONITOR ABSTRACT Pathik Gandhi* 1, Milan Dalwadi
More informationQuartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit - FSM A Sequential circuit contains: Storage
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationAsynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton Dept. of Electrical and Computer Engineering University of British Columbia bradq@ece.ubc.ca
More informationECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
More informationVHDL Test Bench Tutorial
University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory VHDL Test Bench Tutorial Purpose The goal of this tutorial is to demonstrate how to automate
More informationDigital Design Verification
Digital Design Verification Course Instructor: Debdeep Mukhopadhyay Dept of Computer Sc. and Engg. Indian Institute of Technology Madras, Even Semester Course No: CS 676 1 Verification??? What is meant
More informationLatches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationLatch Timing Parameters. Flip-flop Timing Parameters. Typical Clock System. Clocking Overhead
Clock - key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationModelSim-Altera Software Simulation User Guide
ModelSim-Altera Software Simulation User Guide ModelSim-Altera Software Simulation User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01102-2.0 Document last updated for Altera Complete
More informationTimeQuest Timing Analyzer Quick Start Tutorial
TimeQuest Timing Analyzer Quick Start Tutorial 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: 9.1 Document Version: 1.1 Document Date: December 2009 UG-TMQSTANZR-1.1 Copyright
More informationIntroduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems
Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH
More informationLab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)
Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement
More informationQuartus II Introduction for VHDL Users
Quartus II Introduction for VHDL Users This tutorial presents an introduction to the Quartus II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by
More informationA Verilog HDL Test Bench Primer Application Note
A Verilog HDL Test Bench Primer Application Note Table of Contents Introduction...1 Overview...1 The Device Under Test (D.U.T.)...1 The Test Bench...1 Instantiations...2 Figure 1- DUT Instantiation...2
More informationDigital IC Design Flow
Collège Militaire Royal du Canada (Cadence University Alliance Program Member) Department of Electrical and Computer Engineering Départment de Génie Electrique et Informatique RMC Microelectronics Lab
More informationGate-Level Simulation Methodology
Improving Gate-Level Simulation Performance Author: Gagandeep Singh, Cadence Design Systems, Inc. The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is
More informationLab 1: Introduction to Xilinx ISE Tutorial
Lab 1: Introduction to Xilinx ISE Tutorial This tutorial will introduce the reader to the Xilinx ISE software. Stepby-step instructions will be given to guide the reader through generating a project, creating
More informationDigital Circuit Design Using Xilinx ISE Tools
Digital Circuit Design Using Xilinx ISE Tools Contents 1. Introduction... 1 2. Programmable Logic Device: FPGA... 2 3. Creating a New Project... 2 4. Synthesis and Implementation of the Design... 11 5.
More informationImplementation Details
LEON3-FT Processor System Scan-I/F FT FT Add-on Add-on 2 2 kbyte kbyte I- I- Cache Cache Scan Scan Test Test UART UART 0 0 UART UART 1 1 Serial 0 Serial 1 EJTAG LEON_3FT LEON_3FT Core Core 8 Reg. Windows
More informationLecture 7: Clocking of VLSI Systems
Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 Two-Phase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10 - Clocking Note: The analysis
More informationTiming Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
More informationLecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing
More informationLecture 11: Sequential Circuit Design
Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current
More informationClocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1
ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationDesign Methodology for Engineering Change Orders (ECOs) in a Flat Physical Standard Cells Based Design Environment
Diploma Thesis Design Methodology for Engineering Change Orders (ECOs) in a Flat Physical Standard Cells Based Design Environment submitted by Anton Klotz Standard-Cells Based Design Flow (1) Picture of
More informationLecture 10: Multiple Clock Domains
Bluespec SystemVerilog Training Lecture 10: Multiple Clock Domains Copyright Bluespec, Inc., 2005-2008 Lecture 10: Multiple Clock Domains The Clock type, and functions Modules with different clocks Clock
More informationA HARDWARE IMPLEMENTATION OF THE ADVANCED ENCRYPTION STANDARD (AES) ALGORITHM USING SYSTEMVERILOG
A HARDWARE IMPLEMENTATION OF THE ADVANCED ENCRYPTION STANDARD (AES) ALGORITHM USING SYSTEMVERILOG Bahram Hakhamaneshi B.S., Islamic Azad University, Iran, 2004 PROJECT Submitted in partial satisfaction
More informationRTL Low Power Techniques for System-On-Chip Designs
RTL Low Power Techniques for System-On-Chip Designs Mike Gladden Motorola, Inc. Austin, TX rwdb80@email.sps.mot.com Indraneel Das Synopsys, Inc. Austin, TX ineel@synopsys.com ABSTRACT Low power design
More informationECE 451 Verilog Exercises. Sept 14, 2007. James Barnes (James.Barnes@colostate.edu)
ECE 451 Verilog Exercises Sept 14, 2007 James Barnes (James.Barnes@colostate.edu) Organization These slides give a series of self-paced exercises. Read the specification of each exercise and write your
More informationCSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic
More informationRegisters & Counters
Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing
More informationA Utility for Leakage Power Recovery within PrimeTime 1 SI
within PrimeTime 1 SI Bruce Zahn LSI Corporation Bruce.Zahn@lsi.com ABSTRACT This paper describes a utility which is run within the PrimeTime SI signoff environment that recovers leakage power and achieves
More informationSequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
More informationESP-CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation
Datasheet -CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation Overview -CV is an equivalence checker for full custom designs. It enables efficient comparison of a reference design
More informationIL2225 Physical Design
IL2225 Physical Design Nasim Farahini farahini@kth.se Outline Physical Implementation Styles ASIC physical design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification
More informationDATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
More informationPCIe Core Output Products Generation (Generate Example Design)
Xilinx Answer 53786 7-Series Integrated Block for PCI Express in Vivado Important Note: This downloadable PDF of an Answer Record is provided to enhance its usability and readability. It is important to
More informationThe enable pin needs to be high for data to be fed to the outputs Q and Q bar.
of 7 -Type flip-flop (Toggle switch) The -type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure shows how the flip-flop (latch) can be made using -input logic circuits
More informationPCB Project (*.PrjPcb)
Project Essentials Summary The basis of every design captured in Altium Designer is the project. This application note outlines the different kinds of projects, techniques for working on projects and how
More informationSequential Circuits. Combinational Circuits Outputs depend on the current inputs
Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating
More informationCLOCK DOMAIN CROSSING CLOSING THE LOOP ON CLOCK DOMAIN FUNCTIONAL IMPLEMENTATION PROBLEMS
TECHNICAL PAPER CLOCK DOMAIN CROSSING CLOSING THE LOOP ON CLOCK DOMAIN FUNCTIONAL IMPLEMENTATION PROBLEMS TABLE OF CONTENTS 1 Overview...........................................................................1
More informationMeasuring Metastability
Measuring Metastability Sandeep Mandarapu Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Illinois, USA, 62025 ECE595: Masters
More informationDM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary General Description This device contains two independent negative-edge-triggered
More informationWhat is a System on a Chip?
What is a System on a Chip? Integration of a complete system, that until recently consisted of multiple ICs, onto a single IC. CPU PCI DSP SRAM ROM MPEG SoC DRAM System Chips Why? Characteristics: Complex
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationVHDL GUIDELINES FOR SYNTHESIS
VHDL GUIDELINES FOR SYNTHESIS Claudio Talarico For internal use only 1/19 BASICS VHDL VHDL (Very high speed integrated circuit Hardware Description Language) is a hardware description language that allows
More informationChapter 2 Clocks and Resets
Chapter 2 Clocks and Resets 2.1 Introduction The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationLAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flip-flop 2. Use of actual flip-flops to help you understand sequential
More informationLecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay
More informationECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
More information8254 PROGRAMMABLE INTERVAL TIMER
PROGRAMMABLE INTERVAL TIMER Y Y Y Compatible with All Intel and Most Other Microprocessors Handles Inputs from DC to 10 MHz 8 MHz 8254 10 MHz 8254-2 Status Read-Back Command Y Y Y Y Y Six Programmable
More informationEngineering Change Order (ECO) Support in Programmable Logic Design
White Paper Engineering Change Order (ECO) Support in Programmable Logic Design A major benefit of programmable logic is that it accommodates changes to the system specification late in the design cycle.
More informationChapter 5 :: Memory and Logic Arrays
Chapter 5 :: Memory and Logic Arrays Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 5- ROM Storage Copyright 2007 Elsevier 5- ROM Logic Data
More informationTIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING
TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation
More informationECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)
ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment
More informationLife Cycle of a Memory Request. Ring Example: 2 requests for lock 17
Life Cycle of a Memory Request (1) Use AQR or AQW to place address in AQ (2) If A[31]==0, check for hit in DCache Ring (3) Read Hit: place cache word in RQ; Write Hit: replace cache word with WQ RDDest/RDreturn
More informationQuartus Prime Standard Edition Handbook Volume 3: Verification
Quartus Prime Standard Edition Handbook Volume 3: Verification Subscribe QPS5V3 101 Innovation Drive San Jose, CA 95134 www.altera.com Simulating Altera Designs 1 QPS5V3 Subscribe This document describes
More informationContents. Overview... 5-1 Memory Compilers Selection Guide... 5-2
Memory Compilers 5 Contents Overview... 5-1 Memory Compilers Selection Guide... 5-2 CROM Gen... 5-3 DROM Gen... 5-9 SPSRM Gen... 5-15 SPSRM Gen... 5-22 SPRM Gen... 5-31 DPSRM Gen... 5-38 DPSRM Gen... 5-47
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit A Sequential circuit contains: Storage elements:
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
More informationRAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationDM74LS169A Synchronous 4-Bit Up/Down Binary Counter
Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation
More informationRoute Power 10 Connect Powerpin 10.1 Route Special Route 10.2 Net(s): VSS VDD
SOCE Lab (2/2): Clock Tree Synthesis and Routing Lab materials are available at ~cvsd/cur/soce/powerplan.tar.gz Please untar the file in the folder SOCE_Lab before lab 1 Open SOC Encounter 1.1 % source
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationSequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationAlpha CPU and Clock Design Evolution
Alpha CPU and Clock Design Evolution This lecture uses two papers that discuss the evolution of the Alpha CPU and clocking strategy over three CPU generations Gronowski, Paul E., et.al., High Performance
More information路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
More informationCadence Verilog Tutorial Windows Vista with Cygwin X Emulation
Cadence Verilog Tutorial Windows Vista with Cygwin X Emulation This tutorial will serve as an introduction to the use of the Cadence Verilog simulation environment and as a design tool. The Cadence design
More informationE158 Intro to CMOS VLSI Design. Alarm Clock
E158 Intro to CMOS VLSI Design Alarm Clock Sarah Yi & Samuel (Tae) Lee 4/19/2010 Introduction The Alarm Clock chip includes the basic functions of an alarm clock such as a running clock time and alarm
More informationFINITE STATE MACHINE: PRINCIPLE AND PRACTICE
CHAPTER 10 FINITE STATE MACHINE: PRINCIPLE AND PRACTICE A finite state machine (FSM) is a sequential circuit with random next-state logic. Unlike the regular sequential circuit discussed in Chapters 8
More informationSystem on Chip Design. Michael Nydegger
Short Questions, 26. February 2015 What is meant by the term n-well process? What does this mean for the n-type MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What
More informationDownload the Design Files
Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices March 2006, ver. 1.0 Application Note 409 Introduction The altlvds megafunction allows you to instantiate an
More informationThe 104 Duke_ACC Machine
The 104 Duke_ACC Machine The goal of the next two lessons is to design and simulate a simple accumulator-based processor. The specifications for this processor and some of the QuartusII design components
More information6-BIT UNIVERSAL UP/DOWN COUNTER
6-BIT UNIVERSAL UP/DOWN COUNTER FEATURES DESCRIPTION 550MHz count frequency Extended 100E VEE range of 4.2V to 5.5V Look-ahead-carry input and output Fully synchronous up and down counting Asynchronous
More informationQuartus II Introduction Using VHDL Design
Quartus II Introduction Using VHDL Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented
More informationCoding Guidelines for Datapath Synthesis
Coding Guidelines for Datapath Synthesis Reto Zimmermann Synopsys July 2005 Abstract This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths: Guidelines that help achieve
More informationReconfigurable ECO Cells for Timing Closure and IR Drop Minimization. TingTing Hwang Tsing Hua University, Hsin-Chu
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization TingTing Hwang Tsing Hua University, Hsin-Chu 1 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design
More informationPhysics 226 FPGA Lab #1 SP Wakely. Terasic DE0 Board. Getting Started
Physics 226 FPGA Lab #1 SP Wakely I Terasic DE0 Board The DE0 Development and Education board is designed in a compact size with all the essential tools for novice users to gain knowledge in areas of digital
More informationFF-Bond: Multi-bit Flip-flop Bonding at Placement CHANG-CHENG TSAI YIYU SHI GUOJIE LUO IRIS HUI-RU JIANG. IRIS Lab NCTU MST PKU
FF-Bond: Multi-bit Flip-flop Bonding at Placement CHANG-CHENG TSAI YIYU SHI GUOJIE LUO IRIS HUI-RU JIANG IRIS Lab NCTU MST PKU ISPD-13 Outline 2 Introduction Preliminaries Problem formulation Algorithm
More informationDM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation
More informationQuartus II Handbook Volume 3: Verification
Quartus II Handbook Volume 3: Verification Subscribe QII5V3 2015.05.04 101 Innovation Drive San Jose, CA 95134 www.altera.com Simulating Altera Designs 1 2015.05.04 QII5V3 Subscribe This document describes
More informationQuartus II Handbook Volume 2: Design Implementation and Optimization
Quartus II Handbook Volume 2: Design Implementation and Optimization Subscribe QII5V2 2015.05.04 101 Innovation Drive San Jose, CA 95134 www.altera.com Constraining Designs 1 2014.06.30 QII5V2 Subscribe
More information