ECEN 248 Introduction to Digital Systems Design (Spring 2008) (Sections: 501, 502, 503, 507) Prof. Xi Zhang

Transcription

1 ECEN 248 Introducti to Digital Systems Design (Spring 28) (Sectis: 5, 52, 53, 57) Pro. Xi Zhang ECE Dept, TAMU, 333N WERC

2 Chapter 3 Implementati Technology Voltage V DD Logic value V,min Undeined V,max Logic value V SS (Gnd) Figure 3.. Logic values as voltage levels. ECEN 248, Spring 28

3 3. Transistor Switches Most popular type o transistor: Metal Oxide Semicductor Field-Eect Transistor (MOSFET) Two dierent types o MOSFETs: ) N-channel => NMOS transistors 2) P-channel => PMOS transistors Fig. 3.2b is the symbol o NMOS transistor which has 4 electric terminals: ) source; 2) drain; 3) gate; 4) substrate (GND or Body) Fig. 3.2c is the simpliied symbol o NMOS transistor which the GND cnecti is omitted where ) VS is source terminal; 2) VG is gate terminal; 3) VD ECEN 248, Spring 28

4 x = "low" x = "high" (a) A simple switch ctrolled by the input x Gate Source Drain Substrate (Body) (b) NMOS transistor V G V S V D (c) Simpliied symbol or an NMOS transistor ECEN 248, Spring 28 Figure 3.2. NMOS transistor as a switch.

5 The PMOS Transistors PMOS transistors have the opposite behavior o NMOS transistors Fig. 3.3a is its logic symbol o PMOS transistor as a logic switch which is open i x= high, close i x= low. Fig. 3.3b is the symbol o PMOS transistor with the substrate terminal always cnected to VDD Fig. 3.3c is the simpliied symbol o PMOS transistor where i VG = high, PMOS transistor is turned ; i VG = low, PMOS transistor is turned as a switch being closed. ECEN 248, Spring 28

6 x = "high" x = "low" (a) A switch with the opposite behavior o Figure 3.2 a Gate Drain Substrate (Body) V DD Source (b) PMOS transistor V G V S V D (c) Simpliied symbol or a PMOS transistor ECEN 248, Spring 28 Figure 3.3. PMOS transistor as a switch.

7 NMOS & PMOS Transistor switch unctis/symbols Summary: V G V S = V V D V D = V V D Closed switch whenv G = V DD Open switch whenv G = V (a) NMOS transistor V S = V DD V DD V DD V G V D V D Open switch whenv G = V DD V D = V DD Closed switch whenv G = V (b) PMOS transistor ECEN 248, Spring 28 Figure 3.4. NMOS and PMOS transistors in logic circuits.

8 3.2 Logic Gates/Circuits Built NMOS and PMOS Transistors First, we mainly ocus how to implement logic gates/circuits by using NMOS transistors called NMOS gates/circuits? Then, we ccentrate how to implement logic gates/circuits by combining NMOS and PMOS transistors called Complementary MOS or CMOS gates/circuits, which are presently most popular technology widely used. ECEN 248, Spring 28

9 5 V + - R V R V V x V x (a) Circuit diagram (b) Simpliied circuit diagram x x (c) Graphical symbols ECEN 248, Spring 28 Figure 3.5. A NOT gate built using NMOS technology.

10 V V x x x 2 V x 2 (a) Circuit (b) Truth table x x x 2 x 2 (c) Graphical symbols ECEN 248, Spring 28 Figure 3.6. NMOS realizati o a NAND gate.

11 V x V x 2 V x x 2 (a) Circuit (b) Truth table x x x 2 x 2 (c) Graphical symbols ECEN 248, Spring 28 Figure 3.7. NMOS realizati o a NOR gate.

12 V DD V A V x x x 2 V x 2 (a) Circuit (b) Truth table x x x 2 x 2 (c) Graphical symbols ECEN 248, Spring 28 Figure 3.8. NMOS realizati o an AND gate.

13 V DD V x x 2 V x V x 2 (a) Circuit (b) Truth table x x x 2 x 2 (c) Graphical symbols ECEN 248, Spring 28 Figure 3.9. NMOS realizati o an OR gate.

14 3.3 Logic Gates/Circuits Built CMOS Transistors The logic gates/circuits by combining NMOS and PMOS transistors called Complementary MOS or CMOS gates/circuits er some practical implementati advantages over NMOS technology as discussed in Secti 3.8. In NMOS circuits, the logic unctis realized by NMOS transistors combined with a pull-up resistor. We call part o the circuit involving NMOS transistors as the pull-down network (PDN). All NMOS based circuits structures, as shown in Fig 3.5~Fig. 3.8 can be characterized by a block diagram as shown in Fig. 3.. The ccept o CMOS circuit is based the replacing the pull-up device/resistor with a pull-up network (PUN that is built using PMOS transistors, such that the unctis realized by the PDN and PUN networks are complementary as indicated in Fig. 3.. The PDN & PUN have equal number o transistors, which are arranged so that the two networks are duals o e another. Whenever the PDN has NMOS transistors cnected in series, the PUN has PMOS transistors cnected in parallel, and vice versa. ECEN 248, Spring 28

15 V V x V x n Pull-down network (PDN) Figure 3.. Structure o an NMOS circuit. ECEN 248, Spring 28

16 Pull-up network (PUN) V V x V x n Pull-down network (PDN) Figure 3.. Structure o a CMOS circuit. ECEN 248, Spring 28

17 3.3 Basic Logic Gates/Circuits Built CMOS Transistors and Their Implementati Cost Parameter Basic CMOS based NOT gates, NAND gates, NOR gates, and ANG gates with or 2 inputs How to implement logic gates/circuits with more than 2 inputs by using CMOS transistors? The number o transistors required to build up the gate/circuit with speciied unctis is the key parameter or implementati expense using the CMOS based logic gates/circuits. ECEN 248, Spring 28

18 T V x T 2 V x T T 2 (a) Circuit (b) Truth table and transistor states Figure 3.2. CMOS realizati o a NOT gate. ECEN 248, Spring 28

19 T T 2 V V x T 3 x x 2 T T 2 T 3 T 4 V x 2 T 4 (a) Circuit (b) Truth table and transistor states Figure 3.3. CMOS realizati o a NAND gate. ECEN 248, Spring 28

20 V x T V x 2 T 2 V x x 2 T T 2 T 3 T 4 T 3 T 4 (a) Circuit (b) Truth table and transistor states Figure 3.4. CMOS realizati o a NOR gate. ECEN 248, Spring 28

21 V DD V V x V x 2 Figure 3.5. CMOS realizati o an AND gate using a NAND gate and a NOT gate. ECEN 248, Spring 28