ECL: Emitter-Coupled Logic

Transcription

1 Emitter-Coupled ogic EC EC: Emitter-Coupled ogic The key to reducing propagati delay in a bipolar logic family is to prevent a gate s transistors from saturating. Secti BJT.3 shows how Schottky diodes can prevent saturati in TT gates. owever, it is also possible to prevent saturati by using a radically different circuit structure, called current-mode logic (CM) or emitter-coupled logic (EC). Unlike the other logic families in this chapter, EC does not produce a large voltage swing between the OW and IG levels. Instead, it has a small voltage swing, less than a volt, and it internally switches current between two possible paths, depending the output state. The first EC logic family was introduced by General Electric in 96. The ccept was later refined by Motorola and others to produce the still popular K and K EC families. These families are extremely fast, offering propagati delays as short as ns. The newest EC family, ECinPS (literally, EC in picosecds), offers maximum delays under.5 ns (5 ps), including the signal delay getting and off of the IC package. Throughout the evoluti of digital circuit technology, some type of EC has always been the fastest technology for discrete, packaged logic compents. Still, commercial EC families aren t nearly as popular as CMOS and TT, mainly because they csume much more power. In fact, high power csumpti made the design of EC supercomputers, such as the Cray- and Cray-2, as much of a challenge in cooling technology as in digital design. Also, EC has a poor speed-power product, does not provide a high level of integrati, has fast edge rates requiring design for transmissi-line effects in most applicatis, and is not directly compatible with TT and CMOS. Nevertheless, EC still finds its place as a logic and interface technology in very high-speed communicatis gear, including fiber-optic transceiver interfaces for gigabit Ethernet and Asynchrous Transfer Mode (ATM) networks. current-mode logic (CM) emitter-coupled logic (EC) EC. Basic EC Circuit The basic idea of current-mode logic is illustrated by the inverter/buffer circuit in Figure EC- the next page. This circuit has both an inverting output (OUT) and a ninverting output (). Two transistors are cnected as a differential amplifier with a comm emitter resistor. The supply voltages for this example are V CC = 5., V BB = 4., and V EE = V, and the input OW and IG levels are defined to be 3.6 and 4.4 V. This circuit actually produces output OW and IG levels that are.6 V higher (4.2 and 5. V), but this is corrected in real EC circuits. differential amplifier Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.

2 Emitter-Coupled ogic EC 2 V CC = 5. V IN R 3 Ω V IN 4.4 V (IG) R2 33 Ω Q Q2 V E 3.8 V V OUT 4.2 V (OW) V 5. V (IG) OUT V BB = 4. V R3.3 kω V EE =. V Figure EC- Basic EC inverter/ buffer circuit with input IG. When V IN is IG, as shown in the figure, transistor Q is, but not saturated, and transistor Q2 is. This is true because of a careful choice of resistor values and voltage levels. Thus, V is pulled to 5. V (IG) through R2, and it can be shown that the voltage drop across R is about.8 V, so that V OUT is about 4.2 V (OW). V CC = 5. V IN V IN 3.6 V (OW) R 3 Ω R2 33 Ω Q Q2 V E 3.4 V V OUT 5. V (IG) V 4.2 V (OW) OUT V BB = 4. V Figure EC-2 Basic EC inverter/ buffer circuit with input OW. R3.3 kω V EE =. V Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.

3 Emitter-Coupled ogic EC 3 When V IN is OW, as shown in Figure EC-2, transistor Q2 is, but not saturated, and transistor Q is. Thus, V OUT is pulled to 5. V through R, and it can be shown that V is about 4.2 V. The outputs of this inverter are called differential outputs because they are always complementary, and it is possible to determine the output state by looking at the difference between the output voltages (V OUT V ) rather than their absolute values. That is, the output is if (V OUT V ) >, and it is if (V OUT V ) <. It is possible to build input circuits with two wires per logical input that define the logical signal value in this way; these are called differential inputs. Differential signals are used in most EC interfacing and clock distributi applicatis because of their low skew and high noise immunity. They are low skew because the timing of a -to- or -to- transiti does not depend critically voltage thresholds, which may change with temperature or between devices. Instead, the timing depends ly when the voltages cross over relative to each other. Similarly, the relative definiti of and provides outstanding noise immunity, since noise created by variatis in the power supply or coupled from external sources tends to be a comm-mode signal that affect both differential signals similarly, leaving the difference value unchanged. It is also possible, of course, to determine the logic value by sensing the absolute voltage level of e input signal, called a single-ended input. Singleended signals are used in most EC logic applicatis to avoid the obvious expense of doubling the number of signal lines. The basic EC inverter in Figure EC-2 has a single-ended input. It always has both outputs available internally; the circuit is actually either an inverter or a ninverting buffer, depending whether we use OUT or. To perform logic with the basic circuit of Figure EC-2, we simply place additial transistors in parallel with Q, similar to the approach in a TT NOR gate. For example, Figure EC-3 the next page shows a 2-input EC OR/ NOR gate. If any input is IG, the correspding input transistor is active, and V OUT is OW (NOR output). At the same time, Q3 is, and V is IG (OR output). Recall that the input levels for the inverter/buffer are defined to be 3.6 and 4.4 V, while the output levels that it produces are 4.2 and 5. V. This is obviously a problem. We could put a diode in series with each output to lower it by.6 V to match the input levels, but that still leaves another problem the outputs have poor fanout. A IG output must supply base current to the inputs that it drives, and this current creates an additial voltage drop across R or R2, reducing the output voltage (and we d t have much margin to work with). These problems are solved in commercial EC families, such as the K family described next. differential outputs differential inputs comm-mode signal single-ended input Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.

4 Emitter-Coupled ogic EC 4 (a) V CC = 5. V V R 3 Ω R2 33 Ω V OUT V OUT (c) OUT V Q Q2 Q3 V BB = 4. V V E R3.3 kω V EE =. V (b) (d) V V Q Q2 Q3 V E V OUT V OUT OUT Figure EC-3 EC 2-input OR/NOR gate: (a) circuit diagram; (b) functi table; (c) logic symbol; (d) truth table. EC.2 EC K/ Families The packaged compents in today s most popular EC family have 5-digit part numbers of the form xxx (e.g., 2, 8, 29), so the family is generically called EC K. This family has several improvements over the basic EC circuit described previously: EC K family An emitter-follower output stage shifts the output levels to match the input levels and provides very high current-driving capability, up to 5 ma per output. It is also respsible for the family s name, emitter-coupled logic. An internal bias network provides V BB without the need for a separate, external power supply. Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.

5 Emitter-Coupled ogic EC 5 ABNORMA V Imax.8 IG.8 V Omax V Imin.5 V Imax.475 ABNORMA.98 V Omin igh-state DC noise margin ow-state DC noise margin V Imin.85 OW ABNORMA.63 V Omax.85 V Omin Figure EC-4 EC K logic levels. The family is designed to operate with V CC = (ground) and V EE = 5.2 V. In most applicatis, ground signals are more noise-free than the powersupply signals. In EC, the logic signals are referenced to the algebraically higher power-supply voltage rail, so the family s designers decided to make that V (the clean ground) and use a negative voltage for V EE. The power-supply noise that does appear V EE is a comm-mode signal that is rejected by the input structure s differential amplifier. Parts with a prefix (the EC family) are fully voltage compensated, so they will work properly with power-supply voltages other than V EE = 5.2 V, as we ll discuss in Secti EC.4. EC family ogic OW and IG levels are defined in the EC K family as shown in Figure EC-4. Note that even though the power supply is negative, EC still follows cventi and assigns the names OW and IG to the algebraically lower and higher voltages, respectively. DC noise margins in EC K are much less than in CMOS and TT, ly.55 V in the OW state and.25 V in the IG state. owever, EC gates do not need as much noise margin as these families. Unlike CMOS and TT, an EC gate generates very little power-supply and ground noise when it changes state; its current requirement remains cstant as it merely steers current from e path to another. Also, EC s emitter-follower outputs have very low impedance in either state, and it is difficult to couple noise from an external source into a signal line driven by such a low-impedance output. Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.

6 Emitter-Coupled ogic EC 6 multiple inputs differential amplifier V CC2 = V bias network complementary emitter-follower outputs V CC = V (a) V R3 22 Ω R4 245 Ω V C2 V C3 R7 97 Ω Q5 V OUT OUT (NOR) V Q Q2 Q3 Q4 V BB =.29 V Q6 V (OR) V E R 5 kω R2 5 kω R5 779 Ω R6 6. kω R kω R R 2 V EE = 5.2 V (b) V V Q Q2 Q3 V E V C2 V C3 V OUT V OUT (c) OUT (d) OUT Figure EC-5 Two-input K EC OR/NOR gate: (a) circuit diagram; (b) functi table; (c) truth table; (d) logic symbol. Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.

7 Emitter-Coupled ogic EC 7 Figure EC-5(a) is the circuit for an EC OR/NOR gate, e secti of a quad OR/NOR gate with part number 2. A pull-down resistor each input ensures that if the input is left uncnected, it is treated as OW. The bias network has compent values selected to generate V BB =.29 V for proper operati of the differential amplifier. Each output transistor, using the emitterfollower cfigurati, maintains its emitter voltage at e diode-drop below its base voltage, thereby achieving the required output-level shift. Figure EC-5(b) summarizes the electrical operati of the gate. The emitter-follower outputs used in EC K require external pull-down resistors, as shown in the figure. The K family is designed to use external rather than internal pull-down resistors for good reas. The rise and fall times of EC output transitis are so fast (typically 2 ns) that any cnecti lger than a few inches must be treated as a transmissi line and must be terminated as discussed in Secti Zo. Rather than waste power with an internal pull-down resistor, EC K allows the designer to select an external resistor that satisfies both pull-down and transmissi-line terminati requirements. The simplest terminati, sufficient for short cnectis, is to cnect a resistor in the range of 27 Ω to 2 kω from each output to V EE. A typical EC K gate has a propagati delay of 2 ns, comparable to 74AS TT. With its outputs left uncnected, a K gate csumes about 26 mw of power, also comparable to a 74AS TT gate, which csumes about 2 mw. owever, the terminati required by EC K also csumes power, from to 5 mw per output depending the type of terminati circuit. A 74AS TT output may or may not require a power-csuming terminati circuit, depending the physical characteristics of the applicati. EC.3 EC K Family Members of the EC K family have 6-digit part numbers of the form xxx (e.g.,, 7, 7), but in general their functis are different from those of K parts with similar numbers. The K family has the following major differences from the K family: EC K family Reduced power-supply voltage, V EE = 4.5 V. Different logic levels, as a csequence of the different supply voltage. Shorter propagati delays, typically.75 ns. Shorter transiti times, typically.7 ns. igher power csumpti, typically 4 mw per gate. Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.

8 Emitter-Coupled ogic EC 8 EC.4 Positive EC (PEC) We described the advantage of noise immunity provided by EC s negative power supply (V EE = 5.2 V or 4.5 V), but there s also a big disadvantage today s most popular CMOS and TT logic families, ASICs, and microprocessors all use a positive power-supply voltage, typically +5. V but trending to +3.3 V. Systems incorporating both EC and CMOS/TT devices therefore require two power supplies. In additi, interfacing between standard, negative EC K or K logic levels and positive CMOS/TT levels requires special level-translati compents that cnect to both supplies. Positive EC (PEC, prounced peckle ) uses a standard +5.-V power supply. Note that there s nothing in the EC K circuit design of Figure EC-5 that requires V CC to be grounded and V EE to be cnected to a 5.2-V supply. The circuit will functi exactly the same with V EE cnected to ground, and V CC to a +5.2-V supply. Thus, PEC compents are nothing more than standard EC compents with V EE cnected to ground and V CC to a +5.-V supply. The voltage between V EE and V CC is a little less than with standard K EC and more than with standard K EC, but the -series and K parts are voltage compensated, designed to still work well with the supply voltage being a little high or low. ike EC logic levels, PEC levels are referenced to V CC, so the PEC IG level is about V CC.9 V, and OW is about V CC.7 V, or about 4. V and 3.3 V with a nominal 5-V V CC. Since these levels are referenced to V CC, they move up and down with any variatis in V CC. Thus, PEC designs require particularly close attenti to power-distributi issues, to prevent noise V CC from corrupting the logic levels transmitted and received by PEC devices. Recall that CM/EC devices produce differential outputs and can have differential inputs. A differential input is relatively insensitive to the absolute voltage levels of an input-signal pair, and sensitive ly to their difference. Therefore, differential signals can be used quite effectively in PEC applicatis to ease the noise ccerns raised in the preceding paragraph. It is also quite comm to provide differential PEC-compatible inputs and outputs CMOS devices, allowing a direct interface between the CMOS device and a device such as a fiber-optic transceiver that expects EC or PEC levels. In fact, as CMOS circuits have migrated to 3.3-V power supplies, it has even been possible to build PEC-like differential inputs and outputs that are simply referenced to the 3.3-V supply instead of a 5-V supply. positive EC (PEC) Supplementary material to accompany Digital Design Principles and Practices, Fourth Editi, by John F. Wakerly. ISBN Pears Educati, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No porti of this material may be reproduced, in any form or by any means, without permissi in writing by the publisher.