Introduction to PSpice

Transcription

1 IL2218 Analog electronics, advanced course Document version /Bengt M. Introduction to PSpice This introduction is valid for OrCad PSpice ver 9.2 lite edition. The lite edition or student edition of the software is limited to designs with max 64 nodes and max 10 transistors. Installation of OrCad PSpice ver 9.2 lite edition Follow the installation guideline, choose Capture and PSpice, Layout is optional, this software could also be used to draw the layout of printed circuit bords. Additional information how to handle the software could be found in online manuals or in the Learning Capture lessons in Capture help menu. Start a new design project Start the schematic drawing program Capture. Select File / New Project be sure to choose Analog or Mixed A/D. Browse to the location where you want to save your project and give the project a name 1(16)

2 A schematic capture window should open now. To the left is the project manager window. If the schematic window do not open, double-click on PAGE1 in the project manager window. Start to make a schematic drawing In the schematic window choose Place / Part. The first time you run the program you have to add PSpice libraries. Select Add Library and select all libraries in the PSpice library folder. Be sure to use the symbols in.\orcadlite\capture\library\pspice. Other symbol libraries might have symbols not intended for PSpice simulation. (Those symbols are used for layout and design of printed circuit boards.) 2(16)

3 In this example we will be drawing and simulating this design Use these commands to draw the schematic Place / Part MbreakN NMOS transistor, library BREAKOUT MbreakP PMOS transistor Place / Ground 0 Library Source, you might have to add this library from PSpice folder to find the ground symbol with the name 0, in SPICE there has to be one node with the name 0 as an electrical reference. Place / Part VDC DC voltage source, library Source IDC DC current source Place / Wire Place / Net Alias connect components with wires add name to nets in your design and it will be easier to find signals or connecting nets without actually drawing wires (VDD and VSS). Nets with the same name are connected Start drawing by placing MbreakN Double-click on the symbol to start the Property Editor. Chose Filter by: Orcad PSpice, select the row, right-click and choose Pivot if you want a vertical column. Give value 0.5um and 50um to length (L) and width (W) of the transistor. Mark W and press Display... select name and value, to make it visible in schematic. Do the same with L. ( 0.5u means 0.5 μm ) 3(16)

4 Suppose we want to examine the current to voltage characteristics of this transistor. We connect DC voltages to gate-source and drain-source, here they are renamed to VGS and VDS. Also name the nets G and D (guess why!) to make it easier to reference to them later. To be able to simulate this: change MbreakN to nmos (property Implementation). nmos is the name we give the MOS model. Setup simulation: PSpice / New Simulation Profile Next we need a SPICE model for the transistor and to connect the model to the actual transistor. MOS_models should be in a plain text file and look something like this * PSpice Model Razavi Table 2.1 *$.model nmos NMOS + LEVEL=1 VTO=0.7 GAMMA=0.45 PHI=0.9 + NSUB=9E+14 LD=0.08E-6 UO=350 LAMBDA=0.1 + TOX=9E-9 PB=0.9 CJ=0.56E-3 CJSW=0.35E-11 + MJ=0.45 MJSW=0.2 CGDO=0.3E-9 JS=1.0E-8 *$.model pmos PMOS + LEVEL=1 VTO=-0.8 GAMMA=0.4 PHI=0.8 + NSUB=5E+14 LD=0.09E-6 UO=100 LAMBDA=0.2 + TOX=9E-9 PB=0.9 CJ=0.94E-3 CJSW=0.32E-11 + MJ=0.5 MJSW=0.3 CGDO=0.3E-9 JS=0.5E-8 *$ Name this model file Table_2_1.lib (or any other name you like) and copy it to the folder where your design is located (or any other folder you prefer). This model is from Table 2.1 in Razavi, Design of Analog CMOS Integrated Circuits. 4(16)

5 In the tab Libraries in the simulation profile, browse to the model file and add it to the design. The model file Table_2_1.lib is now added to design. You can check the model of the transistor in your schematic by selecting the transistor, right click and choose Edit PSpice Model It is possible to change model parameters with this editor. 5(16)

6 Simulation Now the design is ready to be simulated! PSpice / Run or the Play button. A new window appears (Probe Window) where simulation results can be plotted. Trace / Add Trace... and select I(D) This plot will be generated in the probe window. 8.0mA 6.0mA 4.0mA 2.0mA 0A 0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V 1.6V ID(M1) V_VGS The plot could be cut and paste to your word processor by using Window / Copy to Clipboard. Use this instead of taking a screen shot to avoid the black background. It saves toner or black ink when you are printing your reports! 6(16)

7 You can make the program plotting this result immediately after simulation if you add a Current marker at the drain pin of the transistor. (PSpice / Markers / Current Into Pin) As a next step, let s make a nested DC sweep. PSpice / New Simulation Profile and name it DC-nested-sweep Give values for Primary sweep: VDS 0V to 3V with 0.01V step (this is one curve) Secondary sweep: VGS 0V to 1.5V with 0.1V step (one curve for each VGS-value) Result in Probe Window: 10mA 8mA 6mA 4mA 2mA 0A 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V ID(M1) V_VDS 7(16)

8 Simulating a simple amplifier Now let s make a simple amplifier with this transistor. From the I D -V GS -plot we select a bias voltage V GS = 1.2 V corresponding to a drain current I D = 2.84 ma. Suppose we want to design an amplifier with supply voltage V DD = 3 V and bias point V GS = 1.2 V, V DS = 1.5 V and I D = 2.84 ma We just need to add an external drain resistance R D = 528 Ω. ( R D VDD VDS = = = 528 Ω) I 2.84m D Before we do this, let s check the Project manager window We have this far created two simulation profiles. We could easily switch between which one to choose as active profile. With the mouse, select, right-click and choose Make Active. We now want to make a new schematic drawing without destroying the old one. Let us manage this in the project window. First, rename the current schematic to a better name describing what kind of schematic it is. Select SCHEMATIC1, right-click and rename it to Transistor The select.\problem_x.dsn, right-click and create a new schematic with the name Amplifier Then in the same way, create a new schematic page. Now the project window looks like this. Transistor is still the root schematic in your design. Make Amplifier the root design (select, right-click...) Usually you are urged to save the design before it could be the root design. Then, from the /Transistor/PAGE1 select the drawing in your schematic and copy and paste it into the Amplifier PAGE1 Now you can use this schematic drawing as a base to create a new one. 8(16)

9 Now, make a drawing of this amplifier (at PAGE1 in schematic Amplifier): Bias point simulation calculates DC currents and voltages in the net Create a new simulation profile with the name Bias-point, mark Output File Options and Calculate small signal gain (TF.) from input net Vin to output voltage V(Out). Sometimes when you create new simulation profiles you could inherit and copy it from an existing profile, but in this case it is easier to create a new one. Run a simulation. This simulation calculates the DC voltage and currents in the net. From bias point information a small signal linear model is created and the small signal transfer function is calculated. After the simulation the DC voltages, current or power can be shown in the schematic. This could be toggled ON or OFF with buttons. 9(16)

10 If you take a peek into the output file PSpice / View Output File you can find this information: **** SMALL-SIGNAL CHARACTERISTICS V(OUT)/V_Vin = E+00 INPUT RESISTANCE AT V_Vin = 1.000E+20 OUTPUT RESISTANCE AT V(OUT) = 4.671E+02 and information about DC voltage and currents for the transistor and the small signal parameters in the bias point **** MOSFETS NAME M_M1 MODEL nmos Bias point (quiscent point) ID 2.84E-03 Drain DC current VGS 1.20E+00 Gate to source DC voltage VDS 1.50E+00 Drain to source DC voltage VBS Body to source DC voltage VTH 7.00E-01 Threshold voltage VDSAT 5.00E-01 VDS saturation voltage = VGS VTH= Lin0/Sat1-1.00E+00 if -1.00E+00 ir -1.00E+00 TAU -1.00E+00 Small signal parameters GM 1.14E-02 Transconductance from gate voltage to drain current GDS 2.47E-04 Output conductance GDS, output resistance r o = 1/GDS GMB 2.69E-03 Transconductance from body voltage to drain current CBD CBS CGSOV CGDOV 1.50E-14 CGBOV CGS 4.35E-14 CGD CGB The small signal voltage gain for this amplifier is 2 1 Av = gm( ro // RD) = // = in agreement with simulated V(OUT)/V_Vin = E+00 In output file you also find information about MOS model parameters. A comment on some values that may confuse you: nmos NMOS LEVEL 1 L E-06 W E-06 These values of L and W in output file is default values. In our case these are not guilty. L and W is specified in schematic drawing 10(16)

11 AC analysis small signal linear model calculations In AC analysis a linear small signal model, valid for the transistor in the bias point, is used to calculate the frequency response of the circuit. Different sources are used for different kind of analysis. Change the VDC source to VAC and specify the DC-voltage and small signal voltage for all sources used to generate signals for AC analysis. Set up a new simulation profile. Do not change the old one, maybe you want to switch back to it later. I call this one Frequency sweep. If you mark Include detailed bias point information... you get the information about bias point DC voltages, current and small signal parameters for the transistor in the output file (same as on previous page). Check in the output file that you have the correct bias point NAME MODEL ID VGS VDS VBS M_M1 nmos 2.84E E E+00 This simulation runs from 100 Hz to 100 MHz. Note that you have to write MEG for M (10 6 ). For historical reasons SPICE does not distinguish between upper and lower case letters. Marking Logarithmic makes the calculated frequencies to be distributed at equidistance in a logarithmic scale. 11(16)

12 Run the simulation! If you want to plot the gain in Probe window: Add / Trace and V(Out)/V(In) Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(OUT)/ V(IN) Frequency As expected the gain amplitude is 5.3. The gain goes down slightly at high frequencies. In this case all capacitances are not included in the transistor model so the simulation is not correct at high frequencies. Always be suspicious and check if the output seems to be right! In Probe window it is possible to do different kind of calculations based on simulated results. There are also different functions available in Probe. For more information, refer to the Analyzing waveforms chapter of the PSpice User s Guide, or the PSpice online help. DB() P() decibel calculation phase calculation, 180 degrees at low frequencies in our simple inverting amplifier SEL>> d DB(V(OUT)/ V(IN)) 179.9d 179.8d 179.7d 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz P(V(OUT)/ V(IN)) Frequency 12(16)

13 Capacitances dependent on area of drain and source If the transistor capacitances at the reverse biased PN-junctions from drain and source to the transistor body (substrate) should be present in the simulation model we have to specify the area and perimeter of drain and source. This is done by giving values to the attributes AD and AS drain and source area in m 2 PD and PS drain and source perimeter in m Assume that the geometry of the transistor is as in figure 2.32a in book and E= 1.5 µm. In our simualtion example W= 50 µm. AD = AS = WE = m 2 = m 2 PD = PS = 2 (W+E) = 2 (50+1.5) 10-6 m = 103 µm RD 528 VOFF = 1.2V VAMPL = 1mV FREQ = 1000Hz AC = 1mV Vin In nmos M1 Out L = 0.5u W = 50u AD = 75p AS = 75p PD = 103u PS = 103u 3Vdc VDD DC = 1.2V 0 From output file CBD CBS CGSOV CGDOV CGBOV CGS CGD CGB E E E E-14 Something to think about: Why are some of the capacitances zero? 12.5 SEL>> d DB(V(OUT)/ V(IN)) 160d 120d 100d 10KHz 100KHz 1.0MHz 10MHz P(V(OUT)/ V(IN)) Frequency 100MHz 1.0GHz 10GHz 13(16)

14 Transient analysis calculates voltages and currents as a function of time In transient analysis the voltages and currents are calculated using large signal models of the transistor, i.e. the transistor equations. The analysis calculates voltages and currents in the circuit as a function of time. Now replace the AC voltage source VAC to voltage source VSIN from library source! This specifies a sinusoidal input voltage. VSIN could also be used for AC-analysis (AC=) and DC analysis (DC=). Those attributes is not visible as default, but by now you now how to make it visible. Once again, create a new simulation profile. I have named it Time sweep this time. If maximum step is not specified, it will be the end time divided by 50 (TSTOP/50). The calculation step is dynamically adjusted to get high accuracy in calculation. Maximum step size is the time step used to save data from simulation. Sometimes, if maximum step size is not specified, the plotted curve is not so smooth. To change the maximum step size to a smaller value will save more data and make the plotted curve smoother. 14(16)

15 Input voltage V V V V V 0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms V(IN) Time Output voltage 1.510V 1.505V 1.500V 1.495V 0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms V(OUT) Time Using markers to read the peak-to-peak value of output voltage gives 10.6 mv. Input voltage peak-topeak value is 2 mv. Vout 10.6m Av = = = 5.3 Vin 2m The output voltage is in opposite phase compared to the input voltage. A v = -5.3 If we increase the amplitude of the input voltage to peak value 0.5 V (VAMPL=0.5V) we can see that the output is heavily distorted and clipping of output voltage occurs. 3.0V 2.5V 2.0V 1.5V 1.0V 0.5V 0V 0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms V(OUT) Time 15(16)

16 Types of simulations Transient analysis Bias point DC sweep AC analysis calculates currents and voltages as a function of time. This analysis use large signal models, i.e. transistor transfer equations. calculates DC operating point calculates DC values when one of the DC sources is changing its values. Sweep could be nested, that means that one DC sweep could include sweep of another source. calculates small signals as a function of frequency. This analysis use a linear small signal model. Note that different sources are specified for DC, transient and AC analysis. Sources used for transient analysis like VSIN could be used also for DC and AC analysis if the corresponding attributes is given values. Some hints: SPICE makes no distinction between capital and lower case letters, use MEG for meg, M means milli. Values and prefix should be typed without spaces. For example: 10u not 10 u DC voltages (or current) can be shown in schematic, press button V in Capture schematic window. Voltage level markers (or current) could be used in Capture to show voltage immediately after simulation in output display. Sometimes you could get an error message ERROR -- Node xxx is floating, e.g. if you have two capacitors in series the program cannot solve for the DC voltage at the connection point. You can trick the program to calculate DC voltage if you put a large resistor like 1 G to ground or in parallel to one capacitor. In output display (Probe window): A common problem is that when you change the circuit and resimulate it you want the same trace expression as in last plot after a new simulation. You don t need to type in the same expression, just restore the expression Windows / Display Control... LAST SESSION Restore Copy to Word or other word processor program: In capture, just select the circuit you want to copy and use cut and paste to Word. In output window (Probe windows) Window / Copy to Clipbord and paste the picture in Word. 16(16)