Current Source Biasing

Transcription

1 Current Source Biasing ntegrated circuits have transistors which are manufactured simultaneously with the same device parameters (parameters from chip to chip will vary) As a result, different bias techniques are employed than in discrete designs One common technique is current source biasing, which allows the designer to take advantage of matched devices We will begin by looking at some simple current source circuits A current source is not a naturally occurring device. t can be simulated by a network of transistors and circuit elements.

2 The voltage across E is approximately constant. E is held at a constant value E VEE V = E BE

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7 Problem: For the previous circuits find the bias values C and V CE for each transistor Solution Assume D 1 and D 2 forward biases ( 1 > B2 ) V = V + 2V = 10V + 2( 0. 7V) = 8. 6V B EE F Using KVL around loop A 2V = V + F BE2 E2 2 Since V E2 BE2 V F VF 0. 7V = = 180Ω ma Since C E = = C1 C2 39. ma

8 Check that D 1 and D 2 are forward biased for a worst case minimum βf = 20 B2 C2 = β F 019. ma 1 = V CC V 1 B = 10V ( 8. 6V) 50 kω = 037. ma V = V = 10V ( 39. ma)(1kω) = 61. V C1 CC C1 C V = V V = 8. 6V 0. 7V = 9. 3V E2 B BE2 V = V = 0V V = 0. 7V E1 C2 BE1 V = V V = 61. V ( 0. 7V) = 68. V CE1 C1 E1 V = V V = 0. 7V ( 9. 3V) = 8. 6V CE2 C2 E2

9 Current Mirrors Current mirrors also take advantage of matched transistors but require a minimal number of resistors. They are also well suited for circuits with more than one stage.

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11 Basic BJT Current Mirror

12 A = VCC ( VCE + VEE ) A V V V = 1 CC BE1 EE A = + + A EF B1 B2 F β F is large << << B1 EF B2 EF EF A Problem For the following circuit C3 = 3 ma and V CE = 5.4 V. Find the quiescent (DC bias) power dissipated in each transistor.

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14 = C3 o EF A A = 0V ( VF + VEE ) A A VF VEE = =. V ( V) = 3mA EF 31. kω V = 0. 7V; To achieve V = 54. V, V = 4. 7V E CE C V CC V = 10V 4. 7V = 53. V C C 53. V = = 3mA 18. kω

15 The DC power in each transistor is given by: P = V + V V Q C CE B BE C CE P Q1 = ( 3mA) ( 0. 7V) = 0. 2 mw P Q2 = ( 3mA)[ 0. 7V ( 10V)] 28 mw P Q3 = ( 3mA)(5.4V) = 16 mw

16 MOSFET Current Mirror Advantage: EF = A Gate current is negligible

17 Widlar Current Source The basic current mirror requires that the bias current and reference current be equal The wildar current source sets the mirrored current to a value smaller than EF by using an extra resistor The widlar current source allows you to establish small bias currents (µa) without using large resistor values

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19 EF V V V CC EE BE1 A V = V + BE1 BE2 E2 2 V BE ηv T E = EO e 1 EO e V BE ηv T V BE = ηv T ln E EO Assuming matched BJTs ηv T ln E = ηvt ln + E1 1 EO EO E2 2 = ηv E2 2 T ln E1 E2

20 E1 EF E2 o o VT = η ln 2 EF o Equation difficult to solve in closed form. Use successive iteration or trial and error When you know the desired o then EF can be found directly EF = o o exp 2 ηv T Problem: Using a widlar current source find the values of A and B that will produce o = 100 µa. Given V CC = 10 V, VEE = -10 V, V F = 0.7 V and η = 1.

21 Solution: Select a value of 2 such that o2 ηv T To keep exponent from becoming too large ηv T = 25mV Choose = 100 mv = 1kΩ o 2 2 EF = 100 µ A)(1kΩ ( 100 µ A)exp ( ) = 546. ma. V EF = V V V CC EE F A A = 10V ( 10V) 0. 7V 5.46 ma = 354. kω

22 Wilson Current Source efined Widlar source that can produce O > EF

23 The balance between V BE1 and V BE2 is set by the ratio of 1 to 2 Assuming C E V + = V + BE1 EF 1 BE2 o 2 ηv T ln EF EO1 o + EF 1 = ηvt ln + EO2 o 2 Assuming matched devices o ηvt EF = ln + 2 o EF 1 2

24 Small Signal Modeling of Three Terminal Devices ncremental signals Piecewise linear models ncremental circuit models BJT FET efinements to incremental model Output resistance nput resistance Alternative BJT representation Two - port representations

25 Small Signal Modeling of Three Terminal Devices elated to PWL concept in which the V- characteristics are modeled by a straight line tangent to the curve at a particular operating point With three terminal devices the relationship between the output port and input port must be taken into account. This generally leads to a PWL model with a linearly dependent source. Circuits containing small signal models can be analyzed using linear circuit theory under proper conditions The terms small-signal and incremental will be used interchangeably

26 ncremental Signals Any transient, periodic or AC fluctuation in a voltage or current An incremental signal is small in magnitude compared to the bias voltages or currents in the circuit ncremental signal carries the signal information processed by the circuit

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30 PWL Models of Three Terminal Devices Formation of small signal model begins with PWL model PWL model can be applied to three terminal device if the dependency of the output port is considered

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33 r BE vbe = = i b V, BE B ηv B T Model valid only in constant current region f the circuit in which the BJT is connected produces a signal as well as a bias component to i B then: ic( t) = β ο ib ( t) where i c and i b are inc remental signals and β ο is the incremental current gain

34 Since β F is fairly constant it is possible to assume β ο = β F in many cases The symbols h FE and h fe are sometimes used instead of β F and β ο when using h-parameter analysis

35 ncremental Circuit Model n analyzing the small signal performance of a circuit it is customary to ignore the DC components of the model once the bias conditions have been established. This can be accomplished by the following procedure: 1. Find the DC bias point and determine an appropriate PWL model 2. Set all bias values to zero by setting all DC sources to zero (including those in the PWL model) 3. Solve the desired variables using linear circuit theory 4. Superimpose the signal variables onto the corresponding DC bias voltages and currents to obtain the total voltage and current values

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38 B = V BB V B F = 1V 0. 7V 10 kω = 30 µ A = β = ( 100)( 30 µ A) = 3mA C F B V = V = V = 10V ( 3mA)(1kΩ) = 7V OUT CE CC C C Transistor operates in constant current therefore we can use PWL model developed earlier r be ηvt 1( ) = = 30µ A B 833Ω

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40 i b = B vs + r be v = β i o ο b C v o = βο + r B C be 100( 1kΩ) v = v 9. 2 v 10 kω kω s s s β ο + r B C be is the incremental or small - signal voltage gain V = V + v ( t) = 7V 9. 2 v ( t) OUT CE o s Total = Bias + ncremental Voltage Voltage Signal

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42 Problem: For the following circuit find the incremental components of v c and v e.

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45 Note: v s connection does not represent typical amplifier design. KVL around the input loop for incremental signal v 1 + = i ( ) + i r + ( β + 1) i s b 1 2 b π ο b E 1 2 i b = v 1 s ( ) ( ) + r + ( β + 1) 1 2 π ο E v = ( β + 1) i = e ο b E 1 ο E v ( ) ( ) + r + ( β + 1) ( β + 1) 1 2 π ο E s v = ( β i ) = c ο b C β 1 ο C v s ( ) ( ) + r + ( β + 1) 1 2 π ο E

46 n the limit << ( β + 1) β r 1 2 π ο + 1 β << ( β + 1) ο ο ο E E v e 1 + v 1 2 s v c C E 1 + v 1 2 s

47 ncremental Model of MOSFET

48 g m id [ 2 = = k( V V ] GS T ) = 2k ( V V v v V GS T ), D GS V, GS GS D GS Assume constant current operation V GS D VT = k 1/ 2 g m = 2 k D Similar expression can be derived for JFET

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50 An incremental description for a FET can also be defined for triode (resistive) region t can be shown that the incremental model is as follows

51 r ds = ( V ) 2k V 1 GS T g m = 2k V DS

52 Problem: (A) Find the small signal componont of V OUT for the following circuitd v s = 0.1 Sin ωt, k = 0.2 ma/v 2, V T = -2 V. (B) Find the Thevenin circuit between V OUT and ground..

53 The bias values can be found to be 0. 47mA V = = 0. 47V D GS D E Applying KVL to output loop V = V ( + ) = 10V ( 0. 47mA)(3k) = 8. 6V DS DD D D E Since V DS > (V GS V T ) = 1.53 V the device operates in the constant current region The incremental transconductance g m is given by g = 2k ( V V ) m GS T [ ] = 2( 0. 2 ma / V ) V ( 2 V) 0. 61mA / V 2

54 The signal component of v OUT can be found by substituting the PWL model and setting all DC sources to zero

55 Applying KVL to the output loop v = v i = v ( g v ) gs s d E s m gs E v gs = 1 + vs g m E Note feedback limits the fraction of v that appears as v gs s v = i = g v v OUT d D m gs D OUT gm = 1+ g m D E v s a V vout gm = = v 1+ g s m D E ma / V)(2 k = ( Ω) = (0.61mA / V)(1kΩ) v = a v = ( 0. 76)( 01. sin ωt) = sinωt OUT V s

56 Since v OUT is computed with no load it represents the incremental open circuit Thevenin voltage The incremental r th can be found by setting v s to zero and applying v TEST

57 v = g v can only be satisfied if v = gs m gs E gs 0 i test = v test D r th vtest = = i test D