EECS 240 Topic 7: Current Sources


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1 EECS 240 Analog Integrated Circuits Topic 7: Current Sources Bernhard E. Boser,Ali M. Niknejad and S.Gambini Department of Electrical Engineering and Computer Sciences
2 Bias Current Sources Applications Design objectives Output resistance (& capacitance) Voltage range (V min ) Accuracy Noise Cascoding HighSwing Biasing
3 Resistor Example
4 Current Mirror Bias Noise Cascoding
5 Noise M2 (and I ref!) can add noise Choose small M (power penalty), or Filter at gate of M1 Current source FOMs Output resistance R o Noise resistance R N Active sources boost R o, not R N
6 V min versus Noise Voltage required for large Ro (saturation): V min ~ V* (based on intuition from squarelaw model) Minimizing noise (for given I D ): large R N large V* (and, hence, V min ) At odds with signal swing (to maximize the dynamic range)
7 Bipolar s, GaAs, BJT and R E contribute noise Increasing R E lowers overall noise BJT and MOS exhibit essentially same noise / V min tradeoff Lowest possible noise source is a resistor (and large V min, V DD )
8 Cascoding
9 Output Resistance
10 R out = f(k) How choose k? Issues: Swing versus R o Large k useful only for large V min simultaneously Note: small or no penalty for large k and small V min typically choose k>1
11 R out
12 HighSwing Cascode Biasing Need circuit for generating V bias2 Goal: Set V bias such that V DS1 kv* Important for high R out No penalty for moderate R out Design for insensitivity to Process variations (µ, C ox, V TH, γ, ) Reference current I ref
13 HighSwing Bias 1 M 4 quarter size or less M=1/5 for high R out Note: M k M 5 sets V DS3 = V DS1 : improves matching Sensitive to bodyeffect L currentsource = L cascode Simple
14 HighSwing Bias 2 M5 M10 replace quarter size device All devices same size Less sensitive to bodyeffect L currentsource = L cascode
15 HighSwing Bias 3 M 5 in triode & smaller All other devices same size Sensitive to bodyeffect L currentsource = L cascode
16 Different Device Length
17 HighSwing Bias 4 M 6 in triode Insensitive to body effect Current source and cascode device length may differ Need 3 reference sources (increased power dissipation) Large device ratios Ref: Carlos A. Laber, Chowdhury F. Rahim, Stephen F. Dreyer, Gregory T. Uehara, Peter Kwok, Paul R. Gray; Design considerations for a highperformance 3µm CMOS analog standardcell library, IEEE Journal of SolidState Circuits, vol. 22, pp , April 1987.
18 Intro to gain boosting Remember how cascoding works Vo Vx M2 M1 Ip g m,m2 senses changes Vx and tries to cancel them. Can we increase g m,m2 without degrading ro? Vx=Ip R o,m1 (VoVx)/R o,m2 =g m,m2 (Vx+Ip)
19 Gain Boosting A2 +  Vo M2 Ip Vx M1 g m,m2 senses changes Vx and tries to cancel them. Can we increase g m,m2 without degrading ro? Add amplifier A2 Now gate experiences variations of Vx amplified! Effective increase in g m,m2 Vx=Ip R o,m1 (VoVx)/R o,m2 =g m,m2 (Vx+Ip)
20 Gain Boosting Use feedback to further increase R out No increase of V min (unlike double cascode) Local feedback potential instability Beware of doublets (slow settling) Noise enhancement
21 Gain Boosting Analysis Note: C1 & C2 would not be present in an actual circuit (or smaller). They are added here to separate pole frequencies.
22 Z out Z total = Z boost // Z CL Doublets slow settling Booster bandwidth tradeoff:  push doublet above closedloop bandwidth  ensure stability (nondominant pole at source of M 2 ) Ref: Klaas Bult, Govert J. G. M. Geelen; A fastsettling CMOS Op amp for SC circuits with 90dB DC gain, IEEE Journal of SolidState Circuits, vol. 25, pp , December 1990.
23 Z out Ztotal = Zboost // ZCL Doublets slow settling Booster bandwidth tradeoff:  push doublet above closedloop bandwidth  ensure stability (nondominant pole at source of M 2 ) Ref: Klaas Bult, Govert J. G. M. Geelen; A fastsettling CMOS Op amp for SC circuits with 90dB DC gain, IEEE Journal of SolidState Circuits, vol. 25, pp , December 1990.
24 Noise Analysis
25 Gain Boosting Noise V n,a2 A2 +  Vo M2 Ip Vx Noise from amplifier shows up at Vx (Virtual short circuit) Goes to the output via M1 s ro I o,a2 =V n,a2 /R o,m1 M1 Vx=Ip R o,m1 (VoVx)/R o,m2 =g m,m2 (Vx+Ip)
26 Noise Summary
27 Noise Detail Booster amplifier and cascode contribute noise at high frequency. Actual boosters have more transistors additional noise. Some noise might be filtered out by sampling switch.
28 Cascode Noise Noise from cascode often insignificant. Can contribute substantially at high frequency with lots of (capacitive) degeneration at the source of the cascode transistor (poor layout).
29 If it works, do it again! Since in advanced scaled CMOS g m r o is small, we can use nested gain boosting for higher output impedance. Watch out for polezero doublets!
30 Matching Systematic mismatch ΔV DS source resistance gradients Random mismatch Δ (W/L) ΔV TH
31 Random Mismatch Model: (we need an equation with W/L in it resort to squarelaw) Mismatch: ΔI D, Δ(W/L), ΔV TH Substitute: choose large V GS V TH (V*)
32 Mismatch Example Represent mismatch as random quantities Variances (squares!) add like noise Use large V* (or degeneration) for good current mirror matching
33 Yield = fraction of good dies E.g. need ±2.8% matching σ = 1.4%, k = 2.8 / 1.4 = 2 yield = = 95.4% Typical design goal: ± 3σ ( 6σ ), i.e. k=3 Yield This is only 1 source of variationglobal yield from composition k Yield
34 Device Sizing Examples: m 5 = 1/3, ΔV TH =0V R = 1 m 5 = 1/4, ΔV TH =0V R = 1.55
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