PVD Solutions for Under Bump and TSV Metallization with Higher Productivity for Future Device Generations

Transcription

1 for Under Bump and TSV Metallization with Higher Productivity for Future Device Generations European 3D TSV Summit, Grenoble (France), 22 nd 23 rd January, 2013 Glyn Reynolds, Albert Koller and Robert Mamazza, Jr.

2 Outline 1 Advantages and Disadvantages of PVD 2 Directional PVD 3 HIS Source 4 Hexagon Platform Page 2

3 Outline 1 Advantages and Disadvantages of PVD 2 Directional PVD 3 HIS Source 4 Hexagon Platform Page 3

4 Physical Vapor Deposition (PVD) As IC Manufacturing Has Evolved, PVD Has Endured Sputtered Al alloys Early days: Al evaporator Cu dual damascene structure w/ PVD barrier and Cu seed 2 PVD Al alloy over CVD W plug 1 1 The Laboratory of Physical Sciences, Nanotechnology Group, Univ. of Maryland. 2 F Lanckmans et al., Applied Surface Science 201, pp (2002). Page 4

5 Advantages of Sputtered Films Clean No toxic or hazardous effluent Most metallic and semi-metallic elemental targets available Wide range of alloys available Reactive sputtering of oxides and nitrides Important materials such as Al 2 O 3, TiO 2, ITO,TiN, TaN x, AlN, etc. Dense, pure films Typical contaminants <1% of inert gas CVD and ECD films usually contain impurities Good adhesion Promoted by ion mixing at interface Alloy control V. imp. for Al alloys Maybe for Cu? Well-suited to UBM and RDL deposition in WLP Page 5

6 Disadvantages of Sputter-Deposition Sputter-deposition is line-of-sight Difficult to line or fill high aspect ratio features due to overhang Stress can limit film thickness to 5-10 µm Relatively expensive technique Especially for thicker films Page 6

7 Outline 1 Advantages and Disadvantages of PVD 2 Directional PVD 3 HIS Source 4 Hexagon Platform Page 7

8 Directional PVD The Solution to Line-of-Sight Limitations? Minimize # of atoms arriving at wafer at oblique angles Enhance # of atoms/ ions arriving perpendicular to wafer In practice, this is only possible with ionized techniques Collimation Long throw/ low pressure All these techniques increase cost! High Density Plasma Ionized PVD RF Coil Page 8

9 Outline 1 Advantages and Disadvantages of PVD 2 Directional PVD 3 HIS Source 4 Hexagon Platform Page 9

10 Oerlikon HIS (Highly Ionized Sputtering) Reducing the Cost of Directional PVD Concept based on High Power Pulsed Magnetron Sputtering (HPPMS) Widely used for hard coatings Uses standard planar magnetron High ion fractions Excellent directionality and film quality (esp. HIS texture and density) Ionization occurs in high density plasma region formed adjacent to target Allows close coupling between target and wafer Distances typical of standard PVD apparatus Higher rate than other ionized PVD techniques Lower CoO Higher throughput Lower cost of consumables Lower power consumption Less cooling water required Higher target utilization Longer target life/ increased time between target changes Simple, inexpensive shield design Page 10

11 HIS Ti Barriers for TSVs Ti Ionization Degree /% Ti Ionization Degree n ( Ti (0) ) n ( Ti (1+) ) Peak Discharge Current /A Measurements of Ti ion fraction by 13cm n Ti 0 46% Ti 1+ and Ti 0 Density /arb.u. Ti Coverage in 10:1 AR deep via Field: 815nm Ti 25% depth: 22nm (2.6%) 50% depth: 11nm (1.3%) 75% depth: 14nm (1.7%) 100% depth: 18nm (2.2%) Bottom: 123nm (15.1%) Pictures courtesy of Fraunhofer IZM-ASSID Page 11

12 HIS Ta and TaN x Barriers for TSVs Field: 529nm TaN x / α-ta Mid-via: 35nm (6.6%) TaN x / α-ta bilayer in 8 x 100µm, 12:1 AR deep vias Bottom: 45nm (8.5%) Std. PVD α-ta HIS α-ta Page 12

13 HIS Cu Seed Layers for TSVs 4:1 AR full wafer TSV with connection on backside 4:1 AR Deep via for via last approach Complete filling of 5:1 AR deep vias after ECD Similar process leaves voids in 10:1 AR deep vias Pictures courtesy of Fraunhofer IZM-ASSID Page 13

14 HIS Cu Seed Layer for 10:1 AR TSVs 1 st IP Ti = 6.56 ev 1 st IP Cu = 7.73 ev Process: DRIE 10x100µm SACVD liner 1µm HIS barrier 500nm 9cm target-to-wafer spacing HIS seed 2500nm Cu (rate 14cm target-to-wafer spacing Field: 2500nm Cu 25% depth: 40nm (1.6%) 50% depth: 26nm (1.0%) Complete filling after ECD 75% depth: 20nm (0.8%) 100% depth: 46nm (1.8%) Bottom: 193nm (7.7%) Pictures courtesy of Fraunhofer IZM-ASSID Page 14

15 Summary of Selected HIS Process Results Material and aspect ratio Deposition Rate [nm/s] on 200mm on 300mm Uniformity [%] on 200mm High ion fractions Smooth, dense films High deposition rates Good uniformity Low stress Process Flexibility: ability to fill different aspect ratio features by varying target-to-wafer spacing; deposition rate can be adjusted with source power For 10 x 100µm, 10:1 AR deep vias: ~2% minimum sidewall coverage for Ti, Ta ~1% minimum sidewall coverage for Cu Void-free ECD filling with 2µm thickness on field Specific resistivity Film stress Minimum step on coverage 300mm [µωcm] [MPa] Ti in 10: % 6% > 2% < 70 < 500 compr. α-ta in 10: % 6% > 2% < 26 < 700 compr. Cu in 10: % 8% > 1% < 2.7 < 200 tensile Page 15

16 Outline 1 Advantages and Disadvantages of PVD 2 Directional PVD 3 HIS Source 4 Hexagon Platform Page 16

17 Hexagon Platform Overview Objectives Maximize Throughput Minimize Wafer Transfer Risk Developed for advanced packaging Configuration Indexer Type Handling High Speed Airlock Toroidal Chamber Turbo Pumps in Process Chambers Cryogenic Isolation Traps Full Stainless Process Chambers Process Stations Degas Cool (Optional) Etch PVD/ HIS Degas Etch HIS-Ti HIS-Cu Airlock High Productivity Configuration for TSV Applications Page 17

18 Hexagon Process Capabilities Optimized for WLP, UBM, RDL and backside metallization on 300mm wafers Very small footprint >50wph throughput PVD and ICP etch chambers designed to be compatible with Oerlikon s extensive and proven process portfolio Can use identical PVD chamber configurations for UBM, RDL and HIS/ TSV applications Arctic ICP etch for PI/ PBO wafer processing (-30 to +40 C) Typical within cassette film thickness and uniformity data for Ti Typical within cassette film thickness and uniformity data for Cu Page 18

19 Acknowledgements Juergen Weichart Mohamed Elghazzali Patrick Carazzetti Simon McClatchie Fraunhofer IZM-ASSID Kay Viehweger Page 19

20 Thank you.