Graduate Student Presentations

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1 Graduate Student Presentations Dang, Huong Chip packaging March 27 Call, Nathan Thin film transistors/ liquid crystal displays April 4 Feldman, Ari Optical computing April 11 Guerassio, Ian Self-assembly alternative to lithography April 11 Leenheer, Andrew Next Generation Lithography April 18 Porpora, Daniel Carbon nanotube based microelectronics April 18 Rance, Will 3-d chip architectures April 25 Szymanski, Scott Transition metal thin film interconnects April 25

2 Presentation on Modules III-VI Second presentation and written report -Each team member must present at some time during term -Tuesday, March 14 in class, 10 minute presentation 2 minutes discussion -Evaluation rubric on website -Written report due at class time - No more than 5 pages -A1 and B1 present on oxide procedures (modules 3 and 5) -A2 and B2 present on doping procedures (modules 4 and 6) -Order B1, B2, A1, A2 (B1 come early to setup, everyone be on time) -Expecting an integrated discussion of processing results and associated characterization. -More difficult this time. You don t have the same amount of room, but more to cover. Be succinct and to the point. -Practice makes perfect, test your talk on the projection system -No homework Reading over break, but no problems due the following Tuesday.

3 Where were we? Si solar Cell Two Levels of Masks - photoresist, alignment Etch and oxidation to isolate thermal oxide, deposited oxide, wet etching, dry etching, isolation schemes Doping - diffusion/ion implantation Metallization - Materials deposition, PVD, CVD

4 Ion Implantation Exclusive approach to introduce dopants into silicon B +, As +, P + Generate positive ions Accelerate ( kev) Implant Supplanted diffusion for the following reasons: Precise control of dosage (Q o ) Purity - nothing else added (compare to AsH 3, B 2 O 3 ) Less lateral diffusion (anisotropic process) Good depth control (Abrupt junctions, complex profiles) Cold process - can use a photoresist mask Amenable to control/automation

5 How does it work? Basically four subsystems Ion source: plasma used to generate ions Mass Discrimination: Bending magnet to separate ions Acceleration: Transfer the desired energy End station: wafer handling beam rastering

6 Ion implantation parameters Range and Straggle R p : Projected Range (ion stopping is a random process) R p : Projected Straggle R : Lateral Straggle

7 Ion Stopping - How does it work? Ion transfers energy to the crystal by: Nuclear Collisions Coulombic interactions with target electrons We denote the energy loss per unit length by these two processes as S n and S e. The electronic stopping is modeled a lot like projectile motion with drag (air resistance) you studied in Physics I S e v,s e = k e E This then tells us the energy dependence of the electron stopping

8 Nuclear Scattering Consider the 1-d elastic problem, use conservation of what? initial In[1]:= PlotA4m28êHm +28L 2, 8m, 0, 150<E 1 final Relative energy loss per collision Incident ion Mass (AMU)

9 What have we forgotten! What haven t we forgotten? Effect of impact parameter and inelastic collisions are very important

10 Ion Channeling Less Damage - More Straggle

11 Implantation damage Ion scattering produces displaced atoms - interstitials, vacancies etc. Above a critical dose the substrate becomes amorphous Post implant anneal is typically used to: Repair Silicon Regrow amorphous layers (SPE) Activate Dopants - Substitutional Distribute Profile

12 Buried Dielectrics by implantation SIMOX - Separation by IMplanted Oxygen (for SOI) Intentionally channel High Energy - deep ( kev) Long Time/Hi Dosage (10 18 vs for doping) Elevated Temperature: Anneal Damage during implant Final High T anneal step ( C) O + Anneal

13 Some Disadvantages High temperature processing still required Ion implantation damages the crystal structure Annealing damage Dopant activation Redistribute dopants Performance Limitations Lateral distribution is not zero Wafer charging diverts beam Implant depth is limited to about 1µm Smaller Throughput Requires single wafer processing Involves rastering the beam and substrate Extremely Expensive Complex machinery: High capital cost Maintenance: Almost needs a PhD to run it

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