MC74VHC138/D. 3-to-8 Line Decoder

Transcription

1 MCHC8 -to-8 Line Decoder The MCHC8 is an advanced high speed CMOS to 8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs ( A) determine which one of the outputs (Y0 Y) will go Low. When enable input E is held Low or either E or E is held High, decoding function is inhibited and all outputs go high. E, E, and E inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of systems to systems. High Speed: t PD =.ns (Typ) at CC = Low Power Dissipation: I CC = μa (Max) at T A = C High Noise Immunity: NIH = NIL = 8% CC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for to. Operating Range Low Noise: OLP = 0.8 (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 00 ma ESD Performance: HBM > 000 ; Machine Model > 00 Chip Complexity: FETs or 0. Equivalent Gates These Devices are Pb Free and are RoHS Compliant SOIC D SUFFIX CASE B TSSOP DT SUFFIX CASE 8F MARKING DIAGRAMS HC8G AWLYWW 8 ORDERING INFORMATION HC 8 ALYW HC8 = Specific Device Code A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or = Pb Free Package Device Package Shipping 8 MCHC8DG SOIC 8 Units/Rail MCHC8DRG SOIC 00 Units/Reel MCHC8DTRG TSSOP 00 Units/Reel Semiconductor Components Industries, LLC, 0 May, 0 Rev. Publication Order Number: MCHC8/D

2 MCHC8 PIN ASSIGNMENT CC A Y0 A Y E Y E Y E Y Y 0 Y GND 8 Y FUNCTION TABLE LOGIC DIAGRAM Inputs Outputs E E E A A Y0 Y Y Y Y Y Y Y X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L H = high level (steady state); L = low level (steady state); X = don t care SELECT INPUTS ENABLE INPUTS A A E E E 0 Y0 Y Y Y Y Y Y Y ACTIE-LOW OUTPUTS

3 MCHC8 A A E E E 0 Y Y Y Y Y Y Y Y0 EXPANDED LOGIC DIAGRAM IEC LOGIC DIAGRAM Y0 Y Y Y Y Y Y Y 0 A A E E E BIN/OCT 0 EN & Y0 Y Y Y Y Y Y Y 0 A A E E E 0 DMUX 0 & G 0

4 MCHC8 Î MAXIMUM RATINGS* SymbolÎ Parameter Î alue Î Unit CC Î DC Supply oltage Î 0. to +.0Î in Î DC Input oltage Î 0. to +.0Î out Î DC Output oltage Î 0. to CC + 0.Î I IK Î Input Diode Current Î 0 Î ma I OK Î Output Diode Current Î ± 0 Î ma I out Î DC Output Current, per Pin Î ± Î ma I CC Î DC Supply Current, CC and GND Pins Î ± Î ma P D Î Power Dissipation in Still Air, SOIC Packages Î 00 Î mw TSSOP Package 0 Î T stg Î Storage Temperature Î to + 0 Î C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Derating SOIC Packages: mw/ C from to C TSSOP Package:. mw/ C from to C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Î Min MaxÎ Unit CC DC Supply oltage Î.0.Î in DC Input oltage Î 0.Î out DC Output oltage Î 0 CC Î T A Operating Temperature Î + Î C t r, t f Input Rise and Fall Time CC =. ±0. Î 0 CC =.0 ± Î 0Î ns/ The JA of the package is equal to /Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. DEICE JUNCTION TEMPERATURE ERSUS TIME TO 0.% BOND FAILURES Junction Temperature C Time, Hours Time, Years 80,0,00.8 0, , ,00. 0,000. 0, ,00.0 NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 0 C TJ = 0 C TJ = 0 C TJ = 00 C TJ = 0 C TJ = 80 C TIME, YEARS Figure. Failure Rate vs. Time Junction Temperature

5 MCHC8 DC ELECTRICAL CHARACTERISTICS Î Symbol Parameter Test ConditionsÎ T A = C Î T A = 8 C T A = C CC () Min Typ Î Max Î Min Max Min Î Max Unit IH Minimum High Level.0Î.. Input oltage Î.Î.8.8 IL Maximum.0 0. Î Î 0. Low Level Input oltage.. Î Î. Î.. Î Î. OH Minimum High Level IN = IH or IL Î.0Î..0 Î Î.. Output oltage I IN = IH or IL OH = 0 μa Î.Î.. Î Î.. Î IN = IH or IL Î Î I OH = ma Î.0 Î.8 Î Î Î Î Î.8 Î Î. I OH = 8 ma OL Maximum Low Level Output IN = IH or IL I OL = 0 μa Î Î 0. Î Î 0. oltage. 0.0 Î 0. Î Î 0. IN = IH or IL IN = IH or IL Î I Î Î OL = ma I OL = 8 ma Î Î Î I IN Maximum Input IN =. or Î Leakage Current GND Î 0 to ± 0. Î.Î ±.0 ±.0 Î μa I CC Maximum Quiescent IN = CC or GND Î..0 Î μa Supply Current AC ELECTRICAL CHARACTERISTICS (Input t r = t f =.0ns) T A = 0 to T A = Symbo T A = C Î 8 C C l Parameter Test Conditions Î Min Î Typ Î Max Î Min Î Max Min Î Max Unit t PLH, Maximum CC =. ± 0. C L = pf Î 8. Î.Î.0Î..0 Î. ns t PHL Propagation Delay, C L = 0pF A to Y Î CC =.0 ± 0. C L = pf C L = 0pFÎ.. Î 8. 0.Î.0Î Î. t PLH, Maximum CC =. ± 0. C L = pfî t PHL Propagation Delay, C L = 0pFÎ Î Î Î Î 8. 0.Î.8.Î Î.0 ns 8..0 Î 8. E to Y CC =.0 ± 0. C L = pfî. Î 8.Î.0Î..0 Î. C L = 0pF t PLH, Maximum t PHL Propagation Delay, CC =. ± 0. C L = pf C L = 0pFÎ Î Î Î 8. 0.Î..Î.0Î..0. ns.0.0 Î.0 E or E to Y CC =.0 ± 0. C L = pfî C L = 0pFÎ.8. Î 8. 0.Î.0.0Î..0 Î...0 Î. C IN Maximum Input Î 0Î 0 pf Capacitance C, CC =.0 C PD Power Dissipation Capacitance (Note ) pf. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD CC f in + I CC CC.

6 MCHC8 SWITCHING WAEFORMS A t PLH 0% ALID ALID t PHL CC GND E t PHL 0% t PLH CC GND Y 0% CC Y 0% CC Figure. Figure. TEST POINT E or E 0% t PHL t PLH CC GND DEICE UNDER TEST OUTPUT C L * Y 0% CC Figure. *Includes all probe and jig capacitance Figure. Test Circuit INPUT Figure. Input Equivalent Circuit

7 MCHC8 PACKAGE DIMENSIONS SOIC CASE B 0 ISSUE K A 8 B P 8 PL 0. (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 8.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION 0. (0.00) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0. (0.00) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G D PL K C M R X J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G. BSC 0.00 BSC J K M 0 0 P R (0.00) M T B S A S SOLDERING FOOTPRINT 8X.0 X. X 0.8. PITCH 8 DIMENSIONS: MILLIMETERS

8 MCHC8 PACKAGE DIMENSIONS 0. (0.00) T 0. (0.00) T 0.0 (0.00) T SEATING PLANE L U PIN IDENT. U D S S X L/ C X K REF 0.0 (0.00) M T U S S 8 A G B U TSSOP CASE 8F 0 ISSUE B H J N N J F DETAIL E DETAIL E SOLDERING FOOTPRINT.0 K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N 0. (0.00) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 8.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0. (0.00) PER SIDE.. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0. (0.00) PER SIDE.. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.00) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0. BSC 0.0 BSC H J J K K L.0 BSC 0. BSC M PITCH X 0. X. DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 80 USA Phone: 0 or Toll Free USA/Canada Fax: 0 or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 0 0 Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MCHC8/D