NLSX Bit 20 Mb/s Dual-Supply Level Translator

Transcription

1 2-Bit 20 Mb/s Dual-Supply Level Translator The NLSX4373 is a 2 bit configurable dual supply bidirectional auto sensing translator that does not require a directional control pin. The I/O and I/O ports are designed to track two different power supply rails, and respectively. The supply rail is configurable from.5 V to 5.5 V while supply rail is configurable to.5 V to 5.5 V. This allows voltage logic signals on the side to be translated into lower, higher or equal value voltage logic signals on the side, and vice versa. The NLSX4373 translator has open drain outputs with integrated 0 k pullup resistors on the I/O lines. The integrated pullup resistors are used to pullup the I/O lines to either or. The NLSX4373 is an excellent match for open drain applications such as the I 2 C communication bus. Features can be Less than, Greater than or Equal to Wide Operating Range:.5 V to 5.5 V Wide Operating Range:.5 V to 5.5 V High Speed with 20 Mb/s Guaranteed Date Rate Low Bit to Bit Skew Enable Input and I/O Lines have Overvoltage Tolerant (OVT) to 5.5 V Nonpreferential Powerup Sequencing Integrated 0 k Pullup Resistors Small packaging: UDFN, SO, Micro NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable* This is a Pb Free Device Typical Applications I 2 C, SMBus, PMBus Low Voltage ASIC Level Translation Mobile Phones, PDAs, Cameras Important Information ESD Protection for All Pins Human Body Model (HBM) > 7000 V A Y W VF M A L Y W UDFN MU SUFFIX CASE 57AJ = Specific Device Code = Date Code = Pb Free Package ORDERING INFORMATION MARKING DIAGRAMS VFM Device Package Shipping NLSX4373MUTAG NLVSX4373MUTAG* NLSX4373DR2G SO D SUFFIX CASE 75 = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package Micro DM SUFFIX CASE 46A = Assembly Location = Year = Work Week = Pb Free Package UDFN (Pb Free) UDFN (Pb Free) SO (Pb Free) SX4373 ALYW 4373 AYW 3000/Tape & Reel 3000/Tape & Reel 2500/Tape & Reel NLVSX4373DR2G* NLSX4373DMR2G SO (Pb Free) Micro (Pb Free) 2500/Tape & Reel 4000/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD0/D. Semiconductor Components Industries, LLC, 203 July, 203 Rev. 6 Publication Order Number: NLSX4373/D

2 LOGIC DIAGRAM GND I/O I/O I/O 2 I/O 2 PIN ASSIGNMTS I/O I/O 2 GND UDFN (Top View) I/O I/O 2 I/O I/O 2 GND SOIC (Top View) I/O I/O 2 I/O I/O 2 GND Micro (Top View) I/O I/O 2 PIN ASSIGNMT Pins Description Input Voltage Input Voltage GND Ground Output Enable I/O n I/O Port, Referenced to I/O n I/O Port, Referenced to FUNCTION TABLE L H Operating Mode Hi Z I/O Buses Connected 2

3 MAXIMUM RATINGS Symbol Parameter Value Condition Unit High side DC Supply Voltage 0.3 to +7.0 V High side DC Supply Voltage 0.3 to +7.0 V I/O Referenced DC Input/Output Voltage 0.3 to ( + 0.3) V I/O Referenced DC Input/Output Voltage 0.3 to ( + 0.3) V V Enable Control Pin DC Input Voltage 0.3 to +7.0 V I I/O_SC Short Circuit Duration (I/O and I/O to GND) 40 Continuous ma T STG Storage Temperature 65 to +50 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMDED OPERATING CONDITIONS Symbol Parameter Min Max Unit High side Positive DC Supply Voltage V High side Positive DC Supply Voltage V V Enable Control Pin Voltage GND 5.5 V V IO Enable Control Pin Voltage GND 5.5 V T A Operating Temperature Range C R Pullup 0 k PU One Shot Block Gate Bias One Shot Block PU2 R Pullup 0 k I/O N I/O Figure. Block Diagram ( I/O Line) 3

4 DC ELECTRICAL CHARACTERISTICS ( =.5 V to 5.5 V and =.5 V to 5.5 V, unless otherwise specified) Symbol Parameter Test Conditions Min 40 C to +5 C Typ (Notes, 2) V IHC I/O Input HIGH Voltage 0.4 V V ILC I/O Input LOW Voltage 0.5 V V IHL I/O Input HIGH Voltage 0.2 V V ILL I/O Input LOW Voltage 0.5 V V IH Control Pin Input HIGH Voltage 0.2 V V IL Control Pin Input LOW Voltage 0.5 V V OHC I/O Output HIGH Voltage I/O Source Current = 20 A 2/3 * V V OLC I/O Output LOW Voltage I/O Sink Current = 20 A /3 * V V OHL I/O Output HIGH Voltage I/O Source Current = 20 A 2/3 * V V OLL I/O Output LOW Voltage I/O Sink Current = 20 A /3 * V I QVCC Supply Current I/O and I/O Unconnected, V = A I QVL Supply Current I/O and I/O Unconnected, V = A Max Unit I TS VCC Tristate Output Mode Supply Current I/O and I/O Unconnected, V = GND I TS VL Tristate Output Mode Supply Current I/O and I/O Unconnected, V = GND 0..0 A 0..0 A I OZ I/O Tristate Output Mode Leakage Current T A = +25 C 0..0 A R PU Pullup Resistor I/O and T A = +25 C 0 k. Typical values are for = +2. V, = +. V and T A = +25 C. 2. All units are production tested at T A = +25 C. Limits over the operating temperature range are guaranteed by design. 4

5 TIMING CHARACTERISTICS RAIL TO RAIL DRIVING CONFIGURATIONS (I/O test circuit of Figures 2 and 3, C LOAD = 5 pf, driver output impedance 50, R LOAD = M ) Symbol Parameter Test Conditions 40 C to +5 C (Notes 3 and 4) Min Typ Max =.5 V, = 5.5 V t RVCC I/O Risetime 5 ns t FVCC I/O Falltime 20 ns t RVL I/O Risetime 30 ns t FVL I/O Falltime 0 ns t PDVL VCC Propagation Delay (Driving I/O ) 20 ns t PDVCC VL Propagation Delay (Driving I/O ) 20 ns t PPSKEW Part to Part Skew 5 ns Maximum Data Rate 20 Mb/s =. V, = 2. V t RVCC I/O Risetime 5 ns t FVCC I/O Falltime 5 ns t RVL I/O Risetime 25 ns t FVL I/O Falltime 0 ns t PDVL VCC Propagation Delay (Driving I/O ) 5 ns t PDVCC VL Propagation Delay (Driving I/O ) 5 ns t PPSKEW Part to Part Skew 5 ns Maximum Data Rate 20 Mb/s = 2.5 V, = 3.6 V t RVCC I/O Risetime 5 ns t FVCC I/O Falltime 0 ns t RVL I/O Risetime 5 ns t FVL I/O Falltime 0 ns t PDVL VCC Propagation Delay (Driving I/O ) 5 ns t PDVCC VL Propagation Delay (Driving I/O ) 5 ns t PPSKEW Part to Part Skew 5 ns Maximum Data Rate 20 Mb/s = 2. V, =. V t RVCC I/O Risetime 25 ns t FVCC I/O Falltime 0 ns t RVL I/O Risetime 20 ns t FVL I/O Falltime 5 ns t PDVL VCC Propagation Delay (Driving I/O ) 5 ns t PDVCC VL Propagation Delay (Driving I/O ) 5 ns t PPSKEW Part to Part Skew 5 ns Maximum Data Rate 20 Mb/s 3. Typical values are for = +3.3 V, = +. V and T A = +25 C. 4. All units are production tested at T A = +25 C. Limits over the operating temperature range are guaranteed by design. Unit 5

6 TIMING CHARACTERISTICS RAIL TO RAIL DRIVING CONFIGURATIONS (I/O test circuit of Figures 2 and 3, C LOAD = 5 pf, driver output impedance 50, R LOAD = M ) Symbol Parameter Test Conditions Min 40 C to +5 C (Notes 3 and 4) = 3.6 V, = 2.5 V t RVCC I/O Risetime 5 ns t FVCC I/O Falltime 0 ns t RVL I/O Risetime 5 ns t FVL I/O Falltime 5 ns t PDVL VCC Propagation Delay (Driving I/O ) 5 ns t PDVCC VL Propagation Delay (Driving I/O ) 5 ns t PPSKEW Part to Part Skew 5 ns Maximum Data Rate 20 Mb/s = 5.5 V, =.5 V t RVCC I/O Risetime 30 ns t FVCC I/O Falltime 0 ns t RVL I/O Risetime 5 ns t FVL I/O Falltime 20 ns t PDVL VCC Propagation Delay (Driving I/O ) 20 ns t PDVCC VL Propagation Delay (Driving I/O ) 20 ns t PPSKEW Part to Part Skew 5 ns Maximum Data Rate 20 Mb/s 3. Typical values are for = +3.3 V, = +. V and T A = +25 C. 4. All units are production tested at T A = +25 C. Limits over the operating temperature range are guaranteed by design. Typ Max Unit TIMING CHARACTERISTICS OP DRAIN DRIVING CONFIGURATIONS (I/O test circuit of Figures 4 and 5, C LOAD = 5 pf, driver output impedance 50, R LOAD = M ) Symbol Parameter Test Conditions 40 C to +5 C (Notes 5 and 6) Min Typ Max V t RVCC I/O Risetime 400 ns t FVCC I/O Falltime 50 ns t RVL I/O Risetime 400 ns t FVL I/O Falltime 60 ns t PDVL VCC Propagation Delay (Driving I/O ) 000 ns t PDVCC VL Propagation Delay (Driving I/O ) 000 ns t PPSKEW Part to Part Skew 50 ns MDR Maximum Data Rate 2 Mb/s 5. Typical values are for = +3.3 V, = +. V and T A = +25 C. 6. All units are production tested at T A = +25 C. Limits over the operating temperature range are guaranteed by design. Unit 6

7 TEST SETUPS NLSX4373 NLSX4373 Source I/O I/O C LOAD I/O C LOAD I/O R LOAD R LOAD Source Figure 2. Rail to Rail Driving I/O Figure 3. Rail to Rail Driving I/O NLSX4373 I/O I/O C LOAD NLSX4373 I/O C LOAD R LOAD R LOAD Figure 4. Open Drain Driving I/O Figure 5. Open Drain Driving I/O I/O 0% t RISE/FALL 3 ns I/O 0% t RISE/FALL 3 ns t PD_VL VCC I/O t PD_VL VCC t PD_VCC VL I/O t PD_VCC VL 0% 0% t F VCC t R VCC t F VL t R VL Figure 6. Definition of Timing Specification Parameters 7

8 PULSE GERATOR DUT R 2x OP R T C L R L t PZH, t PHZ Test Switch Open t PZL, t PLZ 2 x C L = 5 pf or equivalent (Includes jig and probe capacitance) R L = R = 50 k or equivalent R T = Z OUT of pulse generator (typically 50 ) Figure 7. Test Circuit for Enable/Disable Time Measurement Input Output t R t PLH t R 0% 0% t F t PHL t F GND Output Output t PZL t PZH t PLZ t PHZ 0% GND HIGH IMPEDANCE V OL V OH HIGH IMPEDANCE Figure. Timing Definitions for Propagation Delays and Enable/Disable Measurement

9 APPLICATIONS INFORMATION Level Translator Architecture The NLSX4373 auto sense translator provides bi directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, and, which set the logic levels on the input and output sides of the translator. When used to transfer data from the to the ports, input signals referenced to the supply are translated to output signals with a logic level matched to. In a similar manner, the to translation shifts input signals with a logic level compatible to to an output signal matched to. The NLSX4373 consists of two bi directional channels that independently determine the direction of the data flow without requiring a directional pin. The one shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high to low and low to high transitions. Each input/output channel has an internal 0 k pull. The magnitude of the pullup resistors can be reduced by connecting external resistors in parallel to the internal 0 k resistors. Input Driver Requirements The rise (t R ) and fall (t F ) timing parameters of the open drain outputs depend on the magnitude of the pull up resistors. In addition, the propagation times (t PD ), skew (t PSKEW ) and maximum data rate depend on the impedance of the device that is connected to the translator. The timing parameters listed in the data sheet assume that the output impedance of the drivers connected to the translator is less than 50 k. Enable Input () The NLSX4373 has an Enable pin () that provides tri state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O and I/O pins to a high impedance state. Normal translation operation occurs when the pin is equal to a logic high signal. The pin is referenced to the supply and has Overvoltage Tolerant (OVT) protection. Power Supply Guidelines During normal operation, supply voltage can be greater than, less than or equal to. The sequencing of the power supplies will not damage the device during the power up operation. For optimal performance, 0.0 F to 0. F decoupling capacitors should be used on the and power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. 9

10 PACKAGE DIMSIONS UDFN. x.2, 0.4P CASE 57AJ ISSUE O 0.0 C PIN ONE REFERCE 0.0 C 0.05 C 0.05 C (b2) D ÏÏ ÏÏ e/2 TOP VIEW (A3) A SIDE VIEW 4 e A B E A DETAIL A X L C SEATING PLANE L DETAIL A NOTE 5 NOTES:. DIMSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMSION: MILLIMETERS. 3. DIMSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWE 0.5 AND 0.30 mm FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH MAY NOT EXCEED 0.03 ONTO BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b b REF D.0 BSC E.20 BSC e 0.40 BSC L L L REF (L2) 5 BOTTOM VIEW X b 0.0 M C A B 7X 0.05 M C NOTE MOUNTING FOOTPRINT SOLDERMASK DEFINED X PITCH DIMSIONS: MILLIMETERS 0

11 PACKAGE DIMSIONS SO CASE ISSUE AK X B Y A 5 4 S 0.25 (0.00) M Y M K NOTES:. DIMSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMSION: MILLIMETER. 3. DIMSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMSION AT MAXIMUM MATERIAL CONDITION THRU ARE OBSOLETE. NEW STANDARD IS Z H G D C 0.25 (0.00) M Z Y S X S SEATING PLANE 0.0 (0.004) N X 45 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.27 BSC BSC H J K M 0 0 N S SOLDERING FOOTPRINT* SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

12 PACKAGE DIMSIONS Micro CASE 46A 02 ISSUE H PIN ID H E T SEATING PLANE 0.03 (0.005) e D E b PL 0.0 (0.003) M T B S A S A NOTES:. DIMSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMSION: MILLIMETER. 3. DIMSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE A-0 OBSOLETE, NEW STANDARD 46A-02. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A A b c D E e 0.65 BSC BSC L H E A c L SOLDERING FOOTPRINT*.04 X X X SCALE : mm inches Micro is a trademark of International Rectifier. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your loca Sales Representative NLSX4373/D