Ch 5: Designing a Single Cycle Datapath

Transcription

1 Ch 5: Designing a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s Topic: Design a Single Cycle Processor machine design Arithmetic (Ch 4) inst. set design (Ch 3) technology

2 The Big Picture: The Performance Perspective CPI Performance of a machine is determined by: count Clock cycle time Inst. Count Clock cycles per instruction Processor design (path and control) will determine: Clock cycle time Clock cycles per instruction Today: Single cycle processor: Advantage: One clock cycle per instruction Disadvantage: long cycle time Cycle Time How to Design a Processor: step-by-step. Analyze instruction set => path requirements the meaning of each instruction is given by the register transfers path must include storage element for ISA registers possibly more path must support each register transfer 2. Select set of path components and establish clocking methodology 3. Assemble path meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic 2

3 The MIPS Formats All MIPS instructions are bits long. The three instruction formats: R-type I-type J-type 3 3 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 26 op target address 6 bits 26 bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction Step a: The MIPS-lite Subset 3 ADD, SUB, AND, OR add rd, rs, rt sub rd, rs, rt and rd, rs,rt or rd,rs,rt 3 LOAD and STORE Word lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: 3 beq rs, rt, imm op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 26 2 op rs rt immediate 6 bits 5 bits 5 bits 6 bits 26 2 op rs rt immediate 6 bits 5 bits 5 bits 6 bits

4 Logical Register Transfers RTL gives the meaning of the instructions First step is to fetch the instruction from op rs rt rd shamt funct = MEM[ PC ] op rs rt Imm6 = MEM[ PC ] inst Register Transfers ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 OR R[rt] < R[rs] R[rt]; PC < PC + 4 LOAD R[rt] < MEM[ R[rs] + sign_ext(imm6)]; PC < PC + 4 STORE MEM[ R[rs] + sign_ext(imm6) ] < R[rt]; PC < PC + 4 BEQ if ( R[rs] == R[rt] ) then PC < PC + sign_ext(imm6)] else PC < PC + 4 Step : Requirements of the Set Memory instruction & Registers ( x ) read RS read RT RT or RD PC Extender and Sub register or extended immediate 4 or extended immediate to PC 4

5 Step 2: Components of the path Combinational Elements Storage Elements Clocking methodology Abstract/Simplified View of path Register # PC ress Registers Register # Register # ress Two types of functional units: elements that operate on values (combinational) elements that contain state (sequential) 5

6 Combinational Logic Elements (Basic Building Blocks) er A B er CarryIn Sum Carry MUX Selec t A Y B MUX A B O P Result State Elements: Review Unclocked vs. Clocked Clocks used in synchronous logic when should an element that contains state be updated? falling edge cycle time rising edge 6

7 An unclocked state element The set-reset latch output depends on present inputs and also on past inputs R Q S _ Q Latches and Flip-flops Output is equal to the stored value inside the element (don't need to ask for permission to look at the value) Change of state (value) is based on the clock Latches: whenever the inputs change, and the clock is asserted Flip-flop: state changes only on a clock edge (edge-triggered methodology) "logically true", could mean electrically low A clocking methodology defines when signals can be read and written wouldn't want to read a signal at the same time it was being written 7

8 D-latch Two inputs: the value to be stored (D) the clock signal (C) indicating when to read & store D Two outputs: the value of the internal state (Q) and its complement C Q D D _ Q C Q D flip-flop Output changes only on the clock edge D D D Q latch C D Q D latch _ C Q Q _ Q C D C Q 8

9 Our Implementation An edge triggered methodology Typical execution: read contents of some state elements, send values through some combinational logic write results to one or more state elements State element Combinational logic State element 2 Clock cycle State element Combinational logic Storage Element: Register (Basic Building Block) Register Similar to the D Flip Flop except N-bit input and output Enable input Enable: negated (): Out will not change asserted (): Out will become In Enable In N Clk Out N 9

10 Register File Built using D flip-flops register number register number 2 Register Register Register n Register n M u x register number register number 2 Register file register 2 M u x 2 Register File Note: we still use the clock to determine when to write Register nu mber n-to- decoder n n C Register D C Register D Register C Register n D C Register n D

11 Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: Enable busw Clk RWRARB bit Registers RA (number) selects the register to put on busa () RB (number) selects the register to put on busb () RW (number) selects the register to be written via busw () when Enable is Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: RA or RB valid => busa or busb valid after access time. busa busb Storage Element: Idealized Memory Enable ress Memory (idealized) One input bus: In In Out One output bus: Out Memory word is selected by: Clk ress selects the word to put on Out Enable = : address selects the word to be written via the In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: ress valid => Out valid after access time.

12 Clocking Methodology Clk Setup Hold Don t Care Setup Hold All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time Step 3 Register Transfer Requirements > path Assembly Fetch Operands and Execute Operation 2

13 3a: Overview of the Fetch Unit The common RTL operations Fetch the : mem[pc] Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- something else We don t know if instruction is a Branch/Jump or one of the other instructions until we have fetched and interpreted the instruction from. So all instructions initially increment the PC address PC Sum a. b. Program counter c. er 3

14 path for Fetch 4 PC address 3b: R-format instructions: add, sub, and, or, slt R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt register, register 2, and register come from instruction s rs, rt, and rd fields control and Reg: control logic after decoding the instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Register numbers 5 3 register 5 5 register 2 Registers register 2 Reg control Zero result a. Registers b. 4

15 path for R-format instructions register register 2 Registers register 2 Reg 3 operation Zero result Clk PC Rs, Rt, Rd, Op, Func ctr Register-Register Timing Old Value Clk-to-Q New Value Old Value Old Value Memory Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value Delay busw Old Value New Value RegWr busw Clk Rd Rs Rt Rw Ra Rb -bit Registers busa busb ctr Result Register Occurs Here 5

16 3d: Load & Store Operations R[rt] <- Mem[R[rs] + SignExt[imm6]] Example: lw rt, rs, imm6 Mem[ R[rs] + SignExt[imm6] <- R[rt] ] Example: sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits Mem ress 6 Sign extend Mem a. unit b. Sign-extension unit path for lw & sw register register 2 Registers register Reg 2 3 operation Zero result ress Mem 6 Sign extend Mem 6

17 3f: The Branch op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 beq rs, rt, imm6 mem[pc] Fetch the instruction from Equal <- R[rs] == R[rt] Calculate the branch condition if (COND eq ) Calculate the next instruction s address PC <- PC ( SignExt(imm6) x 4 ) else PC <- PC + 4 path for branch instruction PC + 4 from instruction path Sum Branch target Shift left 2 register register 2 Registers register Reg 2 6 Sign extend 3 operation Zero To branch control logic 7

18 Using multiplexors to stitch together the path for access and R-format instructions 4 PC address Registers register register 2 register Reg 2 Src M ux 3 operation Zero result ress Mem MemtoReg M ux 6 Sign extend Mem Putting it all together PCSrc M ux PC 4 address register register 2 register Registers 2 Reg 6 Sign extend Shift left 2 Src M ux result 3 operation Zero result ress Mem Mem MemtoReg M ux 8

19 Putting it all together cont d PCSrc M ux 4 Reg Shift left 2 result PC address [3 ] [25 2] [2 6] M ux [5 ] RegDst [5 ] register register 2 register 2 Registers 6 Sign extend Src M ux control Zero result Mem ress Mem MemtoReg M ux [5 ] Op ing the control unit M ux result 4 RegDst Branch Shift left 2 PCSrc Mem [3 26] Control MemtoReg Op Mem Src Reg PC address [3 ] [25 2] [2 6] [5 ] M ux register register 2 Registers register 2 M u x Zero result ress M u x [5 ] 6 Sign extend control [5 ] 9

20 An Abstract View of the Critical Path Register file and ideal : The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: ress valid => Output valid after access time. Next ress Ideal Memory ress Clk PC Rd 5 Clk Rs 5 Rw Ra Rt 5 Rb -bit Registers Imm 6 A B Critical Path (Load Operation) = PC s Clk-to-Q + Memory s Access Time + Register File s Access Time + to Perform a -bit + Memory Access Time + Setup Time for Register File + Clock Skew ress In Clk Ideal Memory Step 4: Given path: RTL -> Control <3:> Inst Memory Adr Op <2:25> <2:25> Fun Rt <:5> <:5> <6:2> Rs Rd Imm6 Control Branch RegWr RegDst Src op MemRd MemWr MemtoReg Zero DATA PATH 2

21 Control Selecting the operations to perform (, read/write, etc.) Design the Control Unit Controlling the flow of (multiplexor inputs) Design the Main Control Unit Information comes from the bits of the instruction Example: add $8, $7, $8 Format: op rs rt rd shamt funct 's operation based on instruction type and function code Control e.g., what should the do with this instruction Example: lw $, ($2) 35 2 op rs rt 6 bit offset control input AND OR add subtract set-on-less-than Why is the code for subtract and not?) (Recall design of from Chapter 4. Bnegate input for adder set to for subtraction 2

22 Control Design opcode LW Op operation Load word Funct field xxxxxx Desired action control input SW Store word xxxxxx BEQ Branch eq xxxxxx Subtract R-type R-type Subtract Subtract R-type AND And R-type OR Or R-type Set on less than Set on less than Control Must describe hardware to compute 3-bit control input given instruction type = lw, sw = beq = arithmetic function code for arithmetic Describe it using a truth table (can turn into gates): Op computed from instruction type Op Funct field Operation Op Op F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X 22

23 Design the main control unit Seven control signals RegDst Reg Src PCSrc Mem Mem MemtoReg Control Signals. RegDst = => Register destination number for the register comes from the rt field (bits 2-6) RegDst = => Register destination number for the register comes from the rd field (bits 5-) 2. Reg = => The register on the register input is written with the on the input (at the next clock edge) 3. Src = => The second operand comes from 2 Src = => The second operand comes from the signextension unit 4. PCSrc = => The PC is replaced with PC+4 PCSrc = => The PC is replaced with the branch target address 5. MemtoReg = => The value fed to the register write input comes from the MemtoReg = => The value fed to the register write input comes from the 6. Mem = => 7. Mem = => 23

24 R-format instructions RegDst = Reg = Src = Branch = MemtoReg = Mem = Mem = Op = Memory access instructions Load word RegDst = Reg = Src = Branch = MemtoReg = Mem = Mem = Op = Store Word RegDst = X Reg = Src = Branch = MemtoReg = X Mem = Mem = Op = 24

25 Branch Equal RegDst = X Reg = Src = Branch = MemtoReg = X Mem = Mem = Op = Control result M u x 4 RegDst Branch Shift left 2 Mem [3 26] MemtoReg Control Op Mem Src Reg PC address [3 ] [25 2] [2 6] [5 ] M u x register register 2 Registers register 2 M u x Zero result ress M u x [5 ] 6 Sign extend control [5 ] RegDst Src Memto- Reg Reg Mem Mem Branch Op p R-format lw sw X X beq X X 25

26 Step 5: Implementing Control Simple combinational logic (truth tables) Op control block Inputs Op5 Op4 Op3 Op2 Op Op Op Op R-format Iw sw beq Outputs RegDst F3 Operation2 Src F (5 ) F2 Operation Operation MemtoReg Reg F F Operation Mem Mem Branch Op Control Unit OpO Main Control Unit Our Simple Control Structure All of the logic is combinational We wait for everything to settle down, and the right thing to be done might not produce right answer right away we use write signals along with clock to determine when to write Cycle time determined by length of the longest path State element Combinational logic State element 2 Clock cycle 26

27 An Abstract View of the Critical Path Register file and ideal : The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: ress valid => Output valid after access time. Next ress Ideal Memory ress Clk PC Rd 5 Clk Rs 5 Rw Ra Rt 5 Rb -bit Registers Imm 6 A B Critical Path (Load Operation) = PC s Clk-to-Q + Memory s Access Time + Register File s Access Time + to Perform a -bit + Memory Access Time + Setup Time for Register File + Clock Skew ress In Clk Ideal Memory Single Cycle Implementation Calculate cycle time assuming negligible delays except: (2ns), and adders (2ns), register file access (ns) PCSrc M ux 4 Reg Shift left 2 result PC address [3 ] [25 2] [2 6] M ux [5 ] RegDst [5 ] register register 2 register 2 Registers 6 Sign extend Src M ux control Zero result Mem ress Mem MemtoReg M ux [5 ] Op 27

28 A Real MIPS path (CNS T) Summary 5 steps to design a processor. Analyze instruction set => path requirements 2. Select set of path components & establish clock methodology 3. Assemble path meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic MIPS makes it easier s same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Single cycle path => CPI=, Clock Cycle Time => long 28