CPU Organization and Assembly Language

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Douglas Richards
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1 COS 140 Foundations of Computer Science School of Computing and Information Science University of Maine October 2, 2015

2 Outline

3 Homework and announcements Reading: Chapter 12 Homework: exercises at end of Chapter 12 (online); due 10/14 Slides: online Prelim I: 7 October! Detailed questions possible on material up through RAID Conceptual questions on material up to/including today s lecture

4 The central processing unit () Recall: control rest of computer All instructions (processing) done here Three parts: registers, ALU, control unit (CU) Today: organization Controlling the : and assembly

5 All s have at least some registers: counter (IC) Also called program counter (PC) Address of next instruction program status word (PSW): status bits/flags instruction register (IR): holds instruction during decoding Data registers for program s use Likely differ on how many others, what they are used for, etc.

6 Register design issues: protected or user-accessible? Want to protect the machine, other processes from current process PSW: protect (usually) IC: generally protected, but... special instructions to change it (branch, subroutine call, etc.) IR: protected Data registers: accessible via many instructions

7 Register design issues: general- or special-purpose? General-purpose flexibility Special-purpose reduce #, size of operands, maybe optimize speed Mixed: some general-, some special-purpose

8 Other register design issues Size maybe different for different purposes Combining using multiple registers as single register Responsibility for saving on interrupt hardware or software?

9 instructions: pattern of bits that cause to perform an operation set: all instructions machine can perform determines capabilities, API of comprises the machine of

10 execution Fetch instruction IR Decode instruction Fetch operands (if any) Perform instruction Store results (if any)

11 format: fields: sub of bits that have meaning op code field with unique patterns of bits specifying operations small in early computers, 1 3 bytes in Intel operands: specify data operated on by instruction 0 or more/instruction operand field may refer to different kinds of operands: in the instruction, in a register, in memory,... Other fields addressing mode, operand size specification, hints to about branch likelihood,...

12 Assembly very difficult for humans to use prone to coding errors Assembly : Human-readable machine (from 1950s on) Usually one-to-one relation to machine instructions Op codes represented by mnemonics: e.g., ADD instead of a bitstring Operands: often symbolic as well, decimal numbers, etc. Addresses within program: symbols (tags, labels) Assembler: program that translates assembly program object code (machine )

13 Abstraction Assembly : some abstraction Place within abstraction hierarchy:

14 of instructions Data transfer Arithmetic Logical Control transfer System control

15 Data transfer instructions Move data Source, destination: registers, memory Different addressing possible Transfer size: often a word could be byte could be enormous

16 Arithmetic instructions ALU carries out instructions Virtually all s: addition, subtraction, multiplication, division Signed integers, usually also floating point Often have to move data to location expected by ALU e.g., register Question: why have subtraction, etc., when you can do it all with addition?

17 Logical instructions Usually: and, or, not, xor, equal, shift, rotate, arithmetic shift Sometimes: operate on particular bits via a mask Questions: What about taking the complement? Can you do this with not? With xor? How would you use a mask to clear bits? How would you use a mask to set bits?

18 Control transfer instructions Branch (or jump) instructions Unconditional, conditional Absolute, relative, base register Subroutine call/return

19 System control instructions Protected operations: only accessed when processor is in a special kernel mode kernel mode: for OS Access protected registers, memory, etc. I/O instructions: usually in this class, too

20 How many instructions should a have? One philosophy: have only a few, simple instructions s can be optimized Simpler/fewer less chip space needed Implemented closer to CU, ALU faster RISC reduced instruction set computers Typically have many (hundreds) of registers Examples: SPARC, PowerPC

21 How many instructions should a have? Another philosophy: Large number of instructions Include special-purpose instructions (e.g., for multimedia) Easier for programmers Less memory, disk space needed CISC complex instruction set computers Example: Intel processor family

22 RISC or CISC? Advantages of RISC: register-based instructions use registers as cache for cache/memory simple, optimized instructions single instruction size very, very fast Advantages of pure CISC: ease of use may optimize in hardware some common tasks Modern s: CISC machines with some RISC-like features Pipelining, predictive execution: reduce RISC s advantages

23 of data Numbers Integers sign-magnitude, 2 s complement, packed decimal Floating point numbers (single, double) Character data: ASCII, Unicode, EBCDIC codes Strings: usually OS- or -level abstractions Logical data Blocks, general bit strings e.g., for multimedia

24 Operand fields describe operands Address mode: determines where actual operand lives (its effective address) Specified: As special in other fields Implicitly, by selection of particular opcode Modes include: immediate, direct, indirect, register, register indirect, displacement, others Issues: How many bits required for instruction? How many memory references required fetch/store actual operand

25 Immediate addressing Immediate mode: operand present in instruction itself E.g., ADD #5,loca might mean add 5 to whatever is in loca Typically a fixed-length field in the instruction Usually just for 2 s complement or characters Advantages: need only a few bits (usually) to describe operand no additional memory reference neeed to fetch operand

26 Direct addressing Direct mode: operand lives in a memory location Operand field in instruction: address of real operand E.g., ADD #5,1024: Add 5 to whatever is stored in address 1024 Bits needed for operand field? varies by computer up to size of word often less: restricted range, relative to some base address

27 Direct addressing Memory references needed: Mem 4 Data Address Busses

28 Indirect addressing Indirect mode: operand field contains not the effective address, but the address where that is stored E.g., ADD if 8 contains the 24, then this means add 5 to the contents of

29 Indirect addressing Number of memory references needed: Mem 8 Data Address Busses

30 Register addressing Operand is a register Operand field contains the register number... although... sometimes no operand: register implicit in opcode E.g., ADD #5,r4: add 5 to register 4 Few bits needed for operand field(s) RISC machines: heavy users of register addressing (maybe force for all) No need to fetch from/store to memory

31 Register indirect addressing: Register contains address of the operand, not the operand E.g., ADD if reg. 4 contains 1024, then 5 is added to that memory location Number of bits for operand field? Same as register addressing But need a memory access to fetch the effective address Question: when would you use this?

32 Other addressing Relative displacement addressing: jump relative to program counter Base register displacement addressing: set a base register all specified addresses are added to this effective address

33 set design Which operations to include? I/O instructions or memory-mapped I/O? RISC or CISC, or mixed? Format of instructions? size: part of word, word, multiple words...? Same sized instructions? Fields within instruction? Same format for all instructions? Address which, and how to specify? # of registers Address granularity?

Instruction Set Architecture (ISA)

Instruction Set Architecture (ISA) * Instruction set architecture of a machine fills the semantic gap between the user and the machine. * ISA serves as the starting point for the design of a new machine