l C-Programming l A real computer language l Data Representation l Everything goes down to bits and bytes l Machine representation Language
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1 198:211 Computer Architecture Topics: Processor Design Where are we now? C-Programming A real computer language Data Representation Everything goes down to bits and bytes Machine representation Language Very limited programming model Digital Logic Transistors g Gates g Circuits Circuits g { Memory, Registers, and Components} What are we going to do now. Processor Design Figure out how a small subset of the instruction set works in hardware Use Hardware blocks to describe data path Use control logic to ensure steps of the instruction flows smoothly Add instruction Type of add depends on where operands are located add reg1, reg2 Add contents of reg1 to reg2 and store result in reg2 add $constant, reg2 Add contents of memory immediately following the instruction to reg 2 and store result in reg2 add (effective-address), reg2 Add contents of effective address to reg2 and store result in reg2 Effective address could be relative; relative + offset; relative + offset, index; relative + offset, index*scaled 1
2 Instruction Example ADD-Add : note src, dst are reversed in the intel manual Addition Instruction Generic Form Encoded Representation addl %edx, %eax 0 3 rarb Add value in register %edx to that in register %eax Store result in register %eax Two-byte encoding First indicates instruction type Second gives source and destination registers In assembly language add src, dst means src + dst à dst Instruction Example in x86 Addition Instruction Generic Form Encoded Representation addl %edx, %eax 0 3 C 2 Opcode is 03 and src, dst are %edx, %eax from previous table (Table 2.2) code is C2 So, 03 C2 means add %edx, %eax means add 8(%ebp), %eax 05 add $cons, %eax addl 8(%ebp), %eax addl $4, %eax
3 Arithmetic and Logical Operations Instruction Code Subtract (ra from rb) And subl ra, rb Function Code 2 B rarb The second byte will vary based on type of operands Set condition codes as side effect Subtract operation- Instruction Set Reference andl ra, rb 2 3 rarb Exclusive-Or xorl ra, rb 3 3 rarb Lower 4 bits can vary depending upon the type Of operand 20 means 8 byte register transfer, Lower 4 bits can vary 30 means 8 byte register transfer, 3
4 Single cycle stages Fetch Instruction (IF) Decode Instruction (ID) Execute Instruction (EX) Memory access (MEM) Write back (WB) Update Program Counter (PC) Building Blocks Combinational Logic Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control Storage Elements Store bits Addressable memories val src valb" srcb" Non-addressable registers Loaded only as clock rises B" B" fun" Register" file" MUX" B" A 1 =" S B valw" W" dstw" Clock" Clock Fetch Instruction Add instruction (add %edx, %eax) +" +" +4" IR %edx Register file %eax PC IR Fetch Instruction and increment Program counter Op code determines type of operation 03 C2 Operands are in registers They are fed to the adder (ALU) Result stored back in register Based On Instruction the signal to ALU can be +, -, * or / 4
5 Add instruction (add $4, %eax) + mov instruction (mov 8(%ebp), %eax) +" Data mem IR %eax Register file IR %ebp Register file %eax data address Op code is determines type of operation One Operand is a register, the other is part of the instruction %eax, immediate value They are fed to the adder (ALU) Result stored back in register Op code is determines type of operation 8b 45 Load word from memory onto register %eax Address is 8 + (%ebp) R/W mov instruction (mov %eax, 8(%ebp)) +" Data mem IR %ebp Register file %eax data address Op code determines type of operation Store word from register %eax onto memory Address is 8 + (%ebp) R/W 5
6 SEQ Hardware Structure PC Write back newpc vale, valm valm SEQ Stages PC Write back newpc vale, valm valm State Program counter register (PC) Condition code register (CC) Register File Memories Access same memory space Data: for reading/writing program data Instruction: for reading instructions Instruction Flow Read instruction at address specified by PC Process through stages Update program counter Memory Execute Decode Fetch icode, ifun ra,rb valc Instruction memory Addr, Data Bch CC alua, alub srca, srcb dsta, dstb Data memory valp vale ALU vala, valb PC increment Register A B M file E Fetch Read instruction from instruction memory Decode Read program registers Execute Compute value or address Memory Read or write data Write Back Write program registers PC Update program counter Memory Execute Decode Fetch icode, ifun ra,rb valc Instruction memory Addr, Data Bch CC alua, alub srca, srcb dsta, dstb Data memory valp vale ALU vala, valb PC increment Register A B M file E PC PC Instruction Decoding Optional Optional Executing Arith./Logical Operation OPl ra, rb 6 fn" rarb icode ifun ra rb valc Instruction Format 5 0 r rb" D" Instruction byte icode:ifun Optional register byte ra:rb Optional constant word valc Fetch Read 2 bytes Decode Read operand registers Execute Perform operation Set condition codes Memory Do nothing Write back Update register PC Update Increment PC by 2 6
7 Stage Computation: Arith/ Log. Ops Fetch Decode Execute OPl ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC Memory Write R[rB] vale back PC update PC valp Read instruction byte Read register byte Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register Write back result Update PC Executing popl popl ra 8 F ra 8 Fetch Memory Read 2 bytes Read from old stack pointer Decode Write back Read stack pointer Update stack pointer Execute Write result to register Increment stack pointer by 4 PC Update Increment PC by 2 Formulate instruction execution as sequence of simple steps Use same general form for all instructions POP Instruction Stage Computation: popl Fetch Decode Execute popl ra icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala %esp valb %esp vale valb + 4 Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer Memory valm M 4 [vala] Read from stack Write R[%esp] vale back R[rA] valm PC update PC valp Use ALU to increment stack pointer Must update two registers Popped value New stack pointer Update stack pointer Write back result Update PC 7
8 Executing Jumps jxx Dest 7 fn" Dest" fall thru: XX XX Not taken Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] Read instruction byte target: XX XX Fetch Read 5 bytes Increment PC by 5 Decode Do nothing Execute Determine whether to take branch based on jump condition and condition codes Taken Memory Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch Fetch Decode valc M 4 [PC+1] valp PC+5 Compute both addresses Read destination address Fall through address Execute Bch Cond(CC,ifun) Take branch? Memory Write back PC update PC Bch? valc : valp Update PC Choose based on setting of condition codes and branch condition Executing call call Dest E 8 Dest" return: XX XX target: XX XX Fetch Read 5 bytes Increment PC by 5 Decode Read stack pointer Execute Decrement stack pointer by 4 Memory Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest 8
9 Stage Computation: call call Dest icode:ifun M 1 [PC] Read instruction byte Call Opcodes in X86 Fetch Decode Execute valc M 4 [PC+1] valp PC+5 valb R[%esp] vale valb + 4 Read destination address Compute return point Read stack pointer Decrement stack pointer Memory M 4 [vale] valp Write return value on stack Write R[%esp] vale back PC update PC valc Update stack pointer Set PC to destination Use ALU to decrement stack pointer Store incremented PC Executing ret ret C 3 return: XX XX Stage Computation: ret ret icode:ifun M 1 [PC] Read instruction byte Fetch Fetch Read 1 byte Decode Read stack pointer Execute Increment stack pointer by 4 Memory Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address Decode Execute Memory Write back PC update vala R[%esp] valb R[%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale PC valm Read operand stack pointer Read operand stack pointer Increment stack pointer Read return address Update stack pointer Set PC to return address Use ALU to increment stack pointer Read return address from memory 9
10 10
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