# Instruction Set Architecture

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1 Instruction Set Architecture Consider x := y+z. (x, y, z are memory variables) 1-address instructions 2-address instructions LOAD y (r :=y) ADD y,z (y := y+z) ADD z (r:=r+z) MOVE x,y (x := y) STORE x (x:=r) 3-address instructions ADDx, y, z (x:= y+z) 0-address instructions (for stack machines) push pop PUSH y (on a stack) PUSH z (on a stack) ADD POP x

2 Points to Consider Special-purpose or general purpose? Word size and instruction size? [Now most instructions have 32-bits, and machines allow operation on 64-bit data operands] Data types? [Whatever the application demands] 0/1/2/3 address instructions, or a mix of them? [Most modern designs allow 3-address instructions, and pack them in a 32-bit frame] How many addressing modes, and which ones? [Whatever the application demands] Register or memory operands? [Register operands can be accessed faster, but you cannot have too many registers] Instruction formats and instruction encoding. [Modern designs have fewer formats and they are less clumsy]

3 Instruction Types BASIC INSTRUCTIONS Data Movement Arithmetic & Logical LOAD, STORE, MOVE ADD, SUB, AND, XOR, SHIFT Branch JUMP (unconditional) JZ, JNZ (conditional) Procedure Call Input Output Miscellaneous CALL, RETURN Memory-mapped I/O* NOP, EI (enable interrupt) SPECIAL INSTRUCTIONS Multimedia instructions (MMX) Many SIMD or vector instructions operate simultaneously on 8 bytes 4 half-words 2 words Digital Signal Processors include multiply-and-accumulate (MAC) to efficiently compute the dot-product of vectors.

4 Load Store Architecture Only LOAD and STORE instructions access the memory. All other instructions use register operands. Used in all RISC machines. If X,Y,Z are memory operands, then X:= Y+Z will be implemented as LOAD LOAD ADD r1, Y r2, Z r1, r2, r3 STORE r3, X Performance improves if the operand(s) can be kept in registers for most of the time. Registers are faster than memory. Register allocation problem.

5 Common Addressing Modes Op data type mode reg addr/data/offset opcode(o) reg (R) address (D) Mode immediate direct Register indirect Memory indirect Auto-increment meaning Operand = D Operand = M[D] Operand = M[R] Operand = M[M[D]] Operand = M[R] R = R + n (n= ) Auto-decrement R = R n (n = ) Operand = M[R] Indexed Scale-index-base (SIB) PC-relative SP-relative Operand = M[R+D] Operand = M[s * R+D] Operand = M[PC+D] Operand = M[SP+D] (Note: R = content of register R) Question: Why so many addressing modes? Do we need all?

6 RISC or CISC? Reduced Instruction Set Computers have a small number of simple, frequently used instructions. Complex Instruction Set Computers include as many instructions as users might need to write efficient programs. Features CISC RISC Semantic Gap Low High Code Size Small Large, but RAMs are cheap! Cost High Low Speed Fast only if the compiler generates appropriate code Slower, but the problem is overcome using more registers and pipelining.

7 MIPS Architecture MIPS follows the RISC architecture. It has 32 registers r0-r31. Each register has 32-bits. The conventional use of these registers is as follows: register assembly name Comment r0 r1 r2-r3 r4-r7 r8-r15 r16-r23 r24-r25 r26-r27 r28 r29 r30 r31 \$zero \$at \$v0-\$v1 \$a0-\$a3 \$t0-\$t7 \$s0-\$s7 \$t8-\$t9 \$k0-\$k1 \$gp \$sp \$fp \$ra Always 0 Reserved for assembler Stores results Stores arguments Temporaries, not saved Contents saved for use later More temporaries, not saved Reserved by operating system Global pointer Stack pointer Frame pointer Return address

8 Example assembly language programs Example 1 f = g + h i Assume that f, g, h, i are assigned to \$s0, \$s1, \$s2, \$s3 add \$t0, \$s1, \$s2 sub \$s0, \$t0, \$s3 # register \$t0 contains g + h # f = g + h i Example 2. g = h + A[8] Assume that g, h are in \$s1, \$s2. A is an array of words the elements are stored in consecutive locations of the memory. The base address is stored in \$s3. lw t0, 32(\$s3) add \$s1, \$s2, \$t0 # t0 gets A[8], 32= 4x8 # g = h + A[8]

9 0 200 Word 1 = 4 bytes Word 2 = 4 bytes Word 3 = 4 bytes 200 s3 t0 lw Word 8 = 4 bytes CPU MEMORY

10 Machine language representations Instruction add belongs to the R-type format. opcode rs rt rd shift amt function src src dst add \$s1, \$s2, \$t0 (s1 := s2 + t0) will be coded as The function field is an extension of the opcode, and they together determine the operation. Note that sub has a similar format.

11 Instruction lw (load word) belongs to I-type format. opcode rs rt address base dst offset lw \$t0, 32(\$s3) will be coded as Both lw and sw (store word) belong to I-format.

12 Making decisions if (i ==j) f = g + h; else f = g h Use bne = branch-nor-equal, beq = branch-equal, and j = jump Assume, f, g, h, are mapped into \$s0, \$s1, \$s2, and i, j are mapped into \$s3, \$s4 bne \$s3, \$s4, Else add \$s0, \$s1, \$s2 # goto Else when i=j # f = g + h j Exit # goto Exit Else: sub \$s0, \$s1, \$s2 # f = g h Exit:

13 The program counter Every machine has a program counter (called PC) that points to the next instruction to be executed Instruction Instruction Instruction 3 PC Instruction 4 data CPU data MEMORY Ordinarily, PC is incremented by 4 after each instruction is executed. A branch instruction alters the flow of control by modifying the PC.

14 Compiling a while loop while (A[i] == k) i = i + j; array A Initially \$s3, \$s4, \$s5 contains i, j, k respectively. Let \$s6 store the base of the array A. Each element of A is a 32-bit word. Loop: add \$t1, \$s3, \$s3 # \$t1 = 2*i add \$t1, \$t1, \$t1 # \$t1 = 4*i add \$t1, \$t1, \$s6 # \$t1 contains address of A[i] lw \$t0, 0(\$t1) add \$s3, \$s3, \$s4 bne \$t0, \$s5, Exit j Loop # \$t0 contains \$A[i] # i = i + j # goto Exit if A[i] k # goto Loop Exit: <next instruction> Note the use of pointers.

15 Compiling a switch statement switch (k) { case 0: case 1: case 2: case 3: f = i + j; break; f = g + h; break; f = g h; break; f = I j; break; } Assume, \$s0-\$s5 contain f, g, h, i, j, k. Assume \$t2 contains 4. slt \$t3, \$s5, \$zero bne \$t3, \$zero, Exit slt \$t3, \$s5, \$t2 beq \$t3, \$zero, Exit # if k<0 then \$t3 = 1 else \$t3=0 # if k<0 then Exit # if k<4 then \$t3 = 1 else \$t3=0 # if k 4 the Exit What next? Jump to the right case!

16 32-bit address L0 32-bit address L1 32-bit address L2 32-bit address L3 jumptable Base address of the jumptable register \$t4 L0 L1 f = i + j J Exit f = g+h j Exit Exit MEMORY

17 Here is the remainder of the program; add \$t1, \$s5, \$s5 add \$t1, \$t1, \$t1 add \$t1, \$t1, \$t4 lw \$t0, 0(\$t1) jr \$t0 L0: add \$s0, \$s3, \$s4 J Exit L1: add \$s0, \$s1, \$s2 J Exit L2: sub \$s0, \$s1, \$s2 J Exit L3: sub \$s0, \$s3, \$s4 Exit: <next instruction>

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