2 1 Implementation using NAND gates: We can write the XOR logical expression A B + A B using double negation as

Transcription

1 Chapter 2 Digital Logic asics 2 Implementation using NND gates: We can write the XOR logical expression + using double negation as + = + = From this logical expression, we can derive the following NND gate implementation: Figure 2.: 2-input XOR gate using only NND gates. Implementation using NOR gates: We can write the XOR logical expression as + = + = From this logical expression, we can derive the following NOR gate implementation:

2 2 Chapter 2 Figure 2.2: 2-input XOR gate using only NOR gates. 2 2 Implementation using NND gates: We can write the exclusive-nor logical expression + using double negation as + = + = From this logical expression, we can derive the following NND gate implementation:

3 Chapter 2 3 Implementation using NOR gates: We can write the exclusive-nor logical expression as + = + = From this logical expression, we can derive the following NOR gate implementation: lternative Implementations: lternatively, we can derive the following NND implementation by modifying the logic circuit in Figure 2. by adding an output inverter:

4 4 Chapter 2 Similarly, we derive the following NOR implementation by modifying the logic circuit in Figure 2.2 by deleting the output inverter: 2 3 NOT gate can be implemented by holding one input at as shown below: 2 4 y keeping one input at, we can turn an XOR gate into a buffer that passes input to output as shown below: It is clear from this and the last exercise that by controlling one input (call it control input), we can turn an XOR gate into either an inverter or a buffer. If the control input is, the XOR gate acts as an inverter; if the control input is, it acts as a buffer. 2 5 We can write the ND logical expression ( ) using double negation as = = + From this logical expression, we can derive the following implementation:

5 Chapter We can write the OR logical expression ( + ) using double negation as + = + = From this logical expression, we can derive the following implementation: 2 7 The two transistors are in series. V out is low only when both transistors are turned on. This happens only when both V in and V in2 are high as shown below: V in V in2 V out low low high low high high high low high high high low s in the text, when we interpret low as and high as, it implements the NND function. 2 8 In this example, the two transistors are in parallel. V out is low when any of the two transistors are turned on. This happens when either V in or V in2 (or both) is high as shown below: V in V in2 V out low low high low high low high low low high high low s in the text, when we interpret low as and high as, it implements the NOR function. 2 9 We assume that input has 5% weight. The truth table is shown below:

6 6 Chapter 2 C F We use the Karnaugh map to derive the simplified logical expression. C C From this K-map, we get the following logical expression: +C The following logic circuit implements this function: C 2 We assume that input has the veto power. The truth table is shown below: C F

7 Chapter 2 7 The sum-of-products expression for F can be simplified by replicating the term ( C) as shown below: F = C + C + C = C + C + C + C = C + = ( +C) You can also use the Karnaugh map method to derive the same logical expression. The following logic circuit implements this function: C 2 (a) x x = x Let us start with x and show that it is equivalent to x x. x = x (Identity) = x (x + x) (Complement) = (x x) + (x x) (Distribution) = (x x) + (Complement) = x x (Identity) (b) x + x = x Let us start with x and show that it is equivalent to x + x (very similar to the last exercise). x = x + (Identity) = x +(x x) (Complement) = (x + x) (x + x) (Distribution) = (x + x) (Complement) = x + x (Identity) (c) x = s in the previous examples, we start with the right hand side () and show that it is equivalent to

8 8 Chapter 2 x. (d) x + = This is the dual of the last exercise. = x x (Complement) = x (x + ) (Identity) = (x x) + (x ) (Distribution) = + (x ) (Complement) = x (Identity) = x + x (Complement) = x + (x ) (Identity) = (x + x) (x + ) (Distribution) = (x + ) (Complement) = x + (Identity) 2 2 We have to show (x y) (x + y) = and (x y) + (x + y) =. (x y) (x +y) = xyx + xyy = + = (x y) + (x +y) = xy + x(y + y) + y(x + x) = xy + x y + x y + y x + y x = (x y + x y) + (x y + y x) = (x y + x y) + (x y + y x) = y + y = 2 3 We have to show (x + y) (x y) = and (x + y) + (x y) =. (x + y) (x y) = x x y + y x y = + =

9 Chapter 2 9 (x + y) + (x y) = x( y + y) + y (x + x) + (x y) = xy + x y+yx + y x + x y = x ( y + y + y) + x(y + y) = x + x = 2 4 ND version: C= + + C The truth table below verifies the ND version. C C + + C OR version: + + C= C The truth table below verifies the OR version. C + + C C 2 5 From the 3-input NND gate shown in Figure 2.23b, we can see that each additional input needs an inverter and a 2-input NND gate. Since we implement the inverter with a 2-input NND gate as well, we need two 2-input NND gates for each additional input. Thus, for an n input NND gate, we need +2(n 2)

10 Chapter 2 2-input NND gates. To build an 8-input NND gate we need +2(8 2)=3gates Since there are four gates in the 74 chip, we need four 74 chips. 2 6 (a) (x +y) (x +y) = (x y) x y (de Morgon s law) = (b) x + yx = x ( + y) + yx = x + xy + yx = x + y (x + x) = x + y (c) = ( + ) ( + ) = = Truth table: C F Sum-of-products form: C + C + C + C Product-of-sums form: ( + + C) ( + + C) ( + + C) ( + + C)

11 Chapter We start with the product-of-sums expression and derive the sum-of-products expression. ( + + C) ( + + C) ( + + C) ( + + C) =( + +C+ + C+ C+ C) ( + + C) (++C) =( C+ C++ C+ C+ C+C+ C) (++C) = C + C + C + C 2 9 Logic expression for Figure 2.a is ( ). Logic expression for Figure 2.b is +. We show that this expression is equivalent to ( ). + = (de Morgon s law) 2 2 We start with the product-of-sum expression and derive the other expression. ( + + C) ( + + C) ( + + C) ( + + C) =( + + C+ + C+ C+ C) ( + +C) (+ + C) =( + + C+ C+ C+C+ + C + C+C)(+ + C) = C + + C + C + C + C + C y observing that + C + C + C is equivalent to ( C), we derive the sum-ofproducts expression. 2 2 We start with the product-of-sums expression and derive the sum-of-products expression. ( + + C) ( + + C) ( + + C) ( + + C) =( + + C++ C+C+ C) (+ + C) ( ++C) =( C+ C + + C+ C+C+ C+ C) ( ++C) = C + C + C + C 2 22 Replace the exercise in the book by the following: Using oolean algebra show that the following two expressions are equivalent: C + C D + C + D + C + C + CD + D + C D + C + CD

12 2 Chapter 2 Solution: C + C + C D + C + D + C + CD = C( + ) + C D + C + D + C + CD =( C + C) + C D + C + D + CD = + C D + ( + C D) + C + ( + C) + D + ( + D) + CD + ( + CD) = + C D + C + D + CD 2 23 The logic circuit is shown below: 2 24 We need a 7-input XOR gate to derive the parity bit. We can construct 7-input XOR using 2-input XOR gates as shown below: P We need to add an inverter at the output to generate odd parity bit.

13 Chapter D + C D + D = D( + C) + C D ( + ) + D = D + D C + C D + C D + D = D + C(D + D) + D( + C) = D + C + D 2 26 The truth table is shown below: C F C + C + C + C = C( + ) + C( + ) = C( + ) = C Clearly, we just need one inverter to implement this simplified logical expression The truth table is shown below:

14 4 Chapter 2 From the following Karnaugh map C D F CD C D we get the simplified logical expression as (C D). We just need a single NOR gate to implement this The following table finds the prime implicants: Column Column 2 Column 3 C D p C D p C D C D p C D p C D p C D p C D p C D p

15 Chapter 2 5 There is no need for Step 2. The simplified expression is C D The truth table is shown below: C D F From the following Karnaugh map CD we derive the simplified expression as D + C + D + C = (C + D) + (C + D) The following circuit implements this logic expression:

16 6 Chapter 2 C D C D 2 3 The following table finds the prime implicants: Column Column 2 D C D p C C D p D CD p C C D p C D p CD p Step 2: Prime implicants D C D C Input product terms C D C D CD C D C D CD N N N N

17 Chapter 2 7 The minimal expression is D + C + D + C = (C + D) + (C + D) 2 3 The truth table is shown below: C D F From the following Karnaugh map CD we derive the following simplified logic expression: C D + CD + C + D = C ( D + D) + C + D n implementation of this logic expression is shown below:

18 8 Chapter 2 C D D C 2 32 The following table finds the prime implicants: Column Column 2 C D C C D C D p D C D p CD p CD CD p Step 2: Prime implicants Input product terms C D C D C D C D CD CD C C D D C D CD N N N N

19 Chapter 2 9 We derive the following simplified logic expression: C D + CD + C + D = C ( D + D) + C + D