Digital Fundamentals
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1 Digital Fundamentals Tenth Edition Floyd hapter Pearson Education, Upper 2008 Pearson Saddle River, Education NJ ll Rights Reserved
2 Summary ombinational Logic ircuits In Sum-of-Products (SOP) form, basic combinational circuits can be directly implemented with ND-OR combinations if the necessary complement terms are available. D J K D JK Product terms + D JK Sum-of-products Product term 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
3 Summary ombinational Logic ircuits n example of an SOP implementation is shown. The SOP expression is an ND-OR combination of the input variables and the appropriate complements. D E DE X = + DE SOP 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
4 Summary ombinational Logic ircuits When the output of a SOP form is inverted, the circuit is called an ND-OR-Invert circuit. The OI configuration lends itself to product-of-sums (POS) implementation. n example of an OI implementation is shown. The output expression can be changed to a POS expression by applying DeMorgan s theorem twice. X = + DE X = + DE OI D E DE X = ()(DE) DeMorgan X = ( + + )(D + E) POS 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
5 Summary Exclusive-OR Logic The truth table for an exclusive-or gate is Notice that the output is HIGH whenever and disagree. The oolean expression is X = + The circuit can be drawn as Symbols: Inputs Output X X = 1 Distinctive shape Rectangular outline 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
6 Summary Exclusive-NOR Logic The truth table for an exclusive-nor gate is Notice that the output is HIGH whenever and agree. The oolean expression is X = + The circuit can be drawn as X Symbols: Inputs Output X = 1 Distinctive shape Rectangular outline 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
7 Summary For each circuit, determine if the LED should be on or off V +5.0 V 330 W LED +5.0 V +5.0 V 330 W LED +5.0 V +5.0 V 330 W LED (a) (b) (c) ircuit (a): XOR, inputs agree, output is LOW, LED is ON. ircuit (b): XNOR, inputs disagree, output is LOW, LED is ON. ircuit (c): XOR, inputs disagree, output is HIGH, LED is OFF Pearson Education, Upper Saddle River, NJ ll Rights Reserved
8 Summary Implementing ombinational Logic Implementing a SOP expression is done by first forming the ND terms; then the terms are ORed together. Show the circuit that will implement the oolean expression X = + D + DE. (ssume that the variables and their complements are available.) Start by forming the terms using three 3-input ND gates. Then combine the three terms using a 3-input OR gate. D D E X = + D + DE 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
9 Summary Karnaugh Map Implementation For basic combinational logic circuits, the Karnaugh map can be read and the circuit drawn as a minimum SOP. Karnaugh map is drawn from a truth table. Read the minimum SOP expression and draw the circuit. changes across this boundary Group the 1 s into two overlapping groups as indicated. 2. Read each group by eliminating any variable that changes across a boundary. 3. The vertical group is read. changes across this boundary 4. The horizontal group is read. The circuit is on the next slide: 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
10 Summary continued ircuit: X = + The result is shown as a sum of products. It is a simple matter to implement this form using only NND gates as shown in the text and following example Pearson Education, Upper Saddle River, NJ ll Rights Reserved
11 Summary NND Logic onvert the circuit in the previous example to one that uses only NND gates. Recall from oolean algebra that double inversion cancels. y adding inverting bubbles to above circuit, it is easily converted to NND gates: X = Pearson Education, Upper Saddle River, NJ ll Rights Reserved
12 Universal Gates Summary NND gates are sometimes called universal gates because they can be used to produce the other basic oolean functions. Inverter ND gate + + OR gate NOR gate 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
13 Universal Gates Summary NOR gates are also universal gates and can form all of the basic gates. + Inverter OR gate ND gate NND gate 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
14 NND Logic Summary Recall from DeMorgan s theorem that = +. y using equivalent symbols, it is simpler to read the logic of SOP forms. The earlier example shows the idea: X = + The logic is easy to read if you (mentally) cancel the two connected bubbles on a line Pearson Education, Upper Saddle River, NJ ll Rights Reserved
15 NOR Logic Summary lternatively, DeMorgan s theorem can be written as + =. y using equivalent symbols, it is simpler to read the logic of POS forms. For example, X = ( + )( + ) gain, the logic is easy to read if you cancel the two connected bubbles on a line Pearson Education, Upper Saddle River, NJ ll Rights Reserved
16 Pulsed Waveforms Summary For combinational circuits with pulsed inputs, the output can be predicted by developing intermediate outputs and combining the result. For example, the circuit shown can be analyzed at the outputs of the OR gates: D D G 1 G 2 G 3 G 1 G 2 G Pearson Education, Upper Saddle River, NJ ll Rights Reserved
17 Summary Pulsed Waveforms lternatively, you can develop the truth table for the circuit and enter 0 s and 1 s on the waveforms. Then read the output from the table. D D G 3 G 1 G 2 G Inputs D Output X Pearson Education, Upper Saddle River, NJ ll Rights Reserved
18 Selected Key Terms Universal gate Negative-OR Negative-ND Either a NND or a NOR gate. The term universal refers to a property of a gate that permits any logic function to be implemented by that gate or by a combination of gates of that kind. The dual operation of a NND gate when the inputs are active-low. The dual operation of a NOR gate when the inputs are active-low Pearson Education, Upper Saddle River, NJ ll Rights Reserved
19 1. ssume an OI expression is + D. The equivalent POS expression is a. ( + )( + D) b. ( + )( + D) c. ( + )( + D) d. none of the above 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
20 2. The truth table shown is for a. a NND gate b. a NOR gate c. an exclusive-or gate d. an exclusive-nor gate Inputs Output X Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
21 3. n LED that should be ON is a. LED-1 b. LED V +5.0 V 330 W LED-1 c. neither d. both +5.0 V +5.0 V 330 W LED Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
22 4. To implement the SOP expression X = + D + DE, the type of gate that is needed is a a. 3-input ND gate b. 3-input NND gate c. 3-input OR gate d. 3-input NOR gate D D E 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
23 5. Reading the Karnaugh map, the logic expression is a. + b. + c. + d Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
24 6. The circuit shown will have identical logic out if all gates are changed to a. ND gates b. OR gates c. NND gates d. NOR gates D 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
25 7. The two types of gates which are called universal gates are a. ND/OR b. NND/NOR c. ND/NND d. OR/NOR 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
26 8. The circuit shown is equivalent to an a. ND gate b. XOR gate c. OR gate d. none of the above 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
27 9. The circuit shown is equivalent to a. an ND gate b. an XOR gate c. an OR gate d. none of the above 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
28 10. During the first three intervals for the pulsed circuit shown, the output of a. G 1 is LOW and G 2 is LOW b. G 1 is LOW and G 2 is HIGH c. G 1 is HIGH and G 2 is LOW d. G 1 is HIGH and G 2 is HIGH D D G 1 G 2 G Pearson Education, Upper Saddle River, NJ ll Rights Reserved 2008 Pearson Education
29 nswers: 1. b 6. c 2. d 7. b 3. a 8. c 4. c 9. a 5. d 10. c 2009 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
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