Resistance. R = ρ t l w ohms where ρ = resistivity, t = thickness, l = conductor length, w = conductor width. Also can use. l w. R = R s.

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1 Resistance R = ρ t l w ohms where ρ = resistivity, t = thickness, l = conductor lenth, w = conductor width Also can use where R = R s l w R s = sheet resistance (Ω/sq.) Independence from l w "square": is obtained by measurin sheet resistance by the w w w t t l l 1 rectanular block R = Rs(l/w) [Ω] l 4 rectanular blocks R = Rs(2l/2w) = Rs(l/w) [Ω]

2 Typical sheet resistances for conductors: SHEET RESISTANE [Ω/SQUARE] Material Min. Typical Max. Intermetal (metal1-metal2) Top-metal Polysilicon Silicide Diffusion (n +,p + ) Silicided diffusion n-well 1k 2k 5k

3 Delay on wire distributed R line R First-order approximation: delay = r c l 2 2 where r = resistance per unit lenth c = capacitance per unit lenth l = lenth of the wire Important fact interconnect delay does not scale with lambda, it is constant. When lambda decreases, R increases and decreases, resultin in delay constant Insertin a buffer in a lon resistance line can be advantaeous. For a poly run = 2mm lenth, r = 20 Ω/µm c = pf/µm 2mm delay = = 16 ns If broken into two 1mm sections, then delay of each section = 4ns. Add a buffer with delay = 1ns and total delay becomes = 9ns.

4 Typically, resistive effects of interconnect much more important than capacitive effects since capacitance tends to be dominated by the ate capacitances. oad Driver oad oad Resistance/apacitance of interconnect apacitance of MOSFET load MOSFET load capacitance >> wire capacitance [unless DSM (deep submicron ( 0.25µm) MOS technoloy] So, if we decrease interconnect resistance, then we reduce overall propaation delay between driver and load. Reduce interconnect resistance by usin metal, increasin the width of the interconnect. Usually just want delay (R), where R is the resistance of the interconnect and is the total of all the capacitive loads.

5 Stae Ratio - Delay Optimization To drive a lare load, do not just want to make one lare driver lare transistors represent a lare load back to internal circuitry load lare driver (lare transistors) Want to drive the load with a series of proressively larer drivers 1 a a 2 a N inv-1 inv-2 inv-3 inv-n load 1 minimum sized inverter 2 N n staes (number of inverters = n) Each driver (inverter) larer than precedin driver by stae ratio "a". et be ate load of first driver which is minimum size. Then, N will be a N and want a n, [Note: n = N + 1]

6 to uarantee that none of capacitances internal to the chain of inverters exceed load. For example, if N load, why we would need the n-th inverter at all! So when the condition a n is set equal we have a n =. Question: What value of "a" will lead to minimum delay? What value of "n"? If we find one, we can compute the other. Delay throuh each stae is approximately a t d where t d is the delay throuh a minimum-sized inverter drivin another minimum-sized inverter. Total Delay = n a t d We know a n =, so a = 1/n Substitutin, Total Delay = n 1/n t d To find optimum value for n, differentiate and set equal to zero. If we do, then we find

7 n opt = ln Once we know nopt, find a opt a n = a ln ( ) = Take the natural lo (i.e., ln) of both sides: ln ln(a) = ln ln(a) = 1 a = e A more detailed analysis shows that the intrinsic output capacitance of the inverter will affect this ratio. k + a opt a opt = exp a opt where k = drain ate.

8 External onditions which can affect delay a) Operatin Temperature b) Supply Voltae c) Process Variation Drain current is proportional to T ( 1.5) As temperature is increased, drain current is reduced for a iven set of operatin conditions, delay increases The temperature of the die is what counts, this is expressed as T j = T a + θ ja P d where T a ambient Temperature ( ) θ ja packae thermal impedance ( /watt) P d power dissipation Typical values for θ ja rane from 35 to 45 ( /watt), dependin on chip packae Packae Type Pin ount θ ja still air θ ja 300 ft/min. Units Plastic J-eaded hip arrier /W /W /W Plastic Quad Flatpack /W Very Thin (1.0mm) Quad Flatpack /W eramic Pin Grid Array /W eramic Quad Flatpack /W

9 Parts usually characterized for different temperature ranes: ommercial: Industrial Military 0 to to to 125 Voltae also affects device speed: voltae increases, drain current increases, delay decreases Typically characterize device around a power supply tolerance Power Supply Voltae Tolerance ommercial ± 5% Industrial ± 10% Military ± 10% Process Variations also affect delay wafer fabrication is a lon series of chemical operations, variations in diffusion depth, dopant densities, oxide/diffusion eometry variations can cause transistor switchin speeds to vary from wafer batch to wafer batch, wafer to wafer and even on the same wafer.

10 Transistors typically characterized as "fast", "nominal", and "slow". Need SPIE transistor models for these cases. However, variations between nmos-speeds and pmos-speeds can be independent so one can obtain "four corners" model slow nmos fast pmos fast nmos fast pmos slow nmos slow pmos fast nmos slow pmos When characterizin for hih speed, also want to use lowest temperature, hihest voltae. When characterizin for "slow" case, want hihest temperature, lowest voltae. MOS Diital Systems hecks (ommercial) PROESS TEMPERATURE VOTAGE TESTS Fast-n / fast-p 0 5.5V (3.6V) Power dissipation (D), clock races Slow-n / slow-p V (3.0V) ircuit speed, external setup and hold times Slow-n / fast-p 0 5.5V (3.6V) Pseudo-nMOS noise marin, level shifters, memory write/read, ratioed circuits Fast-n / slow-p 0 5.5V (3.6V) Memories, ratioed circuits, level shifters

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12 Power Dissipation Power Dissipation has three components: 1. Static 2. Dynamic 3. Short ircuit For traditional MOS desin, static dissipation is limited to the leakae currents in the reversed-biased diodes formed between the substrate (or well) and source/drain reions. But in some DSM MOS technoloy subthreshold leakae tends to also contribute sinificant static dissipation. Subthreshold leakae increases exponentially as threshold voltae decreases; i.e., lower V T (V Tn and V Tp ) MOS technoloy has more static power dissipation (due to subthreshold leakae) than hiher V T technoloy. Static power dissipation can be extremely small: 1 5V 1 to 2 nanowatts static power Dynamic Power is overned by P d = f p V DD 2 This is the amount of power dissipated by charin/discharin internal capacitance and load capacitance. Note the relations: Hiher the switchin speed P d ower the voltae P d! the Bier the ates P d

13 To estimate P d, need to know the switchin frequencies of the internal sinals Typically break this into two parts: P d = ( P d ) clock network + ( P d ) all the rest The power dissipation in the clock network tends to dominate in most desins. Usually assume the switchin frequency of loic sinals as some fraction of the clock frequency, can estimate by runnin some sample simulations and keepin switchin statistics on internal nodes to build a probabilistic model of switchin activity. oic synthesis techniques can be used to do the followin: or and/or a. minimize # of ates b. maximize speed c. minimize switchin activity Also, have "short-circuit" power dissipation proportional to the amount of time when both p- and n-trees are conductin. Slow rise/fall times on nodes can make this sinificant. Usually inored in most calculations.

14 Sizin Routin alculation The sizin of sinal lines to achieve a particular R delay was previously discussed. For power conductors, need to worry about 1. Metal miration - too much current in too small a conductor will "blow" the conductor 2. Ground Bounce - lare current spikes in V DD /GND leads can occur when simultaneous outputs switch Two components to round bounce. a. IR for on-chip conductors, R is resistance of on-chip conductor di b. dt is the on-chip inductance and packae inductance in V DD /GND pins. Packae inductance dominates. Note that di dt is affected by slew rates on input/output pins.

15 Example What would be the conductor width of power and round wires to a 50MHz clock buffer that drives 100pF of on-chip load to satisfy the metalmiration consideration (J A = 0.5mA/µm)? What is the round bounce with chosen conductor size? The module is 500µm from both the power and round pads and the supply voltae is 5 volts P = ƒv DD = = 125mW I = P/V = 25mA Thus the width of the clock wires should be at least 50µm. A ood choice would be 100µm. 2. R = 500/ = 5 squares 0.05 Ω/sq. = 0.25Ω IR = = 6.25mV Typically, IR term of round bounce very small compared to di dt term.