# CMOS Differential Amplifier

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 MOS Differential Amplifier. urrent Equations of Differential Amplifier DD D D (7 D ( E D / G G GS GS G (0 E D / ( G (a (b Fiure. General MOS Differential Amplifier: (a Schematic Diaram, (b nput Gate oltaes mplementation. Fiure (a shows the schematic diaram of a typical differential amplifier. The differential input is iven by: ( ( ( D G G GS GS D ( ( D D GS GS GS TN GS TN ( The commonmode input sinal is iven by: G G ( The input voltaes in term of D and are iven by / (4 G D G / (5 D

2 Fiure (b shows the implementation of the ate voltaes in terms of the differential and common mode voltaes. ts PSpice implementation usin voltae controlled voltae source is iven below: D 7 0 D 0 E E D 0 Two special cases of input ate sinals are of interests : pure differential and pure common mode input sinals. Pure differential input sinals mean 0, from equation (4 and (5; G G D / D / This case is of interest when studyin the differential ain of differential amplifier, see Fiure (a. Pure commonmode input sinals mean D 0, from equation (4 and (5; G G This case is of interest when studyin the commonmode ain of differential amplifier, see Fiure 5(a. Assume both transistor drivers are matched, that is: D D D (6 / (7 D D The transistor currents satisfy the followin equations: D D D (8 OD (9 D D ( / (0 D OD D ( / ( OD Substitutin Eq(0 and Eq( to Eq(7 ( / ( / ( / D OD OD

3 Normalizin by D ( OD OD ( To simplify the equation, let x D, and y OD (4 The equation reduces to: x y y Solve for y, x ( y ( y( y ( y y x y 4 x y x 4 x y x ( 4 The result is: y x x 4 x, provided (5 Substitutin for x and y, one obtains OD D D (6 4 OD D 4 D (7 4 D D 4 D (8 4

4 D D 4 D, provided D (9 4. Low Frequency Small Sinal Equivalent ircuit With Pure Differential nput Sinal ( DD M w5.8u l5.4u (5 M4 w5.8u l5.4u D / O D M D4 w9.6u M D (6 l5.4u D w9.6u G l5.4u G ( ( GS GS D / O (4 (a S S4 m ds v s4 D D4 D D m (v id / S dsds S m (v id / (b 4

5 Fiure. Differential Amplifier mplementation: (a Differential Amplifier with PMOS current mirror load, (b Small Sinal Equivalent ircuit for Purely Differential nput Sinal. An active load acts as a current source. Thus it must be biased such that their currents add up exactly to. n practice this is quite difficult. Thus a feedback circuit is required to ensure this equality. This is achieved by usin a current mirror circuit as load, as in Fiure. The current mirror consists of transistor M and M4. One transistor (M is always connected as diode and drives the other transistor (M4. Since GS GS4, if both transistors have the same, then the current D is mirrored to D4, i.e., D D4. The advantae of this confiuration is that the differential output sinal is converted to a sinle ended output sinal with no extra components required. n this circuit, the output voltae or current is taken from the drains of M and M4. The operation of this circuit is as follows. f a differential voltae, D G G, is applied between the ates, then half is applied to the atesource of M and half to the atesource of M. The result is to increase D and decrease D by equal increment,. The increase D is mirrored throuh MM4 as an increase in D4 of. As a consequence of the increase in D4 and the decrease in D, the output must sink a current of. The sum of the chanes in D and D at the common node is zero. That is, the node is at an ac round, see Fiure (b. From Eq(4 and Eq(5 for pure differential input sinal means the commonmode sinal is zero. That is, the input sinals are G D / and G D /. This is shown in Fiure (a. The transconductance of the differential amplifier is iven by: O md D D D / s m That is, the differential amplifier has the same transconductance as a sinle stae common source amplifier. 5

6 G v id / D m (v id / ds DGG4 v s ds m v s4 D m (v id / D4 v s4 ds v o S S (a S S4 G v id / S D D4 m (v id / ds S S4 (b v o G D D4 v id S m v id ds S S4 (c v o Fiure. Differential Amplifier Operatin in Purely Differential nput Sinal: (a Oriinal Equivalent ircuit, (b Reduction to Twoport Network, and (c hanin nput Port ariable to id. The derivation of the small sinal equivalent circuit is shown in Fiure. The simplification is based on the symmetry of the circuit. n Fiure (b, each transistor equivalent circuit is drawn. Fiure (a redraws the equivalent circuit in Fiure (b in a form suitable for twoport analysis. The further reduction is obtained after the twoport parameters are obtained. From Fiure (a, the followin twoport variables and load are obtained. L and 0 D O / The port current equations are derived to obtain the parameters: 0 (0 ( m s4 ( ds 6

7 m ( s4 ds ds m Substitute eq( to eq( m ( m m ds ds ( m ds ds m ds m m ( ( ds ds ( assumin >> m m m The resultin parameter matrix is: m ds ds 0 m ds 0 The dc voltae ain is, A D0 id O / y y L m ds nstead of half differential input, dc ain with respect to full differential input is desired. That is, A DO O m m (4 id ds ds 7

8 ( DD M w5.8u l5.4u (5 M4 w5.8u l5.4u O B0uA D (6 D4 M D D M w9.6u w9.6u l5.4u l5.4u G ( ( G o GS (8 GS (9 0uA M6 w.6u l.u M5 w.6u l.u (4 Fiure 4. The omplete Differential Amplifier Schematic Diaram Fiure (c is the resultin twoport equivalent circuit. Except for the polarity this ain equation is identical to that of the sinle NMOS inverter with PMOS current load. Fiure 4 shows the complete differential amplifier implemented usin a pair of inverter amplifier with PMOS current load, and 00uA current souce. The PSpice netlist is iven below: * Filename"diffvid.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D D 7 0 D 0 A E E D 0.65 DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W.6U L.U B 9 0UA.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 8

9 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.D D TF (6 D.PROBE.END The operatin point current is determined by the source current, which is split between the two PMOS current loaded inverters. DSQ DSQ /, and similarly DSQ DSQ4 /. For the iven differential amplifier 0uA. The voltae ain is computed as follows: N P N P4 K K N P (W (W N P / L / L P N (40E 6(9.6u/(5.4u * 0.5u (5E 6(5.8u/(5.4u * 0.5u 87.uA/ 87.95uA/ m m N DSQ (87.E 6(0E umho m P DSQ (87.95E 6(0E 6 9. umho ds λ λ λ DS DS4 DS5 DSQ DSQ4 DSQ λ λ λ P N P DSQ DSQ DSQ5.0(0E 6. umho.0(0e 6. umho.0(0e umho A m 8.59E 6.E 6.E 6 D ds.5 9

10 The low frequency input resistance Rin. The output resistance Rout /( ds /(.E6.E6.7M, see Fiure (d, and the computation above. These calculations aree well with Pspice simulation results of: **** SMALLSGNAL HARATERSTS (6/D.47E0 NPUT RETANE AT D.000E0 OUTPUT RETANE AT (6.4E05. Determination of the input commonmode rane 0

11 DD s s4 SD M M4 SD4 DG G M M G GS GS o GG M5 DS5 S S4 m ds v s4 D D4 D D m v s dsds m v s o S S Fiure 5. Differential Amplifier with Purely ommonmode nput Sinal: (a Schematic Diaram, and (b Small Sinal Equivalent ircuit. The input commonmode rane is the rane of commonmode voltae ic G G in which all the transistors are operatin in saturation reion. To determine this a purely commonmode input is applied at both inputs, see Fiure 5.. Maximum G or G Determination As G approaches DD transistor M and M o into the triode reion. G (max is the value of the input when it occurs. This can be determined from Fiure 5 by writin the KL equation from DD toward G.

12 G DD DD SD SG DG DG, since D G DS SG ( GS TP TP P TP G DD DS P TP DG From Fiure 5(a, DG can be determined in term of the commonly known transistor voltaes of M. or DG DS DS GS GS DG Transistor M is on saturation when the followin condition holds. GS That is, TN TN DG DS GS DG The minimum value of DG is achieved when transistor M is on the threshold of saturation. That is, TN DG The maximum input voltae is obtained when TN DG. That is, G (max DD DD DS P DS P DD TP TN P (5 Assumin TP TN.. Minimum G or G Determination

13 As G approaches, M becomes cutoff. The minimum input voltae G is determined when M5 is no loner in saturation. This is obtained by writin the KL equation from to G. G DS5 GS Transistor M5 is on saturation when, GS5 TN5 DS5 M5 is at vere of saturation when, GS5 TN5 DS5 DS5(SAT That is, the minimum input voltae occurs when,. G DS5(SAT GS GS5 TN5 DS5(SAT (min (6 (min ( G GS5 TN5 GS G (min GG GG ( GG TN5 DS N DS N GG TN5 ( TN N GS TN TN (7 norin the bulk bias effect. Usin the SPE parameters for the differential amplifier implemented in Fiure 4. From Eq(5, (max G P P DD K (W / L P (5E 6(5.8u/(5.4u *0.5u ua/ 0E 6 G (max E 6 and from Eq(7, 0E 6 G (min GG N To uarantee that the differential amplifier stays on the linear reion of operation, set commonmode sinal at half way the commonmode rane. That is, [ G (max G (min]/[0.9.8]/ Low Frequency Small Sinal Equivalent ircuit With Pure ommonmode nput Sinal

14 ic G v s D DGG4 D D4 v s v s4 m v s m v s ds v S D5 c S o ds ds m v s4 S S5 S4 (a ic G v s D DGG4 D D4 v s ds ds m m v s m v s ds S D5 c S v o S S5 S4 (b G D D ic s m v s S D5 ds ds L ds m v o S5 S Fiure 6. Small Sinal Equivalent ircuit: (a Oriinal Small Sinal Equivalent ircuit, (b Accountin for Source alues and Polarities, and (c Twoport onversions. Fiure 5(a shows the schematic when a purely commonmode input is applied at both inputs that is, G G. f increases both D and D increases. Their sum at the common node also increases. Fiure 5(b shows that is not at ac round, unlike the pure differential input sinal case shown in Fiure (b. Due to sinal symmetry when both inputs are the same, DS DS4. Since both G and S of M and M4 are connected to each other, means GS GS4. M is diode connected with G and D connected, means GS DS. From these expressions, DS4 GS4 can be deduced. That is the voltae (c 4

15 across D and S of M4 can be labelled as GS4, see Fiure 6(a. The current source of M4 is therefore reduced to conductance, see Fiure 6(b. Since DS DS4, the D and D4 can be connected toether. Fiure 6(c shows the final equivalent circuit after combinin all components that are in parallel. L and From Fiure 6(c, the followin twoport variables and load are obtained. ds assumin O ds m m ds The twoport current equations are derived to obtain the parameters. 0 ( ds m ds m ds ( ds ( m ds ( ds ds ds m m ( ( ds ds ds ds ( ds m ( ds ds m m ds m The parameter matrix is: 0 m ds ds m 0 m ds m assumin ds ds m ds ds 0 ds ( ds ds 0 m ds m The dc commonmode voltae ain is, 5

16 A 0 y y ds m ds assumin ( m L >> m m ds ds. ds ds ds m m m ds ( ds m m ( m m r m m ds m m r m m m r m * Filename"diffvic.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D 7 0 D 0 E E D 0 DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W00.8U L.6U M7 9 9 PMOS W.6U L.6U.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.OP.D TF (6.PROBE.END 6

17 A O r m (9.E 6(.7E This is very closed to the PSpice simulation result. **** SMALLSGNAL HARATERSTS 7

18 (6/.459E0 NPUT RETANE AT.000E0 OUTPUT RETANE AT (6.86E05 The oal of differential amplifier is to amplify the difference sinal and to reject commonmode sinal. A fiure of merit called commonmode rejection ration (MRR is defined as: MRR A A D Differential Gain Frequency Response 8

19 DD M s s4 M4 db db4 d4 G d GS M db db M GS d G L (a DD M M4 d db db s s4 d db db4 L d4 (5 (6 ( ( G M M (8 GS GS G (b Fiure 7. Parasitic apacitances of Differential Amplifier Operatin in Purely Differential nput Sinal: (a Parasitic apacitances of each Transistor, (b Lumped Parasitic apacitances. Fiure 7(a shows all the parasitic capacitances of the differential amplifier with purely differential input sinals. Since both inputs are voltae sources, they are at ac round when considerin the effects of ate capacitances. Fiure 7(b shows that there are basically three capacitances. These are: d d d4 db db db db4 s L s4 9

20 G v id / D DGG4 S m (v id / S ds ds m D D4 m (v id / v s4 S S4 ds v o d db db s s4 d db db4 L d4 (a G D DGG4 D D4 id / s4 O m (v id / m (v id / v s4 S S S S4 (b m m Fiure 8. Hih Frequency Small Sinal Equivalent ircuit: (a Small Sinal Equivalent ircuit Showin Lumped apacitances, (b Small Sinal Equivalent ircuit ombinin apacitance and Resistance to Admittance. NOTE is not a miller capacitance, it is connected between the outputs of the two inverter amplifiers, and not between an output and an input terminals of an amplifier. in this case is normally small and can be inored. Fiure 8(b shows that the three admittances are iven by: ds ds s ds s d4 m s s The twoport parameters are to be determined. Fiure 8(b shows that the twoport variables are: 0 L / and id O 0

21 m m m m m m s4 s4 s4 m s4 s4 s4 m s4 m s4 m s4 ( ( ( Solve for 0 ( 0 ( At node D ( ( ( 0 The parameter matrix is: m m m 0 0 For differential amplifier the assumption that or is approximately 0 is valid. That is, m m 0 0 The differential ain is iven by:

22 A D m y y ( ( ds ds m m ds ds L ds m s m m s ( ds ds m s ds ds m ( ds ds m s s ds ds m ds s s ds ds ds ( ds m ds m ( m( m ds s ds ds m m s s ( s ds ds The differential ain when the input voltae is chaned to D is: A p p D A where : z ds O id DO ds ds p << p << z s m ds s ds s ( z s s ( ( p p ds ds m m m m ds ds ds m m s ds NOTE the differential voltae ain has polezero doublets. That is, the zero z is double that of the nondominant pole p. The dominant (lowest frequency pole p occurs at the output node. The above transfer function can also be obtained by notin that each pole correspond to a node in the differential amplifier.

23 Each node is at a finite impedance with respect to round. That is, each node there is a resistance R n (or conductance and capacitance n to round. To determine which poles are dominant (or more sinificant, the impedance levels must be monitored. The parasitic capacitances n are of approximately the same manitude, but R n usually vary considerably. When the resistance (conductance is hih (low, a dominant pole is enerated. The impedance levels are summarized in the follwin table: Node(From Netlist Resistance apacitance Pole 0 (ac round X 0 (ac round X 5 R 5 /( ds ds m p /(R 5 * 6 R 6 /( ds p /(R (ac round X The derivation shows that the pole p create a zero doublet. * Filename"diffreq.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D D 7 0 D 0 A E E D 0.65 DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W00.8U L.6U M7 9 9 PMOS W.6U L.6U.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.A DE 00 HZ 00000GHZ.PROBE.END

24 6. ommonmode Frequency Response 4

25 DD M M4 G M M G sb sb GS GS o d5 GG M5 db5 DD M M4 G M M G GS GS o GG M5 S S sb sb db5 d5 Fiure 9. Differential Amplifier Operatin in Pure ommonmode nput Sinal: (a All Parasitic apacitances at ommon Node c, (b Total apacitances Across the Drain and Source of M5. From the expression of the dc commonmode ain, it is primarily a function of m and r. The first order frequency response analysis can be simplified by inorin all parasitic capacitances except the capacitance S across r, see Fiure 9. That is r is replaced by z in the the commonmode ain expression to account for frequency dependency. 5

26 z A where : S (r z sb r //S sr m sb db5 m S r sr d5 S ( sr r m S * Filename"diffreqc.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D 7 0 D 0 E E D 0.65 A DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W00.8U L.6U M7 9 9 PMOS W.6U L.6U.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.A DE 00 HZ 00000GHZ.PROBE.END 6

27 The differentialmode voltae ain decreases with increasin frequency but commonmode voltae increases. Therefore, MRR decreases with increasin frequency. 7. Desinin Differential Amplifier With Specified MR Given a commonmode rane of 0.75 < <0.75, GG, DS5 00uA, L min 5.4u, 0.5. Determine the size of each transistor in the differential amplifier circuit, see Fiure 4. GS TN. Determine the (W/L 5 to sink 00uA. DS5 W L 5 K N5 ( N GS5 ( GS5 DS5 TN5 K K (00E 6 (40E 6[ (.5 ] TN5 N W L N ( 5 GG ( GS5 DS5 08u 0 5.4u TN5 TN5. Determine (W/L (W/L from (min G (min specification From Eq(6, 7

28 GS W L (min 0.75 G W L K N DS5(SAT ( GS DS5(SAT DS 0.75 ( TN GS 0.75 (50E 6 (40E 6(.5 6u u. Determine (W/L(W/L4 from (max G (max specification From Eq(5, W L (max DS P K P ( G ( (max DD DD G DS G (max DD (max K P DS P W L ( DD G (50E 6 (5E 6( (max.75u u The above is simulated usin PSpice. The results aree well with the calculations. * Filename"diffcmr.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D 7 0 D 0 E E D 0 DD 0 D.5OLT 4 0 D.5OLT M NMOS W6U L5.4U M NMOS W6U L5.4U M 5 5 PMOS W.75U L5.4U M4 6 5 PMOS W.75U L5.4U M NMOS W08U L5.4U GG 9 0 D.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.D TF (6.PROBE.END 8

29 9

### CMOS COMPARATOR. 1. Comparator Design Specifications. Figure 1. Comparator Transfer Characteristics.

CMOS COMARATOR. Comparator Design Specifications o OH ( in+ - in- ) OL (a) OH L H ( in+ - in- ) OL (b) OS OH L H ( in+ - in- ) OL (c) Figure. Comparator Transfer Characteristics. A comparator is a circuit

### p-channel MOSFET Models

p-channel MOSFET Models DC drain current in the three operating regions: -I D > 0 I D = 0 A ( V SG V T ) I D = µ p C ox ( W L) [ V SG V Tp ( V SD 2) ]( 1 λ p V SD )V SD ( VSG V Tp, V SD V SG V Tp ) I D

### ECEN474: (Analog) VLSI Circuit Design Fall 2012

ECEN474: (Analo) VLSI Circuit Desin Fall 0 Lecture 9: Output Staes Sam Palermo Analo & Mixed-Sinal Center Texas A&M University Announcements & Aenda Exam 3 is on Friday Nov. 30 Output Staes Source Follower

### CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS

CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS Chapter Outline 10.1 The Two-Stage CMOS Op Amp 10.2 The Folded-Cascode CMOS Op Amp 10.3 The 741 Op-Amp Circuit 10.4 DC Analysis of the 741 10.5 Small-Signal Analysis

### MOSFET transistor I-V characteristics

MOSFET transistor I-V characteristics Linear region: v DS «v GS Triode region: v DS < v GS i D = K[ 2( v GS )v DS ] 2 i D = K[ 2( v GS )v DS v DS ] K n K = = C ox µ n W ----- K 2L n v DS = v GS sat (current)

### Resistance. R = ρ t l w ohms where ρ = resistivity, t = thickness, l = conductor length, w = conductor width. Also can use. l w. R = R s.

Resistance R = ρ t l w ohms where ρ = resistivity, t = thickness, l = conductor lenth, w = conductor width Also can use where R = R s l w R s = sheet resistance (Ω/sq.) Independence from l w "square":

### MOSFET DIFFERENTIAL AMPLIFIER (TWO-WEEK LAB)

page 1 of 7 MOSFET DIFFERENTIAL AMPLIFIER (TWO-WEEK LAB) BACKGROUND The MOSFET is by far the most widely used transistor in both digital and analog circuits, and it is the backbone of modern electronics.

### OPTIMIZATION OF LADDER FILTERS WITH GmC SIMULATION OF FLOATING INDUCTORS

OPTMZATON OF LADDER FLTERS WTH GmC SMULATON OF FLOATNG NDUCTORS Mahmoud Shaktour, Josef Bajer, Dalibor Biolek BUT/UD, Dept. of Microelectronics/EE Udolni 53/Kounicova 65, Brno, Czech Republic dalibor.biolek@unob.cz

### INTRODUCTION TO ANALOG IC DESIGN

in cooperation with participants to 5-day training on INTRODUCTION TO ANALOG IC DESIGN Venue: Microelectronics Laboratory, 2 nd flr., College of Engineering bldg., MSU-Iligan Institute of Technology, Tibanga,

EE539: Analog Integrated Circuit Design; Common mode feedback circuits Nagendra Krishnapura (nagendra@iitm.ac.in) 8 April 2006 v op v on common mode detector v op + v on 2 error amplifier Figure : Principle

### 1. Class-A Source Follower with External Resistor Output Stage

1. Class-A Source Follower with External Resistor utput Stage V (1) (3) M1 VB Vi (5) I SS I DS1 (4) () RL Vo V SS Figure 1. Class A Amplifier Class-A source follower amplifier with external resistor is

### EE-4232 Review of BJTs, JFETs and MOSFETs

EE-4232 Review of BJTs, JFETs and MOSFETs 0 A simplified structure of the npn transistor. 1 A simplified structure of the pnp transistor. 2 Current flow in an npn transistor biased to operate in the active

### Electronic Circuits for Mechatronics ELCT609 Lecture 7: MOS-FET Transistor

Electronic Circuits for Mechatronics ELCT609 Lecture 7: MOS-FET Transistor Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 Introduction Why we call it Transistor? The name came as an

### Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 2

Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 I SD = µ pcox( VSG Vtp)^2(1 + VSDλ) 2 From this equation it is evident that I SD is a function

### MOSFET Small-Signal Model

MOSFET Small-Signal Model Concept: Þnd an equivalent circuit which interrelates the incremental changes in i D, v GS, v DS, etc. Since the changes are small, the small-signal equivalent circuit has linear

### Notes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits

Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure

### Review - Non-linear and Active Loads Maximum gain: A v,max

6.012 Microelectronic Devices and Circuits Lecture 21 DiffAmp Anal. II: Output Stages Outline Announcements DP: Get help before the Thanksgiving break. It's due Friday, Dec. 4 On Stellar: Writeup on the

### 3.4 - BJT DIFFERENTIAL AMPLIFIERS

BJT Differential Amplifiers (6/4/00) Page 1 3.4 BJT DIFFERENTIAL AMPLIFIERS INTRODUCTION Objective The objective of this presentation is: 1.) Define and characterize the differential amplifier.) Show the

### MOSFET DEVICES. If the MOSFET is operating in saturation, then the following conditions are satisfied:

MOSFET DEVICES If the MOSFET is operating in saturation, then the following conditions are satisfied: V V I GS GS D > V T V T K = 2 P = V W L DSAT 2 ( V ) ( 1 + λv ) DSAT < V DS DS + VGS - ID + VDS - The

### Biasing in MOSFET Amplifiers

Biasing in MOSFET Amplifiers Biasing: Creating the circuit to establish the desired DC oltages and currents for the operation of the amplifier Four common ways:. Biasing by fixing GS. Biasing by fixing

### Bipolar Junction Transistors (BJT): Part 4 Small Signal BJT Model. Reading: Jaeger , Notes. ECE Dr. Alan Doolittle

Lecture 20 Bipolar Junction Transistors (BJT): Part 4 Small Signal BJT Model Reading: Jaeger 13.5-13.6, Notes Further Model Simplifications (useful for circuit analysis) Ebers-Moll Forward Active Mode

### Study on Performance Analysis of CMOS RF front-end circuits for 2.4GHz Wireless Applications

Study on Performance Analysis of CMOS RF front-end circuits for 2.4GHz Wireless Applications M.Sumathi, 2 S.Malarvizhi Department of ECE,Sathyabama University,Chennai-9 Department/ECE, SRM University,

### IV. Transistors (Biasing & Small-Signal Model)

IV. Transistors (Biasing & Small-Signal Model) 4.1 Introduction Amplifiers are the main component of any analog circuit. Not only they can amplify the signal, they can be configured into may other useful

### Operational Amplifiers

Operational Amplifiers Introduction The operational amplifier (op-amp) is a voltage controlled voltage source with very high gain. It is a five terminal four port active element. The symbol of the op-amp

### ENEE 307 Electronic Circuit Design Laboratory Spring 2012. A. Iliadis Electrical Engineering Department University of Maryland College Park MD 20742

1.1. Differential Amplifiers ENEE 307 Electronic Circuit Design Laboratory Spring 2012 A. Iliadis Electrical Engineering Department University of Maryland College Park MD 20742 Differential Amplifiers

### Microelectronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements Exam Two Results -

6.012 Microelectronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Exam Two Results Exams will be returned tomorrow (Nov 13). Review Biasing and amplifier metrics

### ELECTRONICS. EE 42/100 Lecture 8: Op-Amps. Rev C 2/8/2012 (9:54 AM) Prof. Ali M. Niknejad

A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 8 p. 1/23 EE 42/100 Lecture 8: Op-Amps ELECTRONICS Rev C 2/8/2012 (9:54 AM) Prof. Ali M. Niknejad University of California, Berkeley

### Design and Layout of Two Stage High Bandwidth Operational Amplifier

Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard

### Transconductance. (Saturated) MOSFET Small-Signal Model. The small-signal drain current due to v gs is therefore given by

11 (Saturated) MOSFET Small-Signal Model Transconductance Concept: find an equivalent circuit which interrelates the incremental changes in i D v GS v DS etc. for the MOSFET in saturation The small-signal

### Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs

The MOSFET Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Assets: High integration density and relatively simple manufacturing

### Chapter 10 Advanced CMOS Circuits

Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in

### Chapter 8 Differential and Multistage Amplifiers. EE 3120 Microelectronics II

1 Chapter 8 Differential and Multistage Amplifiers Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4.

### Lecture 24. MOSFET Basics (Understanding with no math)

Lecture 24 MOSFET Basics (Understanding with no math) Reading: Pierret 17.1-17.2 and Jaeger 4.1-4.10 and Notes Flow of current from Source to Drain is controlled by the Gate voltage. Control by the Gate

### NMOS Digital Circuits. Introduction Static NMOS circuits Dynamic NMOS circuits

NMOS Digital Circuits Introduction Static NMOS circuits Dynamic NMOS circuits Introduction PMOS and NMOS families are based on MOS transistors with induced channel of p, respectively n NMOS circuits mostly

### EEC 118 Spring 2011 Midterm

EEC 118 Spring 2011 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis May 2, 2011 This examination is closed book and closed notes. Some formulas

### Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Introduction to Transistor-Level Logic Circuits Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed state

### LM 358 Op Amp. If you have small signals and need a more useful reading we could amplify it using the op amp, this is commonly used in sensors.

LM 358 Op Amp S k i l l L e v e l : I n t e r m e d i a t e OVERVIEW The LM 358 is a duel single supply operational amplifier. As it is a single supply it eliminates the need for a duel power supply, thus

### An Introduction to the EKV Model and a Comparison of EKV to BSIM

An Introduction to the EKV Model and a Comparison of EKV to BSIM Stephen C. Terry 2. 3.2005 Integrated Circuits & Systems Laboratory 1 Overview Characterizing MOSFET operating regions EKV model fundamentals

### ON THE TUNING PERFORMANCE OF AN ACTIVE RF BANDPASS FILTER

Volume 49, Number 3, 008 ON THE TUNING PERFORMANCE OF AN ACTIVE RF BANDPASS FILTER Cristian ANDRIESEI Liviu GORAŞ Gh. Asachi Technical University, Iaşi 700506 Iasi, Bd. Carol I, No., Phone: (+40 3 7004,

### Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors.

Whites, EE 320 Lecture 30 Page 1 of 8 Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors. There are two different environments in which MOSFET amplifiers are found, (1) discrete circuits and

### IGFET Transistors. Biasing, Gain, Input and Output. James K Beard, Ph.D. Assistant Professor Rowan University

IGFET Transistors Biasing, Gain, Input and Output James K Beard, Ph.D. Assistant Professor Rowan University beard@rowan.edu Table of Contents IGFET Transistors...i Biasing, Gain, Input and Output... i

### EE105 Fall 2014 Microelectronic Devices and Circuits. Operational Amplifier Error Sources: dc Current and Output Range Limitations

EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 Operational Amplifier Error Sources: dc Current and Output Range Limitations dc error

### Design of an Folded Cascode Operational Amplifier in High Voltage CMOS Technology

Institute of Integrated Sensor Systems Dept. of Electrical Engineering and Information Technology Design of an Folded Cascode Operational Amplifier in High Voltage CMOS Technology Benjamin LUTGEN Wintersemester

### Objectives The purpose of this lab is build and analyze Differential amplifiers based on NPN transistors (or NMOS transistors).

1 Lab 03: Differential Amplifiers (BJT) (20 points) NOTE: 1) Please use the basic current mirror from Lab01 for the second part of the lab (Fig. 3). 2) You can use the same chip as the basic current mirror;

### Band Gap Energy in Silicon

Band Gap Enery in Silicon Jeremy J. Low, Michael L. Kreider, Drew P. Pulsifer Andrew S. Jones and Tariq H. Gilani Department of Physics Millersville University P. O. Box 12 Millersville, Pennsylvania 17551

### BJT Amplifier Circuits

JT Amplifier ircuits As we have developed different models for D signals (simple large-signal model) and A signals (small-signal model), analysis of JT circuits follows these steps: D biasing analysis:

### 3. Common Mode Rejection Ratio: Part I

3. ommon Mode ejection atio: Part I 3. Introduction In general, an instrumentation amplifier is required to amplify the difference between two input signals or voltages, and as shown in Fig.. However,

### Lecture 260 Buffered Op Amps (3/28/10) Page 260-1

Lecture 260 Buffered Op Amps (3/28/0) Page 260 LECTURE 260 BUFFERED OP AMPS LECTURE ORGANIZATION Outline Introduction Open Loop Buffered Op Amps Closed Loop Buffered Op Amps Use of the BJT in Buffered

### EECS 240 Topic 7: Current Sources

EECS 240 Analog Integrated Circuits Topic 7: Current Sources Bernhard E. Boser,Ali M. Niknejad and S.Gambini Department of Electrical Engineering and Computer Sciences Bias Current Sources Applications

### VI. Transistor amplifiers: Biasing and Small Signal Model

VI. Transistor amplifiers: iasing and Small Signal Model 6.1 Introduction Transistor amplifiers utilizing JT or FET are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly.

### Field effect transistors

Field effect transistors Junction FETs Metal-Oxide Semiconductor FETs type N type P enhancement depletion type N type P type N type P Slide 1 Junction field effect transistor - JFET Construction and circuits

### Lecture 27: Frequency response. Context

Lecture 27: Frequency response Prof J. S. Smith Context Today, we will continue the discussion of single transistor amplifiers by looking at common source amplifiers with source degeneration (also common

### Monte Carlo Simulation of Device Variations and Mismatch in Analog Integrated Circuits

Proceedings of The National Conference On Undergraduate Research (NCUR) 2006 The University of North Carolina at Asheville Asheville, North Carolina April 6 8, 2006 Monte Carlo Simulation of Device Variations

### CMOS Digital Integrated Circuits Analysis and Design

CMOS Digital Integrated Circuits nalysis and Design Chapter 7 Combinational MOS Logic Circuits 1 Introduction Combination logic circuit Performing Boolean operations between input and put Static and dynamic

### Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-1

Lecture 230 Design of TwoStage Op Amps (3/27/0) Page 230 LECTURE 230 DESIGN OF TWOSTAGE OP AMPS LECTURE OUTLINE Outline Steps in Designing an Op Amp Design Procedure for a TwoStage Op Amp Design Example

### Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications

Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications Rajkumar S. Parihar Microchip Technology Inc. Rajkumar.parihar@microchip.com Anu Gupta Birla Institute of

### Experiment 4 Common-Source Transistor Amplifiers

Name and ID: 1 OBJECTIVE Group Number: Date: Experiment 4 Common-Source Transistor Amplifiers To measure DC and AC voltages in common-source amplifier. To obtain measured values of voltage amplification

### Junction Field Effect Transistor (JFET)

Junction Field Effect Transistor (JFET) The single channel junction field-effect transistor (JFET) is probably the simplest transistor available. As shown in the schematics below (Figure 6.13 in your text)

### Fully Differential CMOS Amplifier

ECE 511 Analog Electronics Term Project Fully Differential CMOS Amplifier Saket Vora 6 December 2006 Dr. Kevin Gard NC State University 1 Introduction In this project, a fully differential CMOS operational

### Introduction to PSpice

IL2218 Analog electronics, advanced course Document version 3.1 2010 01 11/Bengt M. Introduction to PSpice This introduction is valid for OrCad PSpice ver 9.2 lite edition. The lite edition or student

### EE105 Fall 2014 Microelectronic Devices and Circuits. Ideal vs Non-ideal Op Amps

EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) vs Non-ideal Op Amps Op Amp A 0 Non-ideal Op Amp A < < > 0 Other non-ideal characteristics:

### Op-Amp Simulation EE/CS 5720/6720. Read Chapter 5 in Johns & Martin before you begin this assignment.

Op-Amp Simulation EE/CS 5720/6720 Read Chapter 5 in Johns & Martin before you begin this assignment. This assignment will take you through the simulation and basic characterization of a simple operational

### CHAPTER.4: Transistor at low frequencies

CHAPTER.4: Transistor at low frequencies Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model Introduction There are three models commonly

### Lecture 220 Compensation of Op Amps (3/27/10) Page 220-1

Lecture 220 Compensation of Op Amps (3/27/0) Page 220 LECTURE 220 INTRODUCTION TO OP AMPS LECTURE OUTLINE Outline Op Amps Categorization of Op Amps Compensation of Op Amps Miller Compensation Other Forms

### Lecture 280 Differential-In, Differential-Out Op Amps (3/28/10) Page 280-1

Lecture 280 DifferentialIn, DifferentialOut Op Amps (3/28/10) Page 2801 LECTURE 280 DIFFERENTIALIN, DIFFERENTIALOUT OP AMPS LECTURE ORGANIZATION Outline Introduction Examples of differential output op

### Lecture 250 Measurement and Simulation of Op amps (3/28/10) Page 250-1

Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 LECTURE 5 SIMULATION AND MEASUREMENT OF OP AMPS LECTURE ORGANIZATION Outline Introduction Open Loop Gain CMRR and PSRR A general method of measuring

### 6.012 DP: CMOS Integrated Differential Amplifier

6.012 DP: CMOS Integrated Differential Amplifier Tony Hyun Kim Contents 1 Introduction 1 2 Common-source gain stage with Lee load 2 3 Cascode current mirror gain stage 3 4 Push-pull output stage 5 4.1

### Lecture 19 - Transistor Amplifiers (I) Common-Source Amplifier. November 15, 2005

6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 191 Lecture 19 Transistor Amplifiers (I) CommonSource Amplifier November 15, 2005 Contents: 1. Amplifier fundamentals 2. Commonsource amplifier

### Lecture 060 Push-Pull Output Stages (1/11/04) Page 060-1. ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 060 PushPull Output Stages (1/11/04) Page 0601 LECTURE 060 PUSHPULL OUTPUT STAGES (READING: GHLM 362384, AH 226229) Objective The objective of this presentation is: Show how to design stages that

### BJT Amplifier Circuits

JT Amplifier ircuits As we have developed different models for D signals (simple large-signal model) and A signals (small-signal model), analysis of JT circuits follows these steps: D biasing analysis:

### Chapter 12: The Operational Amplifier

Chapter 12: The Operational Amplifier 12.1: Introduction to Operational Amplifier (Op-Amp) Operational amplifiers (op-amps) are very high gain dc coupled amplifiers with differential inputs; they are used

### Capacitors and RC Circuits

Chapter 6 Capacitors and RC Circuits Up until now, we have analyzed circuits that do not change with time. In other words, these circuits have no dynamic elements. When the behavior of all elements is

### Enhancement Mode MOSFET Circuits

Engineering Sciences 154 Laboratory Assignment 4 Enhancement Mode MOSFET Circuits Note: This is quite a long, but very important laboratory assignment. Take enough time - at least two laboratory sessions

### Physics 160. Fun with Op Amps. R. Johnson May 13, 2015

Physics 160 Lecture 14 Fun with Op Amps. Johnson May 13, 015 Ideal Op-Amp Differential gain, of course. Common-mode gain is ideally zero. Such an ideal op-amp of course does not exist, but a first analysis

### CMOS Sample-and-Hold Circuits

CMOS Sample-and-Hold Circuits ECE 1352 Reading Assignment By: Joyce Cheuk Wai Wong November 12, 2001 Department of Electrical and Computer Engineering University of Toronto 1. Introduction Sample-and-hold

### School of Engineering Department of Electrical and Computer Engineering

1 School of Engineering Department of Electrical and Computer Engineering 332:223 Principles of Electrical Engineering I Laboratory Experiment #4 Title: Operational Amplifiers 1 Introduction Objectives

### Design and Layout of a Telescopic Operational Transconductance Amplifier

Design and Layout of a Telescopic Operational Transconductance Amplifier By Erik McCarthy Department of Electrical and Computer Engineering University of Maine Orono, Maine erik.mccarthy@umit.maine.edu

### Transistor amplifiers: Biasing and Small Signal Model

Transistor amplifiers: iasing and Small Signal Model Transistor amplifiers utilizing JT or FT are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly. Then, similar FT

### Operational Amplifiers

Operational Amplifiers Aims: To know: Basic Op Amp properties eal & Ideal Basic ideas of feedback. inv input noninv input output gnd To be able to do basic circuit analysis of op amps: using KCL, KL with

### Chapter 8:Field Effect Transistors (FET s)

Chapter 8:Field Effect Transistors (FET s) The FET The idea for a field-effect transistor (FET) was first proposed by Julius Lilienthal, a physicist and inventor. In 1930 he was granted a U.S. patent for

### Peggy Alavi Application Engineer September 3, 2003

Op-Amp Basics Peggy Alavi Application Engineer September 3, 2003 Op-Amp Basics Part 1 Op-Amp Basics Why op-amps Op-amp block diagram Input modes of Op-Amps Loop Configurations Negative Feedback Gain Bandwidth

### A High Unity Gain Bandwidth and Rail-to-Rail Operational Amplifier Design

A High Unity Gain Bandwidth and Rail-to-Rail Operational Amplifier Design Department of Electrical and Computer Engineering North Carolina State University Wenxu Zhao, Zhuo Yan {wzhao2, zyan2}@ncsu.edu

### Lecture 060 Push-Pull Output Stages (1/6/02) Page 060-1. ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 060 PushPull Output Stages (1/6/02) Page 0601 LECTURE 060 PUSHPULL OUTPUT STAGES (READING: GHLM 362384, AH 226229) Objective The objective of this presentation is: Show how to design stages that

### Lecture 140 The MOS Switch and Diode (3/25/10) Page 140-1

Lecture 140 The MOS Switch and Diode (3/25/10) Page 140-1 LECTURE 140 THE MOS SWITCH ND MOS DIODE LECTURE ORGNIZTION Outline MOSFET as a switch Influence of the switch resistance Influence of the switch

### Current Source Biasing

Current Source Biasing ntegrated circuits have transistors which are manufactured simultaneously with the same device parameters (parameters from chip to chip will vary) As a result, different bias techniques

### MAS.836 HOW TO BIAS AN OP-AMP

MAS.836 HOW TO BIAS AN OP-AMP Op-Amp Circuits: Bias, in an electronic circuit, describes the steady state operating characteristics with no signal being applied. In an op-amp circuit, the operating characteristic

### The BJT Differential Amplifier. Basic Circuit. DC Solution

c Copyright 010. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The BJT Differential Amplifier Basic Circuit Figure 1 shows the circuit

### BJT Ebers-Moll Model and SPICE MOSFET model

Department of Electrical and Electronic Engineering mperial College London EE 2.3: Semiconductor Modelling in SPCE Course homepage: http://www.imperial.ac.uk/people/paul.mitcheson/teaching BJT Ebers-Moll

### PSPICE Schematic Student 9.1 Tutorial --X. Xiong

PSPICE Schematic Student 9.1 Tutorial --X. Xiong This tutorial will guide you through the creation and analysis of a simple MOSFET circuit in PSPICE Schematic. The circuit diagram below is what you will

### Chapter 11 Current Programmed Control

Chapter 11 Current Programmed Control Buck converter v g i s Q 1 D 1 L i L C v R The peak transistor current replaces the duty cycle as the converter control input. Measure switch current R f i s Clock

### DC Circuits: Operational Amplifiers Hasan Demirel

DC Circuits: Operational Amplifiers Hasan Demirel Op Amps: Introduction Op Amp is short form of operational amplifier. An op amp is an electronic unit that behaves like a voltage controlled voltage source.

### EXPERIMENT 1.2 CHARACTERIZATION OF OP-AMP

1.17 EXPERIMENT 1.2 CHARACTERIZATION OF OPAMP 1.2.1 OBJECTIVE 1. To sketch and briefly explain an operational amplifier circuit symbol and identify all terminals 2. To list the amplifier stages in a typical

### Fig. 1 :Block diagram symbol of the operational amplifier. Characteristics ideal op-amp real op-amp

Experiment: General Description An operational amplifier (op-amp) is defined to be a high gain differential amplifier. When using the op-amp with other mainly passive elements, op-amp circuits with various

### Any-Cap Low Dropout. Voltage Regulator. Matthew Topp. A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science

Any-Cap Low Dropout Voltage Regulator by Matthew Topp A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science Approved April 2012 by the Graduate Supervisory Committee:

### Lecture 39: Intro to Differential Amplifiers. Context

Lecture 39: Intro to Differential Amplifiers Prof J. S. Smith Context Next week is the last week of lecture, and we will spend those three lectures reiewing the material of the course, and looking at applications

### Diploma in Applied Electronics

DUBLIN INSTITUTE OF TECHNOLOGY KEVIN STREET, DUBLIN 8 Diploma in Applied Electronics YEAR II SUMMER EXAMINATIONS 1999 ELECTRIC CIRCUITS MR. P. Tobin MR. C. Bruce DATE Attempt FIVE questions with a maximum

### Laboratory 4: Feedback and Compensation

Laboratory 4: Feedback and Compensation To be performed during Week 9 (Oct. 20-24) and Week 10 (Oct. 27-31) Due Week 11 (Nov. 3-7) 1 Pre-Lab This Pre-Lab should be completed before attending your regular

### Operational Amplifiers: Part 2. Non-ideal Behavior of Feedback Amplifiers DC Errors and Large-Signal Operation

Operational Amplifiers: Part 2 Non-ideal Behavior of Feedback Amplifiers DC Errors and Large-Signal Operation by Tim J. Sobering Analog Design Engineer & Op Amp Addict Summary of Ideal Op Amp Assumptions