The future of nano-computing

The future of nano-computing George Bourianoff Intel Corporation Presented to International Engineering Consortium and Electrical and Computer Engineering Department Heads Jan. 27, 2003 San Jose, Ca 2/5/2003 Intel Corp. George Bourianoff 1

Future of Nanocomputing Scalable new technology criteria Scalable new technology Silicon highway criteria characteristics origins limits taxonomy elements 2/5/2003 Intel Corp. George Bourianoff 2

Key messages CMOS scaling will continue for next 12 15 years Alternative new technologies will emerge and begin to be integrated on CMOS by 2015 Nanoscience research is needed to facilitate radical new scalable technologies beyond 2020 2/5/2003 Intel Corp. George Bourianoff 3

The future of nanocomputing Introduction Scaled CMOS Nano-computing, nano-technology and nano-science Radical new technologies Challenges Conclusions 2/5/2003 Intel Corp. George Bourianoff 4

The foundations of microelectronics Government funded research in solid state physics in 1930 s and 40 s laid the foundation Central Breakthroughs: Band structure concept Minute amounts of impurities control properties Advances in purification and high quality crystal growth of Si and Ge Beginning about 1946, we began to utilize this knowledge base Most basic semiconductor devices were demonstrated within 12 years Bipolar transistor 1948 Field effect transistor 1953 LED 1955 Tunnel diode 1957 IC 1959 Laser 1960 2/5/2003 Intel Corp. George Bourianoff 5

The beauty of silicon For four decades, the semiconductor industry has steadily reduced the unit cost of IC components by 1. Scaling device dimensions downward 2. Scaling wafer diameter upward DRAMs Feature size Wafer diameter Cost per Megabit 1990 1995 2000 4 MB 64 MB 1 GB 0.8 µm 0.35 µm 0.15 µm 6 8 12 $6.50 $3.14 $0.10 2/5/2003 Intel Corp. George Bourianoff 6

Brick Walls on the ITRS YEAR TECHNOLOGY NODE 1999 180 nm 2002 130 nm 2005 100 nm On-chip local frequency (MHz) 1.25 2.10 3.50 Number of metal levels - Logic 6-7 7-8 8-9 Number of optional levels 0 2 2 Jmax (A/cm 2 ) - wire (at 105 o C) 5.8 E5 9.6 E5 1.4 E6 Local wiring pitch - DRAM non-contacted (nm) 360 260 200 Local wiring pitch - Logic (nm) 500 325 230 Local wiring AR-Logic (Cu) 1.4 1.5 1.7 Cu local dishing (nm) 18 14 11 Intermediate wiring pitch - Logic (nm) 560 405 285 Intermediate wiring h/w AR - Logic (Cu DD via/lin) 2.0/2.1 2.2/2.1 2.4/2.2 Cu intermediate wiring dishing - 15 um wide wire (nm) 64 51 41 Dielectric erosion, intermediate wiring 50% density (nm) 64 51 41 Global wiring pitch - Logic (nm) 900 650 460 Global wiring h/w AR - Logic - Cu DD via/line (nm) 2.2/2.4 2.5/2.7 2.7/2.8 Cu global wiring dishing, 15 um wide wire (nm) 116 95 76 Contact aspect ratio - DRAM, stacked cap 9.3 11.4 13 Conductor effective resistivity (uohm -cm) 2.2 2.2 2.2 Barrier/cladding thickness (nm) 17 13 10 Interlevel metal insulator effective dielectric constant (k) - Logic 4.0-3.5 3.5-2.7 2.2-1.6 2008 70 nm 2011 50 nm 2014 35 nm 6.00 10.00 13.50 9 9-10 10 3 4 4 2.1 E6 3.7 E6 4.6 E6 140 100 70 165 120 85 1.9 2.1 2.2-2.3 9 7 5 210 145 110 2.5/2.3 2.7/2.4 2.9/2.5 30 22 17 0 0 0 330 240 170 2.8/2.9 2.9/3.0 3.0/3.1 55 38 20 14.1 16.1 23.1 1.8 < 1.8 < 1.8 0 0 0 1.4 <1.5 <1.5 2008 70 nm 2011 50 nm 2014 35 nm 6.00 10.00 13.50 9 9-10 10 3 4 4 2.1 E6 3.7 E6 4.6 E6 140 100 70 165 120 85 1.9 2.1 2.2-2.3 9 7 5 210 145 110 2.5/2.3 2.7/2.4 2.9/2.5 30 22 17 0 0 0 330 240 170 2.8/2.9 2.9/3.0 3.0/3.1 55 38 20 14.1 16.1 23.1 1.8 < 1.8 < 1.8 0 0 0 1.4 <1.5 <1.5 Solutions Exist Solutions being pursued 2/5/2003 No known solutions Intel Corp. George Bourianoff 7

Silicon Nanotechnology is Here! 10 Nominal feature size 10000 1 1000 Micron 0.1 Gate Width 130nm 90nm 100 Nano- meter Nanotechnology 70nm 50nm 0.01 10 1970 1980 1990 2000 2010 2020 2/5/2003 Intel Corp. George Bourianoff 8

The ingredients of scaling Material Evolution in MOS 2000 s Al-Cu New materials Al-Cu Al-Cu W Al-Si Ti/TiN Ti/TiN Al Poly WSi2/Poly TiSi2/Poly 60 s 70 s 80 s 90 s Al-Cu W Low K Ti/TiN TiSi2/Poly W Cu ELK Ti/TiN CSi2/Poly Improved processing New geometries SiO2 SiO2 SiO2 SiO2 SiO2 SiO2/SiN Silicon Silicon Silicon Silicon Silicon Silicon Scaling Will continue as long as (δ cost) /(δ performance) < alternate technologies 2/5/2003 Intel Corp. George Bourianoff 9

Transistor Scaling 70nm 70nm transistor for 0.13µm process 2001 production Demo: 2000 30nm Drain Current (µa/µm) 500 400 300 200 100 0 15nm NMOS Vg = 0.8V 0 0.2 0.4 0.6 0.8 Drain Voltage (V) 0.7V 0.6V 0.5V 0.4V 0.3V Influenza virus Source: CDC 100nm 30nm transistor Prototype Source: Intel (IEDM, Dec 2001) 15nm 15nm transistor prototype 2/5/2003 Intel Corp. George Bourianoff 10

New Materials Changes Made Gate Silicide added Channel Strained silicon Transistor Future Options High-k gate dielectric New transistor structure Source: Intel The problem: High Ioff current 2/5/2003 Intel Corp. George Bourianoff 11

New Geometries Gate Silicon Id ( (ma ma/µm) 1.2 1.0 0.8 0.6 0.4 0.2 Drain Source Source Gate Drain Source: Intel (ISSDM, Sep 2002) 0 0.3 0.6 0.9 1.2 Vd (V) Source: Intel 2/5/2003 Intel Corp. George Bourianoff 12

Improved processing EUV Lithography Prototype Exposure Tool 50nm Lines Printed with EUV Lithography EUV lithography in commercialization phase Cost effectiveness is key challenge 2/5/2003 Intel Corp. George Bourianoff 13 Source: Sandia

The limits of logic scaling For an arbitrary switching device made of of a single electron in a dual quantum well Operating at room temperature It can be shown a power dissipation limit of 100 W/cm**2 Will limit the operational frequency to ~100 GHz at length scales ~ 4 nm 2/5/2003 Intel Corp. George Bourianoff 14

CMOS device circa 2016 Cost 10-11 $/gate Size 8 nm / device Speed 0.2 ps /operation Energy 10-18 J/operation 2/5/2003 Intel Corp. George Bourianoff 15

The future of nanocomputing Introduction Scaled CMOS Nano-computing, nano-technology and nano-science A taxonomy New devices New architectures Alternative state variables Radical new technologies Challenges Conclusions 2/5/2003 Intel Corp. George Bourianoff 16

biotech Digital Electric charge A taxonomy for nano-computing Memory devices analogue Molecular state patterns sensors Spin orientation probabilities Flux quanta associative Quantum state Heirarchy Data represent ations State variables Boolean Scaled CMOS CNN Crossbar Quantum Architecture CNT FETs Molecular Spintronics Quantum Devices Time 2/5/2003 Intel Corp. George Bourianoff 17

The future of nanocomputing Introduction Scaled CMOS Nano-computing, nano-technology and nano-science A taxonomy New devices New architectures Alternative state variables Radical new technologies Challenges Conclusions 2/5/2003 Intel Corp. George Bourianoff 18

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CNT-FET Device Structure E-beam Ti/Au gate Mo S/D 8 nm ZrO2 1.4 nm diameter single wall CNT McEuen et. al,. Cornell Universwity 2/5/2003 Intel Corp. George Bourianoff 20

Nanowire Gating Geometries Back gate D S G SiO 2 Si Top gate G D S D Coaxial gate G S 2/5/2003 Intel Corp. George Bourianoff C. Leiber et. al., Harvard U 21

Top-gated p-si Nanowire Transistors -2.5-2.0 V GS G D S SiO x Si I DS (µa) -2.0-1.5-1.0-1.5 V GS -1.0 V GS -0.5 V GS -0.5 0.0 V GS C. Leiber et. al., Harvard U 1 µm G D S -I DS (na) +0.5 V GS 0.0-4 -3-2 -1 0 V DS (V) 1500 250 mv/dec 1000 700 na/v 1000 100 10 500 1 -I DS (na) 1 µm 0.1 V DS = -1 V 0 0.01-2 -1 0 1 2 2/5/2003 Intel Corp. George Bourianoff 22 V GS (V)

Crossed Nanowire Structures: A Powerful Strategy for Creation & Integration of Nanodevices Nanowires serve dual purpose: both active devices and interconnects. All key nanoscale metrics are defined during synthesis and subsequent assembly. Crossed nanowire architecture provides natural scaling and potential for integration at highest densities. No additional complexity (with added material). 2/5/2003 Intel Corp. George Bourianoff 23 C. Leiber et. al., Harvard U

Crossed Nanowire FETs Current (na) 400 200 0-200 -400 Current (na) 10 2 10 0 10-2 0 1 2 3 4 Gate (V) 5-1.0-0.5 0.0 0.5 1.0 Bias (V) S V g (V): G D 0 1 2 3 In crossed nanowire FETs (cnw-fet), all critical nanoscale metrics are defined by synthesis and assembly: channel width by the active nanowire diameter (to 2 nm) channel length by the gate nanowire diameter (to 1-2 nm) gate dielectric oxide coating on the nanowires (to 1 atomic layer) The conductance of cnw-fets can be changed by more than 10 5 -times with less than 0.1 V variation in the nano-gate. 2/5/2003 Intel Corp. George Bourianoff 24 Huang, Duan, Lieber et al., Science 294, 1313 (2001)

Device Demonstrated P-N Junction Lieber/Harvard 2/5/2003 Intel Corp. George Bourianoff 25

Room temperature Single Electron Transistor (SET) Single electron in island controls current flow from source to drain Typical sizes of the TiOx lines are 15-25 nm widths and 30-50 nm lengths. Typical island sizes are 30-50 nm by 35-50 50 nm Courtesy, NEC, IEDM 2000, PP 481 2/5/2003 Intel Corp. George Bourianoff 26

Spin resonance transistor (SRT) Transistors that control spins rather than charge More energy efficient than conventional transistors Combines magnetic and electrostatic fields May enable quantum computing Courtesy Eli Yablanovitch,, UCLA 2/5/2003 Intel Corp. George Bourianoff 27

A Molecular Electronic Switch (2-amino-4-ethyinylphenyl-4-ethylphenyl-5- Silicon Nitride nitro-1-benzenethiolate) Au 1000 Self Assembled Molecules (SEM) Current (pa) 1 1 Au IV Characteristics (@T=60K) 0.00 0.50 1.00 1.50 2.00 2.50 3.00 Voltage (V) 2/5/2003 Intel Corp. George Bourianoff 28 Source: M.Reed & others,yale Univ and Rice Univ

The future of nanocomputing Introduction Scaled CMOS Nano-computing, nano-technology and nano-science A taxonomy New devices New architectures Alternative state variables Radical new technologies Challenges Conclusions 2/5/2003 Intel Corp. George Bourianoff 29

Emerging Research Architectures ON 2 H 2 N ARCHITECTURE DEVICE IMPLEMENTATION ADVANTAGES CHALLENGES 3-D INTEGRATION CMOS with dissimilar material systems Less interconnect delay, Enables mixed technology solutions Heat removal, No design tools, Difficult test and measurement QUANTUM CELLULAR AUTOMATA Arrays of quantum dots High functional density. No interconnects in signal path Limited fan out, Dimensional control (low temperature operation), Sensitive to background charge DEFECT TOLERANT ARCHITECTURE Intelligently assembles nanodevices Supports hardware with defect densities >50% Requires precomputing test MOLECULAR ARCHITECTURE Molecular switches and memories Supports memory based computing Limited functionality CELLULAR NONLINEAR NETWORKS Single electron array architectures Enables utilization of single electron devices at room temperature Subject to background noise, Tight tolerances QUANTUM COMPUTING Spin resonance transistors, NMR devices, Single flux quantum devices Exponential performance scaling, Enables unbreakable cryptography Extreme application limitation, Extreme technology MATURITY Demonstration Demonstration Demonstration Concept Demonstration Concept 2/5/2003 Intel Corp. George Bourianoff 30

Quantum Cellular Automata Adder circuit with carry executed in QCA logic Example of asynchronous, CNN, nearest neighbor architecture Courtesy of Notre Dame 2/5/2003 Intel Corp. George Bourianoff 31

Fault tolerant architecture All-memory architecture Defect tolerant Potentially self-repairing and reconfigurable J. Heath, R. S. Williams et al, UCLA and HP 2/5/2003 Intel Corp. George Bourianoff 32

Store information in the relative phase of 2 signals Multi-valued logic possible depending on frequencies of 2 signals Tunneling Phase logic devices use RTDs to create one of the signals Phase logic Courtesy: R Keihle,, University of Minnesota 2/5/2003 Intel Corp. George Bourianoff 33

Quantum Computer A-Gate J-Gate A-Gate - - - + + + 28 Si Barrier layer e - 31 P 31 P Selected technological implementations Liquid-state NMR Linear ion trap Coupled quantum dots Deterministically doped semicondustor structures 2/5/2003 Intel Corp. George Bourianoff 34

The future of nanocomputing Introduction Scaled CMOS Nano-computing, nano-technology and nano-science A taxonomy New devices New architectures Alternative state variables Radical new technologies Challenges Conclusions 2/5/2003 Intel Corp. George Bourianoff 35

Alternative state variables Electric charge Molecular state Spin orientation Electric dipole orientation Photon intensity Photon polarization Quantum state Phase state Mechanical state 2/5/2003 Intel Corp. George Bourianoff 36

The future of nanocomputing Introduction Scaled CMOS Nano-computing, nano-technology and nano-science A taxonomy New devices New architectures Alternative state variables Radical new technologies Challenges Conclusions 2/5/2003 Intel Corp. George Bourianoff 37

Economic criteria Economic relevance criteria The risk adjusted ROI for any new technology must exceed that of silicon Caution Sufficiently advanced technologies will create their own applications. New technologies cannot necessarily be justified by current day applications. 2/5/2003 Intel Corp. George Bourianoff 38

Technical criteria CMOS compatibility Energy efficiency Scalability Performance Architectural compatibility Sensitivity to parametric variation Room temperature operation Stability and reliability 2/5/2003 Intel Corp. George Bourianoff 39

Existence proof for alternate models The brain is the ultimate model for its ability to deal with complexity Little understanding on its architecture & organization It is however Orders of magnitude more powerful than the best microprocessor Self assembled Parallel operation Self repairing to a significant degree Fault tolerant Runs on ~ 10W 2/5/2003 Intel Corp. George Bourianoff 40

Breakthrough scientific investigation is needed 1952 Achievements Bulk band structure of solids Doping 2002 Needs geometry dependent energetic structure of nanostructures precise location of atoms Crystal growth self organization of matter in complex structures 2/5/2003 Intel Corp. George Bourianoff 41

The integration challenge Scalability Node Controller Memory Scalability Node Controller Memory Scalability Port Switch Scalability Port Switch I/O Bridge I/O Hub I/O Bridge I/O Hub PCI-(X) Bridge InfiniBand* Bridge PCI-(X) Bridge InfiniBand* Bridge Intel 82870 4-way & 8-way 8 Server Configurations 2/5/2003 Intel Corp. George Bourianoff 42

Conclusions CMOS scaling will continue for next 12 15 years Alternative new technologies will emerge and begin to be integrated on CMOS by 2015 Nanoscience research is needed to facilitate radical new scalable technologies beyond 2020 2/5/2003 Intel Corp. George Bourianoff 43

For further information on Intel's silicon technology, please visit the Silicon Showcase at www.intel.com/research/silicon 2/5/2003 Intel Corp. George Bourianoff 44

Backup 2/5/2003 Intel Corp. George Bourianoff 45

For about four decades now we have exploited (mined) our investment in basic science and we have continuously evolved the devices based on this understanding 2/5/2003 Intel Corp. George Bourianoff 46

Nanotechnology for Gate Dielectrics Transistor gate oxide thickness trend Gate 1.2nm SiO 2 Source: Intel Dimension (nm) 100 10 90nm process Capacitance 1X Leakage 1X Si-O bond: 0.16nm SiO2 High K 1 1970 1980 1990 2000 2010 2020 First year in production Experimental high-k 1.6X < 0.01X Silicon substrate Gate 3.0nm High-k Silicon substrate Leakage is the limiter to SiO2 scaling Integration is the key challenge to High K 2/5/2003 Intel Corp. George Bourianoff 47

What new basic science is s r R needed? Spin manipulation, e.g. transport, storage, detection, creation, Geometry related quantum effects, e.g. quantum wedge, parabolic wells, Source Si P + P + B - Drain Precise location of atoms e.g. coherent manipulation of entangled wavefunctions 2/5/2003 Intel Corp. George Bourianoff 48

Transport in Si-Ge Core-Shell Structures -2.5 V GS = -1.1 V D G S SiO x Ge Si I DS (µa) -2.0-1.5-1.0-0.5-0.9-0.7-0.5-0.3 0.0 0.0-4 -3-2 -1 0 V DS (V) 1000 1000 S D G 500 nm 0 0.01-1.0 0.0 1.0 2/5/2003 Intel Corp. George Bourianoff 49 V GS (V) -I DS (na) 800 600 330 mv/dec 100 10 400 200 1300 na/v 1 0.1 V DS = -1 V -I DS (na)

Coaxially-Gated Si-Ge SiO x Ge -2.5-2.0 Si I DS (µa) -1.5-1.0-0.5-1 V GS -2 V GS Ge 0.0 O V GS 0.5-1.5-1.0-0.5 0.0 V SD (V) 3.0 450 mv/dec. 1000 2.5 100 2.0 1.5 10 1.0 1.5 µa/v 1 0.5 +1 V DS 0.0 0.1-2 -1 0 1 2 2/5/2003 Intel Corp. George Bourianoff 50 V GS (V) I DS (µa) I DS (na)

Devices Demonstrated Nanowire FET Lieber/Harvard 2/5/2003 Intel Corp. George Bourianoff 51

Photonic devices Man-made crystals produced by etching precisely placed holes in silicon or III-V material Can produce, detect and manipulate light more efficiently than naturally occurring materials 2/5/2003 Intel Corp. George Bourianoff 52

System software design needs to facilitate emerging technologies Challenge CMOS is based on Boolean logic and binary data representation Alternative technologies will require native logic systems and data representations to optimize their performance Solution? Design science must provide functional abstractions and interfaces to couple multiple, dissimilar technologies into a single functional system 2/5/2003 Intel Corp. George Bourianoff 53

Nano-computing, nanotechnology and nano-science 2/5/2003 Intel Corp. George Bourianoff 54

Changing architectural paradigms Current Boolean logic Binary data representation 2D Homogeneous Globally interconnected Synchronous Von Neuman 3 terminal Future Neural networks, CNN, QCA, Associative, patterned, memory based, data representations 3D Non homogeneous Nearest neighbor Asynchronous Integrated memory/logic 2 terminal 2/5/2003 Intel Corp. George Bourianoff 55