Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 8 Latches And Flip Flops Characteristics November 25, 2012
1. Objectives: 1. To become familiar with flip-flops. 2. To implement and observe the operation of different flip-flops. 2. Theory: Sequential Circuits: Digital electronics is classified into combinational logic and sequential logic. Combinational logic output depends on the inputs levels, whereas sequential logic output depends on stored levels and also the input levels. The memory elements are devices capable of storing binary info. The binary info stored in the memory elements at any given time defines the state of the sequential circuit. The input and the present state of the memory element determine the output. Memory elements next state is also a function of external inputs and present state. A sequential circuit is specified by a time sequence of inputs, outputs, and internal states. Examples of sequential circuits are Flip-Flops, latches, counters, registers, and time state generators. So, combinatorial circuits are ones whose outputs depend on the current input state. When inputs change, the outputs do not depend on the previous inputs. Sequential circuits are similar, but they do also rely on previous input states. It can be inferred that they have memory. There are two types of sequential circuits. Their classification depends on the timing of their signals: Synchronous sequential circuits Asynchronous sequential circuits Synchronization is achieved by a timing device called a clock pulse generator. Clock pulses are distributed throughout the system in such a way that the flip-flops are affected only with the arrival of the synchronization pulse. Synchronous sequential circuits that use clock pulses in the inputs are called clocked-sequential 1
circuits. They are stable and their timing can easily be broken down into independent discrete steps, each of which is considered separately. Synchronous The same clock signal is applied to each flip-flop, and changes in state occur when the clock changes state from one level to another. Asynchronous The behavior of an asynchronous circuit depends on the order in which the inputs change. Sometimes, there is an input labeled clock, that provides some level of synchronization, but it is normally only applied to one flip-flop. In addition to this style of asynchronous circuit, you also get gate-level asynchronous circuits, which are combinatorial circuits with feedback. Flip-Flops & Latches: "Flip-flop" is the common name given to two-state devices which offer basic memory for sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and are commonly used in banks called "registers" for the storage of binary numerical data. Types of Flip-Flops There are several types of flip-flops and they are R-S, J-K, D and T flip-flops, but the two most important kinds are the D and J-K flip-flops. SR latch The flip-flop circuit can be constructed from tow NAND gates or tow NOR gates. 2
The NOR SR latch has active high inputs, meaning that if either input is brought high, it will force a corresponding output condition. Note that setting both input values high must be avoided in order to retain the output values as opposite to each other. The NAND based SR latch is an active low device with a default state of logic high for both S and R inputs. The S and R input values are brought low to change the state. Just as the NOR based SR latch should not have both input values turned high simultaneously, the S and R for a NAND based SR latch should not be brought low at the same time. Latches vs. Flip-Flops:- Latches are flip-flops for which the timing of the output changes is not controlled. For a latch, the output essentially responds immediately to changes on the input lines (and possibly the presence of a clock pulse). A flip-flop is designed to change its output at the edge of a controlling clock signal. 3
RS Flip-Flop: In order to avoid this indeterministic behavior, we must make sure that the two inputs are never de-asserted at the same time. Note that both of them can be deasserted, but just not at the same time. In practice, this is guaranteed by not having both of them asserted. Another reason why we do not want both inputs to be asserted is that when they are both asserted, Q is equal to Q', but we usually want Q to be the inverse of Q'. D Flip-Flop: The D flip-flop is widely used. It is also known as a data or delay flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line. 4
JK Flip-Flop: The JK flip-flop is the most versatile of the basic flip-flops. It has the inputfollowing character of the clocked D flip-flop but has two inputs, traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge. JK flip-flop from D flip-flop T Flip-Flop: The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock pulse. 5
Table 1. Flip-Flop Types Excitation tables for flip-flops For SR: Q S R Q(T+1) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1? 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1? 6
Q Q(T+1) S R 0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 For T: Q T Q(T+1) 0 0 0 0 1 1 1 0 1 1 1 0 Q Q(T+1) S R 0 0 0 x 0 1 1 0 1 0 0 1 1 1 x 0 Excitation table for SR flip-flop Q Q(T+1) T 0 0 0 0 1 1 1 0 1 1 1 0 Follow the same steps to find other Excitation table for flip-flops. Excitation table for T flip-flop Examples for converting flip-flop: Example 1: Convert a D-FF to a T-FF: Solution: Consider the excitation table: 7
Treating D as a function of T and current FF state Q, we have Q T 0 1 0 1 0 1 1 0 Example 2: Convert a D-FF to a JK-FF: Solution: Consider the excitation table: Using K-map: D = Q'J + K'Q 8
Timing diagram: Timing diagram for the positive edge triggered D flip-flop: The timing diagram for the negatively triggered JK flip-flop Timing diagram for the D latch 9
3. Lab Work: Part1: D Flip-Flop: - Construct D Flip-Flop using KL-33008 block d as shown then test the results. Part2: JK Flip-Flop: - Construct JK Flip-Flop using KL-33008 block d as shown then test the results. 10
Part3: T Flip-Flop: - Construct T Flip-Flop using KL-33008 block d, then test the results. Part4: RS Latch & RS Flip-Flop: - Construct RS Latch using KL-33008 block d, then test the results. 11
- Construct RS Flip-Flop using KL-33008 block d, then test the results. 4. Exercises: 1) Convert a RS-FF to a JK-FF: 2) Convert a RS-FF to a D-FF: 12
3) Complete the timing diagram for D Latch: 13