ELE2120 Digital Circuits and Systems Tutorial Note 5
Outline 1. Complex PLD 2. Field - Programmable Gate Array (FPGA) 3. Lookup Table (LUT) 4. Multiplexer 5. Shannon s Expansion
Complex PLD(CPLD) Combined by PAL-like blocks With interconnection wires to connect all the PAL-like blocks
Complex PLD(CPLD) XOR with 1 programmable input: If input = 1, complement the OR gate output. If input = 0, retain the OR gate output. D-type flip flop: Store value of the previous state Multiplexer: Select between value of current state or previous state Tri-state buffer: Control the pin to be input or output Close: output. Open: input.
Field Programmable Gate Array(FPGA) FPGAs are a distinct from SPLDs and CPLDs and typically offer the highest logic capacity. An FPGA consists of an array of logic blocks, surrounded by programmable I/O blocks, and connected with programmable interconnect. A typical FPGA contains from 64 to tens of thousands of logic blocks and an even greater number of flip-flops. Most FPGAs do not provide 100% interconnect between logic blocks (to do so would be prohibitively expensive). Instead, sophisticated software places and routes the logic on the device much like a PCB auto-router would place and route components.
Field Programmable Gate Array (FPGA) CPLD FPGA Structure AND and OR planes Constructed by many logic blocks Compatible Combinational circuits Sequential circuits Capability 10,000 equ. Gates >1000,000 equ. Gates Power consumption Large Reasonable small
Lookup Table (LUT) Steps for generate Lookup Table: 1.Write down the truth table 2. Transfer the output column to lookup table. 2 input multiplexer For the function (X1+X2)
Exercise: LUT for FPGA For the logic function F1=X1X3+X2X3+X1X2, 1.Write down the truth table for F1. 2. Draw the LUT for F1. 3. What would be the result if Select = 0? Q2 Q1 X1 X2 X3 F 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Q3
Exercise: FPGA For the logic function F1=X1X3+X2X3+X1X2, 1.Write down the truth table for F1. 2. Draw the LUT for F1. 3. What would be the result if Select = 0? Q2 0 0 0 1 0 1 11 Step 2 fill the lookup table Q1 X1 X2 X3 F 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Q3 Step 1 fill the truth table
Multiplexer Multiplexer circuit has a number of data inputs, one or more select inputs, and one output.
Multiplexer Transmission Gate Symbol Transmission Gate Equivalent circuit Truth Table Why we use both PMOS and NMOS transistors to build transmission gate? Answer: 1.NMOS transistors passes 0 well and 1 poorly while PMOS transistor passes 1 well and 0 poorly. It is possible to combine an NMOS and a PMOS transistor into a single switch that is capable of driving its output terminal either to a low or high voltage equally well. 2.Small impedance(~100ohm) between x and f when closed. However, high impedance (~10 9 ohm) when opened. 3. Very short time delay between x and f.
Exercise(1): Multiplexer What is the truth table for Load, Data, A, B and output? Load Data Output
Exercise(1): Multiplexer Analysis: (1) Load = 0: TG1 closed,tg2 opened; A=Data, B=A, Output=Data; State Transmission (2) Load = 1:TG1 opened, TG2 closed; A=Output, B=A, Output=A ; State Retained
Exercise(1): Multiplexer Data Q Load _ Q D-Latch Load Data Output
Multiplexer 4-to-1 multiplexer 3 2-to-1 multiplexer Larger multiplexer can be built based on small multiplexers such as 4-to-1 or 2-to-1 multiplexer, e.g., a 4-to-1 multiplexer can be built with 3 2-to- 1multiplexers,a 8-to-1 multiplexer can be composed of 2 4-to-1 and a 2-to- 1 multiplexers, and a 16-to-1 multiplexer can be set up using 5 4-to-1 multiplexers.
Exercise(2): Multiplexer Implement the circuit for the truth table shown below by using a 4-to-1 multiplexer: W1 W2 W3 F 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1
Shannon s Expansion Multiplexer implementations of logic functions require that a given function be decomposed in terms of the variables that are used as the select inputs. This can be accomplished by means of a theorem proposed by Claude Shannon s Expansion Theorem Any Boolean function can be written in the form This expansion can be done in terms of any of the n variables. Example: f(w1,w2,w3)=w1w2+w1w3+w2w3 Expanding this function in terms of w1 gives which is the expression that we derived above Method I f(w1,w2,w3)=w1(w2+w3)+(w1+w1 )w2w3= w1(w2+w3+ w2w3)+w1 w2w3=w1(w2+w3)+w1 w2w3 Method II f(0,w2,w3)=w2w3 f(1,w2,w3)=w2+w3+w2w3 =w 2 +w 3 f(w1,w2,w3)=w 1 f(0,w2,w3)+w1 f(1,w2,w3)= w1 w2w3+ w1(w2+w3)
Shannon s Expansion Steps for solving Shannon s Expansion Method I 1. Expand(or split) the function into two part (with respect to w1 and w1 ). 2. Combine the terms into two groups of w1 and w1. Method II 1. For f(w1,w2,.wn), let w1=0, the remain minimized function is the factor for w1 2. For f(w1,w2,.wn), let w1=1, the remain minimized function is the factor for w1
Exercise: Shannon s Expansion Use the Shannon s Expansion to expand the following function: w1+w2 w3+w2w3 with respect of w1, w2: