Hardware and Software

Size: px
Start display at page:

Download "Hardware and Software"

Transcription

1 Hardware and Software 1

2 Hardware and Software: A complete design Hardware and software support each other Sometimes it is necessary to shift functions from software to hardware or the other way around Cost, speed,overall system complexity, development time and skills, etc. all affect design choices 2

3 Limitations of the software approach processors are more capable but: power consumption cost programming the solution must fit the application 3

4 Tradeoffs depend on appliction SOFTWARE Cons:constraints: power budget cost security? Pros: can be modified easier to develop HARDWARE Pros: lower power (sometimes) lower cost in volume less vulnerable to tampering Cons: no modifications 4

5 Circuits A little electronics can go a long way Design choices Very few people are experts in everything - so work with other experts to achieve more It is still good to know what is possible using other methods 5

6 Logic circuits discrete logic (74xx series components) AND, OR, NOR, NAND, XOR, and their combinations... Programmable logic is one way to consolidate digital logic circuits into fewer chips. Can be very fast, 250MHz 6

7 State machines/lookup tables Source: 7

8 State machines/lookup tables Simple state machines can be implemented as lookup charts For a fixed set of inputs, a fixed set of outputs Quick and easy to do with a PLD Use logic design and logical algebra to reduce instructions to a minimum 8

9 PLD Programmable Logic Device One-time or reprogrammable Contain macrocells which consist of basic logic, a 1-bit memory, and multiplexers Macrocells are linked by a configurable array of logic. A good example is the 22V10 Gate Array Logic device &AMID=120 9

10 Complex PLD Complex PLDs borrow capabilities from FPGAs (next) but need to be preprogrammed High-speed digital logic Example: Cypress top-of-the-line Delta39K CPLD 10

11 Verilog/VHDL Verilog and VHDL are hardware description languages With them, one can create hardware implementations through programming Can be used to program all programmable devices and even design ASICs Cypress Technical Article on VHDL 11

12 FPGA Field Programmable Gate Array Recofigurable logic device Can be reprogrammed in a short time incircuit Xilinx FPGA brochure Xilinx FPGA details 12

13 DES/3DES En/Decryption A complex algorithm in a 25MHz AVR microcontroller with FPGA at 4.2 MByte/Sec throughput 13

14 ASIC Application Specific Integrated Circuit Multiple analog and/or digital components incorporated in a single chip 14

15 System On Chip A combination of a System On Chip and programmable logic Source: 15

16 System On Chip pt2 A basic PC on a chip, just add memory and connectors Source: 16

17 Programmable System on Chip Triscend A fixed core (uproc) configurable logic configurable peripherals Can reduce system cost significantly for low and medium volumes 17

Digital Systems Design! Lecture 1 - Introduction!!

Digital Systems Design! Lecture 1 - Introduction!! ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:

More information

Chapter 7 Memory and Programmable Logic

Chapter 7 Memory and Programmable Logic NCNU_2013_DD_7_1 Chapter 7 Memory and Programmable Logic 71I 7.1 Introduction ti 7.2 Random Access Memory 7.3 Memory Decoding 7.5 Read Only Memory 7.6 Programmable Logic Array 77P 7.7 Programmable Array

More information

NIOS II Based Embedded Web Server Development for Networking Applications

NIOS II Based Embedded Web Server Development for Networking Applications NIOS II Based Embedded Web Server Development for Networking Applications 1 Sheetal Bhoyar, 2 Dr. D. V. Padole 1 Research Scholar, G. H. Raisoni College of Engineering, Nagpur, India 2 Professor, G. H.

More information

Digital Systems. Role of the Digital Engineer

Digital Systems. Role of the Digital Engineer Digital Systems Role of the Digital Engineer Digital Design Engineers attempt to clearly define the problem(s) Possibly, break the problem into many smaller problems Engineers then develop a strategy for

More information

Lecture N -1- PHYS 3330. Microcontrollers

Lecture N -1- PHYS 3330. Microcontrollers Lecture N -1- PHYS 3330 Microcontrollers If you need more than a handful of logic gates to accomplish the task at hand, you likely should use a microcontroller instead of discrete logic gates 1. Microcontrollers

More information

9/14/2011 14.9.2011 8:38

9/14/2011 14.9.2011 8:38 Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer

More information

AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)

AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) Samuel Lakeou, University of the District of Columbia Samuel Lakeou received a BSEE (1974) and a MSEE (1976)

More information

Open Flow Controller and Switch Datasheet

Open Flow Controller and Switch Datasheet Open Flow Controller and Switch Datasheet California State University Chico Alan Braithwaite Spring 2013 Block Diagram Figure 1. High Level Block Diagram The project will consist of a network development

More information

Pre-tested System-on-Chip Design. Accelerates PLD Development

Pre-tested System-on-Chip Design. Accelerates PLD Development Pre-tested System-on-Chip Design Accelerates PLD Development March 2010 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 Pre-tested

More information

7a. System-on-chip design and prototyping platforms

7a. System-on-chip design and prototyping platforms 7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit

More information

ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT

ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT 216 ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT *P.Nirmalkumar, **J.Raja Paul Perinbam, @S.Ravi and #B.Rajan *Research Scholar,

More information

Fondamenti su strumenti di sviluppo per microcontrollori PIC

Fondamenti su strumenti di sviluppo per microcontrollori PIC Fondamenti su strumenti di sviluppo per microcontrollori PIC MPSIM ICE 2000 ICD 2 REAL ICE PICSTART Ad uso interno del corso Elettronica e Telecomunicazioni 1 2 MPLAB SIM /1 MPLAB SIM is a discrete-event

More information

Designing an efficient Programmable Logic Controller using Programmable System On Chip

Designing an efficient Programmable Logic Controller using Programmable System On Chip Designing an efficient Programmable Logic Controller using Programmable System On Chip By Raja Narayanasamy, Product Apps Manager Sr, Cypress Semiconductor Corp. A Programmable Logic Controller (PLC) is

More information

Introduction to Programmable Logic Devices. John Coughlan RAL Technology Department Detector & Electronics Division

Introduction to Programmable Logic Devices. John Coughlan RAL Technology Department Detector & Electronics Division Introduction to Programmable Logic Devices John Coughlan RAL Technology Department Detector & Electronics Division PPD Lectures Programmable Logic is Key Underlying Technology. First-Level and High-Level

More information

Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic

Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk How to go

More information

CMS Level 1 Track Trigger

CMS Level 1 Track Trigger Institut für Technik der Informationsverarbeitung CMS Level 1 Track Trigger An FPGA Approach Management Prof. Dr.-Ing. Dr. h.c. J. Becker Prof. Dr.-Ing. Eric Sax Prof. Dr. rer. nat. W. Stork KIT University

More information

Optimising the resource utilisation in high-speed network intrusion detection systems.

Optimising the resource utilisation in high-speed network intrusion detection systems. Optimising the resource utilisation in high-speed network intrusion detection systems. Gerald Tripp www.kent.ac.uk Network intrusion detection Network intrusion detection systems are provided to detect

More information

BUILD VERSUS BUY. Understanding the Total Cost of Embedded Design. www.ni.com/buildvsbuy

BUILD VERSUS BUY. Understanding the Total Cost of Embedded Design. www.ni.com/buildvsbuy BUILD VERSUS BUY Understanding the Total Cost of Embedded Design Table of Contents I. Introduction II. The Build Approach: Custom Design a. Hardware Design b. Software Design c. Manufacturing d. System

More information

Digital Systems. Syllabus 8/18/2010 1

Digital Systems. Syllabus 8/18/2010 1 Digital Systems Syllabus 1 Course Description: This course covers the design and implementation of digital systems. Topics include: combinational and sequential digital circuits, minimization methods,

More information

Introduction to Digital System Design

Introduction to Digital System Design Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital

More information

Lesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education

Lesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: Embedded Systems - , Raj Kamal, Publs.: McGraw-Hill Education Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,

More information

How To Design An Image Processing System On A Chip

How To Design An Image Processing System On A Chip RAPID PROTOTYPING PLATFORM FOR RECONFIGURABLE IMAGE PROCESSING B.Kovář 1, J. Kloub 1, J. Schier 1, A. Heřmánek 1, P. Zemčík 2, A. Herout 2 (1) Institute of Information Theory and Automation Academy of

More information

Seeking Opportunities for Hardware Acceleration in Big Data Analytics

Seeking Opportunities for Hardware Acceleration in Big Data Analytics Seeking Opportunities for Hardware Acceleration in Big Data Analytics Paul Chow High-Performance Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Toronto Who

More information

Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students

Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Session: 2220 Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Adam S. El-Mansouri, Herbert L. Hess, Kevin M. Buck, Timothy Ewers Microelectronics

More information

Implementation of Full -Parallelism AES Encryption and Decryption

Implementation of Full -Parallelism AES Encryption and Decryption Implementation of Full -Parallelism AES Encryption and Decryption M.Anto Merline M.E-Commuication Systems, ECE Department K.Ramakrishnan College of Engineering-Samayapuram, Trichy. Abstract-Advanced Encryption

More information

Implementation and Design of AES S-Box on FPGA

Implementation and Design of AES S-Box on FPGA International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 232-9364, ISSN (Print): 232-9356 Volume 3 Issue ǁ Jan. 25 ǁ PP.9-4 Implementation and Design of AES S-Box on FPGA Chandrasekhar

More information

Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and

Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and Simulink targeting ASIC/FGPA. Previously Worked as logic

More information

Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com

Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and

More information

White Paper 40-nm FPGAs and the Defense Electronic Design Organization

White Paper 40-nm FPGAs and the Defense Electronic Design Organization White Paper 40-nm FPGAs and the Defense Electronic Design Organization Introduction With Altera s introduction of 40-nm FPGAs, the design domains of military electronics that can be addressed with programmable

More information

Design of a High Speed Communications Link Using Field Programmable Gate Arrays

Design of a High Speed Communications Link Using Field Programmable Gate Arrays Customer-Authored Application Note AC103 Design of a High Speed Communications Link Using Field Programmable Gate Arrays Amy Lovelace, Technical Staff Engineer Alcatel Network Systems Introduction A communication

More information

Lecture 1. Introduction to Embedded Computer Systems

Lecture 1. Introduction to Embedded Computer Systems CENG 314 Lecture 1 Introduction to Embedded Computer Systems Asst. Prof. Tolga Ayav, Ph.D. Department of Computer Engineering System A system has a set of one or more inputs entering a black box and a

More information

Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

More information

RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition

RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston

More information

Software Defined Radio Architecture for NASA s Space Communications

Software Defined Radio Architecture for NASA s Space Communications From July 2007 High Frequency Electronics Copyright 2007 Summit Technical Media Software Defined Radio Architecture for NASA s Space Communications By Maximilian C. Scardelletti, Richard C. Reinhart, Monty

More information

DRAFT 18-09-2003. 2.1 Gigabit network intrusion detection systems

DRAFT 18-09-2003. 2.1 Gigabit network intrusion detection systems An Intrusion Detection System for Gigabit Networks (Working paper: describing ongoing work) Gerald Tripp Computing Laboratory, University of Kent. CT2 7NF. UK e-mail: G.E.W.Tripp@kent.ac.uk This draft

More information

Solutions for Increasing the Number of PC Parallel Port Control and Selecting Lines

Solutions for Increasing the Number of PC Parallel Port Control and Selecting Lines Solutions for Increasing the Number of PC Parallel Port Control and Selecting Lines Mircea Popa Abstract: The paper approaches the problem of control and selecting possibilities offered by the PC parallel

More information

On the use of programmable logic in FabLabs

On the use of programmable logic in FabLabs 09.09.2013 Self introduction Electrical Engineer Self employed: Focus: Embedded Systems Motivation for being here: Providing and getting new ideas, make an offer, meeting interesting people Source: http://opensourceecology.org

More information

Ingar Fredriksen AVR Applications Manager. Tromsø August 12, 2005

Ingar Fredriksen AVR Applications Manager. Tromsø August 12, 2005 Ingar Fredriksen AVR Applications Manager Tromsø August 12, 2005 Atmel Norway 2005 Atmel Norway 2005 The history of computers Foundation for modern computing 3 An automatic computing machine must have:

More information

Low-resolution Image Processing based on FPGA

Low-resolution Image Processing based on FPGA Abstract Research Journal of Recent Sciences ISSN 2277-2502. Low-resolution Image Processing based on FPGA Mahshid Aghania Kiau, Islamic Azad university of Karaj, IRAN Available online at: www.isca.in,

More information

40G MACsec Encryption in an FPGA

40G MACsec Encryption in an FPGA 40G MACsec Encryption in an FPGA Dr Tom Kean, Managing Director, Algotronix Ltd, 130-10 Calton Road, Edinburgh EH8 8JQ United Kingdom Tel: +44 131 556 9242 Email: tom@algotronix.com February 2012 1 MACsec

More information

Compiling PCRE to FPGA for Accelerating SNORT IDS

Compiling PCRE to FPGA for Accelerating SNORT IDS Compiling PCRE to FPGA for Accelerating SNORT IDS Abhishek Mitra Walid Najjar Laxmi N Bhuyan QuickTime and a QuickTime and a decompressor decompressor are needed to see this picture. are needed to see

More information

Enhancing High-Speed Telecommunications Networks with FEC

Enhancing High-Speed Telecommunications Networks with FEC White Paper Enhancing High-Speed Telecommunications Networks with FEC As the demand for high-bandwidth telecommunications channels increases, service providers and equipment manufacturers must deliver

More information

Android Controlled Based Interface

Android Controlled Based Interface Android Controlled Based Interface Objective Fix Foba Build Rofi (Fifth Generation Robot) Develop, Build, and Implement a Dynamic Balanced Biped Robot Table of Contents Objective... 1 Android Controlled

More information

A First Course in Digital Design Using VHDL and Programmable Logic

A First Course in Digital Design Using VHDL and Programmable Logic A First Course in Digital Design Using VHDL and Programmable Logic Shawki Areibi Abstract Present industry practice has created a high demand for systems designers with knowledge and experience in using

More information

Architectures and Platforms

Architectures and Platforms Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation

More information

Moving Beyond CPUs in the Cloud: Will FPGAs Sink or Swim?

Moving Beyond CPUs in the Cloud: Will FPGAs Sink or Swim? Moving Beyond CPUs in the Cloud: Will FPGAs Sink or Swim? Successful FPGA datacenter usage at scale will require differentiated capability, programming ease, and scalable implementation models Executive

More information

White Paper FPGA Performance Benchmarking Methodology

White Paper FPGA Performance Benchmarking Methodology White Paper Introduction This paper presents a rigorous methodology for benchmarking the capabilities of an FPGA family. The goal of benchmarking is to compare the results for one FPGA family versus another

More information

International Journal of Advancements in Research & Technology, Volume 2, Issue3, March -2013 1 ISSN 2278-7763

International Journal of Advancements in Research & Technology, Volume 2, Issue3, March -2013 1 ISSN 2278-7763 International Journal of Advancements in Research & Technology, Volume 2, Issue3, March -2013 1 FPGA IMPLEMENTATION OF HARDWARE TASK MANAGEMENT STRATEGIES Assistant professor Sharan Kumar Electronics Department

More information

Sistemas Digitais I LESI - 2º ano

Sistemas Digitais I LESI - 2º ano Sistemas Digitais I LESI - 2º ano Lesson 6 - Combinational Design Practices Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA - PLDs (1) - The

More information

Chapter 2 Features of Embedded System

Chapter 2 Features of Embedded System Chapter 2 Features of Embedded System Abstract This chapter will introduce the basic elements of embedded systems (or dedicated systems). The integrated control systems represent one of the areas of modern

More information

DNA Mapping/Alignment. Team: I Thought You GNU? Lars Olsen, Venkata Aditya Kovuri, Nick Merowsky

DNA Mapping/Alignment. Team: I Thought You GNU? Lars Olsen, Venkata Aditya Kovuri, Nick Merowsky DNA Mapping/Alignment Team: I Thought You GNU? Lars Olsen, Venkata Aditya Kovuri, Nick Merowsky Overview Summary Research Paper 1 Research Paper 2 Research Paper 3 Current Progress Software Designs to

More information

Boole-WebLab-Deusto: Integration of a Remote Lab in a Tool for Digital Circuits Design

Boole-WebLab-Deusto: Integration of a Remote Lab in a Tool for Digital Circuits Design Boole-WebLab-Deusto: Integration of a Remote Lab in a Tool for Digital Circuits Design Javier García-Zubía (IEEE Senior Member), Ignacio Angulo, Luis Rodríguez-Gil Faculty of Engineering University of

More information

Microcontroller Based Low Cost Portable PC Mouse and Keyboard Tester

Microcontroller Based Low Cost Portable PC Mouse and Keyboard Tester Leonardo Journal of Sciences ISSN 1583-0233 Issue 20, January-June 2012 p. 31-36 Microcontroller Based Low Cost Portable PC Mouse and Keyboard Tester Ganesh Sunil NHIVEKAR *, and Ravidra Ramchandra MUDHOLKAR

More information

FPGA Implementation of Boolean Neural Networks using UML

FPGA Implementation of Boolean Neural Networks using UML FPGA Implementation of Boolean Neural Networks using UML Roman Kohut,, Bernd Steinbach, Dominik Fröhlich Freiberg University of Mining and Technology Institute of Computer Science Freiberg (Sachs), Germany

More information

KEEP IT SYNPLE STUPID

KEEP IT SYNPLE STUPID Utilizing Programmable Logic for Analyzing Hardware Targets Dmitry Nedospasov SHORT DESCRIPTION Hardware security analysis differs from software security analysis primarily in the tools

More information

Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards

Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards Points ddressed in this Lecture Lecture 8: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Read-only memory Implementing logic with ROM Programmable logic

More information

FPGA Music Project. Matthew R. Guthaus. Department of Computer Engineering, University of California Santa Cruz http://vlsida.soe.ucsc.

FPGA Music Project. Matthew R. Guthaus. Department of Computer Engineering, University of California Santa Cruz http://vlsida.soe.ucsc. Department of Computer Engineering, University of California Santa Cruz http://vlsida.soe.ucsc.edu Biographic Info 2006 PhD, University of Michigan in Electrical Engineering 2003-2005 Statistical Physical

More information

A universal forensic solution to read memory chips developed by the Netherlands Forensic Institute. The NFI Memory Toolkit II

A universal forensic solution to read memory chips developed by the Netherlands Forensic Institute. The NFI Memory Toolkit II A universal forensic solution to read memory chips developed by the Netherlands Forensic Institute The NFI Memory Toolkit II The NFI Memory Toolkit II The NFI Memory Toolkit II is a universal forensic

More information

A Second Undergraduate Course in Digital Logic Design: The Datapath+Controller-Based Approach

A Second Undergraduate Course in Digital Logic Design: The Datapath+Controller-Based Approach A Second Undergraduate Course in Digital Logic Design: The Datapath+Controller-Based Approach Mitchell A. Thornton 1 and Aaron S. Collins 2 Abstract A second undergraduate course in digital logic design

More information

Electronic system-level development: Finding the right mix of solutions for the right mix of engineers.

Electronic system-level development: Finding the right mix of solutions for the right mix of engineers. Electronic system-level development: Finding the right mix of solutions for the right mix of engineers. Nowadays, System Engineers are placed in the centre of two antagonist flows: microelectronic systems

More information

SoC Curricula at Tallinn Technical University

SoC Curricula at Tallinn Technical University SoC Curricula at Tallinn Technical University Margus Kruus, Kalle Tammemäe, Peeter Ellervee Tallinn Technical University Phone: +372-6202250, Fax: +372-6202246 kruus@cc.ttu.ee nalle@cc.ttu.ee lrv@cc.ttu.ee

More information

The Evolution of CCD Clock Sequencers at MIT: Looking to the Future through History

The Evolution of CCD Clock Sequencers at MIT: Looking to the Future through History The Evolution of CCD Clock Sequencers at MIT: Looking to the Future through History John P. Doty, Noqsi Aerospace, Ltd. This work is Copyright 2007 Noqsi Aerospace, Ltd. This work is licensed under the

More information

Let s put together a Manual Processor

Let s put together a Manual Processor Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce

More information

Implementing a Digital Answering Machine with a High-Speed 8-Bit Microcontroller

Implementing a Digital Answering Machine with a High-Speed 8-Bit Microcontroller Implementing a Digital Answering Machine with a High-Speed 8-Bit Microcontroller Zafar Ullah Senior Application Engineer Scenix Semiconductor Inc. Leo Petropoulos Application Manager Invox TEchnology 1.0

More information

Modeling a GPS Receiver Using SystemC

Modeling a GPS Receiver Using SystemC Modeling a GPS Receiver using SystemC Modeling a GPS Receiver Using SystemC Bernhard Niemann Reiner Büttner Martin Speitel http://www.iis.fhg.de http://www.iis.fhg.de/kursbuch/kurse/systemc.html The e

More information

Reconfigurable Architecture Requirements for Co-Designed Virtual Machines

Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Kenneth B. Kent University of New Brunswick Faculty of Computer Science Fredericton, New Brunswick, Canada ken@unb.ca Micaela Serra

More information

Handout 17. by Dr Sheikh Sharif Iqbal. Memory Unit and Read Only Memories

Handout 17. by Dr Sheikh Sharif Iqbal. Memory Unit and Read Only Memories Handout 17 by Dr Sheikh Sharif Iqbal Memory Unit and Read Only Memories Objective: - To discuss different types of memories used in 80x86 systems for storing digital information. - To learn the electronic

More information

Development of a Research-oriented Wireless System for Human Performance Monitoring

Development of a Research-oriented Wireless System for Human Performance Monitoring Development of a Research-oriented Wireless System for Human Performance Monitoring by Jonathan Hill ECE Dept., Univ. of Hartford jmhill@hartford.edu Majdi Atallah ECE Dept., Univ. of Hartford atallah@hartford.edu

More information

A DA Serial Multiplier Technique based on 32- Tap FIR Filter for Audio Application

A DA Serial Multiplier Technique based on 32- Tap FIR Filter for Audio Application A DA Serial Multiplier Technique ased on 32- Tap FIR Filter for Audio Application K Balraj 1, Ashish Raman 2, Dinesh Chand Gupta 3 Department of ECE Department of ECE Department of ECE Dr. B.R. Amedkar

More information

Embedded Systems Engineering Certificate Program

Embedded Systems Engineering Certificate Program Engineering Programs Embedded Systems Engineering Certificate Program Accelerate Your Career extension.uci.edu/embedded University of California, Irvine Extension s professional certificate and specialized

More information

Reconfigurable System-on-Chip Design

Reconfigurable System-on-Chip Design Reconfigurable System-on-Chip Design MITCHELL MYJAK Senior Research Engineer Pacific Northwest National Laboratory PNNL-SA-93202 31 January 2013 1 About Me Biography BSEE, University of Portland, 2002

More information

Chapter 5 :: Memory and Logic Arrays

Chapter 5 :: Memory and Logic Arrays Chapter 5 :: Memory and Logic Arrays Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 5- ROM Storage Copyright 2007 Elsevier 5- ROM Logic Data

More information

Programmable Logic Devices: A Test Approach for the Input/Output Blocks and Pad-to-Pin Interconnections

Programmable Logic Devices: A Test Approach for the Input/Output Blocks and Pad-to-Pin Interconnections Programmable Logic Devices: A Test Approach for the Input/Output Blocks and Pad-to-Pin Interconnections Manuel G. Gericota, Gustavo R. Alves Department of Electrical Engineering ISEP Rua Dr. António Bernardino

More information

University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54

University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Fall 2005 Instructor Texts University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Lab: Section 1: OSS LL14 Tuesday

More information

Hardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner

Hardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Hardware Implementations of RSA Using Fast Montgomery Multiplications ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Overview Introduction Functional Specifications Implemented Design and Optimizations

More information

FPGA IMPLEMENTATION OF AN AES PROCESSOR

FPGA IMPLEMENTATION OF AN AES PROCESSOR FPGA IMPLEMENTATION OF AN AES PROCESSOR Kazi Shabbir Ahmed, Md. Liakot Ali, Mohammad Bozlul Karim and S.M. Tofayel Ahmad Institute of Information and Communication Technology Bangladesh University of Engineering

More information

ELEC 5260/6260/6266 Embedded Computing Systems

ELEC 5260/6260/6266 Embedded Computing Systems ELEC 5260/6260/6266 Embedded Computing Systems Spring 2016 Victor P. Nelson Text: Computers as Components, 3 rd Edition Prof. Marilyn Wolf (Georgia Tech) Course Topics Embedded system design & modeling

More information

FPGA-based Multithreading for In-Memory Hash Joins

FPGA-based Multithreading for In-Memory Hash Joins FPGA-based Multithreading for In-Memory Hash Joins Robert J. Halstead, Ildar Absalyamov, Walid A. Najjar, Vassilis J. Tsotras University of California, Riverside Outline Background What are FPGAs Multithreaded

More information

RAM & ROM Based Digital Design. ECE 152A Winter 2012

RAM & ROM Based Digital Design. ECE 152A Winter 2012 RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in

More information

World-wide University Program

World-wide University Program 1 World-wide University Program Preparing Today s Students for Tomorrow s Technology Joe Bungo Manager Americas/Europe R&D Division 2 CONFIDENTIAL ARM Ltd ARM founded in November 1990 Advanced RISC Machines

More information

White Paper Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors

White Paper Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors White Paper Increase Bandwidth in Medical & Industrial Applications With FPGA Co-Processors Introduction Programmable logic devices (PLDs) have long been used as primary and co-processors in telecommunications

More information

IMPLEMENTATION OF FPGA CARD IN CONTENT FILTERING SOLUTIONS FOR SECURING COMPUTER NETWORKS. Received May 2010; accepted July 2010

IMPLEMENTATION OF FPGA CARD IN CONTENT FILTERING SOLUTIONS FOR SECURING COMPUTER NETWORKS. Received May 2010; accepted July 2010 ICIC Express Letters Part B: Applications ICIC International c 2010 ISSN 2185-2766 Volume 1, Number 1, September 2010 pp. 71 76 IMPLEMENTATION OF FPGA CARD IN CONTENT FILTERING SOLUTIONS FOR SECURING COMPUTER

More information

Gates, Circuits, and Boolean Algebra

Gates, Circuits, and Boolean Algebra Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks

More information

Technical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview

Technical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview Technical Note TN-29-06: NAND Flash Controller on Spartan-3 Overview Micron NAND Flash Controller via Xilinx Spartan -3 FPGA Overview As mobile product capabilities continue to expand, so does the demand

More information

Architecture bits. (Chromosome) (Evolved chromosome) Downloading. Downloading PLD. GA operation Architecture bits

Architecture bits. (Chromosome) (Evolved chromosome) Downloading. Downloading PLD. GA operation Architecture bits A Pattern Recognition System Using Evolvable Hardware Masaya Iwata 1 Isamu Kajitani 2 Hitoshi Yamada 2 Hitoshi Iba 1 Tetsuya Higuchi 1 1 1-1-4,Umezono,Tsukuba,Ibaraki,305,Japan Electrotechnical Laboratory

More information

Digital Design and Synthesis INTRODUCTION

Digital Design and Synthesis INTRODUCTION Digital Design and Synthesis INTRODUCTION The advances in digital design owe its progress to 3 factors. First the acceleration at which the CMOS technology has advanced in last few decades and the way

More information

Custom design services

Custom design services Custom design services Your partner for electronic design services and solutions Barco Silex, Barco s center of competence for micro-electronic design, has established a solid reputation in the development

More information

Thanks, But No Thanks

Thanks, But No Thanks Thanks, But No Thanks Current Cryptographic Standards Are Sufficient for Software Dan Shumow MSR Security and Cryptography Group Microsoft Research Introduction Disclaimer: I am a Software Developer, so

More information

Systemy wbudowane. Współczesne technologie implementacji mikrokontrolerów i systemów wbudowanych. Copyright 2007 Frank Vahid

Systemy wbudowane. Współczesne technologie implementacji mikrokontrolerów i systemów wbudowanych. Copyright 2007 Frank Vahid Systemy wbudowane Współczesne technologie implementacji mikrokontrolerów i systemów wbudowanych dr inż. Ignacy Pardyka, UJK Kielce Materiały źródłowe:. Slides to accompany the textbook, First Edition,

More information

LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER

LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER OBJECTIVES 1. Learn the basic elements of VHDL that are implemented in Warp. 2. Build a simple application using VHDL and

More information

SPI Flash Programming and Hardware Interfacing Using ispvm System

SPI Flash Programming and Hardware Interfacing Using ispvm System March 2005 Introduction Technical Note TN1081 SRAM-based FPGA devices are volatile and require reconfiguration after power cycles. This requires external configuration data to be held in a non-volatile

More information

An Open Platform for Development of Network Processing Modules in Reprogrammable Hardware

An Open Platform for Development of Network Processing Modules in Reprogrammable Hardware An Open Platform for Development of Network Processing s in Reprogrammable Hardware John W. Lockwood Department of Computer Science Applied Research Lab Washington University 1 Brookings Drive Saint Louis,

More information

International Workshop on Field Programmable Logic and Applications, FPL '99

International Workshop on Field Programmable Logic and Applications, FPL '99 International Workshop on Field Programmable Logic and Applications, FPL '99 DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconægurable Systems? Kiran Bondalapati and

More information

Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah

Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah (DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de NIOS II 1 1 What is Nios II? Altera s Second Generation

More information

AES1. Ultra-Compact Advanced Encryption Standard Core. General Description. Base Core Features. Symbol. Applications

AES1. Ultra-Compact Advanced Encryption Standard Core. General Description. Base Core Features. Symbol. Applications General Description The AES core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. Basic core is very small (start at 800 Actel tiles). Enhanced versions

More information

CHAPTER 5 FINITE STATE MACHINE FOR LOOKUP ENGINE

CHAPTER 5 FINITE STATE MACHINE FOR LOOKUP ENGINE CHAPTER 5 71 FINITE STATE MACHINE FOR LOOKUP ENGINE 5.1 INTRODUCTION Finite State Machines (FSMs) are important components of digital systems. Therefore, techniques for area efficiency and fast implementation

More information

Implementation of emulated digital CNN-UM architecture on programmable logic devices and its applications

Implementation of emulated digital CNN-UM architecture on programmable logic devices and its applications Implementation of emulated digital CNN-UM architecture on programmable logic devices and its applications Theses of the Ph.D. dissertation Zoltán Nagy Scientific adviser: Dr. Péter Szolgay Doctoral School

More information

SYSTEM-ON-PROGRAMMABLE-CHIP DESIGN USING A UNIFIED DEVELOPMENT ENVIRONMENT. Nicholas Wieder

SYSTEM-ON-PROGRAMMABLE-CHIP DESIGN USING A UNIFIED DEVELOPMENT ENVIRONMENT. Nicholas Wieder SYSTEM-ON-PROGRAMMABLE-CHIP DESIGN USING A UNIFIED DEVELOPMENT ENVIRONMENT by Nicholas Wieder A thesis submitted to the faculty of The University of North Carolina at Charlotte in partial fulfillment of

More information

路 論 Chapter 15 System-Level Physical Design

路 論 Chapter 15 System-Level Physical Design Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS

More information

All Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule

All Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule All Programmable Logic Hans-Joachim Gelke Institute of Embedded Systems Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries www.ines.zhaw.ch Research: Education:

More information