LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER
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1 LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER OBJECTIVES 1. Learn the basic elements of VHDL that are implemented in Warp. 2. Build a simple application using VHDL and its simulation. 3. Being able to programming the GAL IC using All-11 Universal Programmer. 4. Being able to create other applications using IC GAL22V10D. INTRODUCTION Introducing VHDL The following will explain the basic elements of VHDL which include: identifier, data objects, data types, entity, architecture and package. 1. Identifier Identifier in VHDL consists of one or more characters which form the character of letters, digits or underscore with the following rules: The characters that are allowed are uppercase (A Z), lowercase (a z), letters (0...9) and underscore (_). The first character must be a letter. The last character may not be an underscore (_), use two underscore character ( ) are also not allowed. The use of uppercase and lowercase letters are considered equal (not case sensitive). Comments in VHDL start with a Data Objects In the third known VHDL data objects are: Constant, Variable and Signal Constant Constant object can store a value which is defined as a constant declaration. Predefined value cannot be changed during the design process.. Declaration: constant identifier[,identifier..]:type[:value]; Example: constant bus_width: integer := 8; Variable Object variable can store a given value at design time, and that value can be changed at any time of the design. Declaration: variable identifier[,identifier..]:type[:value]; Example: variable ctrl_bits: std_logic; Signal Signal can be equated with the object variable, the difference is that the signal can store or release the logic value, while variables cannot, therefore, the signal can be realized in the memory element. Declaration: signal identifier[,identifier..]:type[:value]; Example: signal con: std_logic;
2 3. Data Types In the Warp, has defined several types of data that is often used, namely: integer, boolean, bit, character, string, bit_vector, std_logic and std_logic_vector. 4. Entity VHDL is composed by the couple of entity and its architecture, defines the design entity I/O or interface, while the architecture stated content or conduct of the design. Entity and architecture pair may be used as a complete design or can be used also as a component. Declaration of the entity program code is: ENTITY entity-name IS PORT [signal][sig-name,..]:[direction] type; [;signal[sig-name,..]:[direction] type].. ); END entity-name; Name of the entity that is created will be used as a reference for its architecture. Entity declare the port, the port is an object of class signal is defined in the entity. Each port has a port name, mode and type. Type used on the port is in (default), out, in-out, and buffer. 5. Architecture Architecture to describe the behavior of a design/process and the structure of the entity. Program code of the architecture declaration is: ARCHITECTURE architecture-name OF entity-name IS [type-declarations] [signal-declarations] [constant-declarations] BEGIN [architecture definition] END architecture-name; 6. Package A package can declare a partner entity and component architecture, types, constants or functions that these items can be used in other designs. Package often written before the entity and architecture. In order for a design can use a package that has been made, then the design should call the package that will be used by using the USE clause. 7. Generic Array Logic (GAL) GAL is an IC-type most widely used PLD, GAL produced by many IC vendors (eg, Cypress, Lattice and Texas Instruments). All digital expressions can be represented using the sum of product (SOP), therefore, using an array of AND/OR can be programmed, will be obtained much
3 desired digital circuit applications. GAL contains an array of AND / OR (Fig. Fig. III-1), the AND array, all the input and its complement is connected to the AND gate, the output of the AND array (product) is connected to the OR gate (sum). Fig. III-1. GAL/PAL s Structure At GAL, AND array input can be disconnected or reconnected to the programmed path. For example, if the desired logic equations the relationship array input AND the GAL can be demonstrated as shown Fig. III-2. Fig. III-2. Programming Input of AND Gate IC PLD on earlier, the relationship input AND array is made of fuse that will break if the drain voltage is high. With this fuse, then the AND array input cannot be reprogrammed. IC PLD generation now use EEPROM, so that the AND array input can be reprogrammed. To program an IC PLD, can be done by writing programs using the VHDL compilation and enter the results into the IC using a Programmer. One of the commonly used IC-Programmer is All-11 Universal Programmer who has the ability to program the PLD IC, MCU, EPROM, EEPROM, etc. REQUIREMENT 1. Full pack of HBE-LogicCircuit-Digital
4 2. Cooper Cable 3. IC GAL22V10D 4. IC Programmer ALL PC with WARPR 6.3 Galaxy and Active-HDL Simulator PRE-LAB WORK TASK 1. Read the Lab Work s Technical Guide first! 2. Learn the Data Sheet of each ICs of Logic Gates used in this lab work! 3. What is VHDL? What is/are the difference(s) with Verilog? 4. What is the difference(s) of data types of std_logic and std_logic_vector? Explain! 5. Write the program code in VHDL to create a simple application of 3- inputs OR gate, complete with library, entity and its architecture! 6. Explain the working principle of PAL/GAL! Search the datasheet of IC GAL22V10D! 7. Describe and explain the function of the pins of the IC GAL22V10D! EXPERIMENT 1 : VHDL [Trial 1] Making 2-Input AND Gate Using VHDL [Preparation] I/O Device - Module - Others PC with WARPR 6.3 Galaxy [Procedure] 1. Open Galaxy Software 2. Create a new project via File menu New, then select Project [Target - Device] and click Ok 3. Select the Project Type VHDL. 4. Enter the name of the project "and3in" 5. Enter Project Path to the directory: "C:\Rangkaian Logika\VHDL\ and3in" 6. Click Next to get to the Add Files Wizard. Add Files Wizard is used to add the VHDL file into the Project. Just ignore the dialog and click Next to go to Target Device Wizard. 7. Choose the device by selecting the SPLD (Small PLDs) c22v10, on select Package PALC22V10D-25PC (Fig. Fig. III-3) 8. Click Finish to create the project 9. Click Yes to save the project 10. Create a new file via the File -> New 11. Select Text File, then click Ok, then you will see a text editor as shown in Fig. III-3
5 Fig. III-3. Device Option Fig. III-4. Blank Editor 12. Save the empty file via the File -> Save, put in a directory with the project file "and3in.pfg" and name the file "and2in.vhd 13. Next is to write entity, we will create an entity to an AND gate with 2 inputs, declared entity name, direction and data type of each port to be used. Type the following entity: entity and2in is port( input: in std_logic_vector(1 downto 0); output: out std_logic); end and2in; 14. The next step is to write AND 2 Architecture of the input that we make. Architecture defines the behavior of the components are made, and it's always been after the entity, type the following 2 input AND architecture:
6 architecture archand2in of and2in is begin and2in: process (input) begin if (input = "00") then output <= '0'; elsif (input = "01") then output <= '0'; elsif (input = "10") then output <= '0'; elsif (input = "11") then output <= '1'; end if; end process; end archand2in; 15. The next step is to write Package of 2 input AND gate before, write the name and2in_pkg Package with program code below! Put before the entity! package and2in_pkg is component and2in port(input: in std_logic_vector(1 downto 0); output: out std_logic); end component; end and2in_pkg; 16. The next step is to write Library, type library in accordance with the code below! Put one before Package and one before the Entity! library ieee; use ieee.std_logic_1164.all; [Trial 2] Making 3-Input AND Gate Using VHDL [Preparation] I/O Device - Module - Others PC with WARPR 6.3 Galaxy [Procedure] Fig. III-5. 3-Input AND Gate Using 2-Input AND Gate
7 1. Create a new text file and name it "and3in.vhd", put in the same folder with the file Project "and3in.pfg"! 2. Write the library, entity and its architecture with the following program code: library ieee; use ieee.std_logic_1164.all; use work.and2in_pkg.all; entity and3in is port ( a,b,c: in std_logic; y: out std_logic); attribute pin_numbers of and3in:entity is " a:1 b:3 c:5 y:15 "; end and3in; architecture archand3in of and3in is signal con : std_logic; begin and_1: and2in port map ( input(0) => a, input(1) => b, output => con ); and_2: and2in port map ( input(0) => con, ); end archand3in; input(1) => c, output => y 3. The next step is adding a VHDL file "and2in.vhd" and "and3in.vhd" into the project. Add the file through Project -> Add Files..., when they are finished, click Ok 4. The next step is to make the file "and3in.vhd" as the Top Level. Create a file "and3in" as the top level via the right click and choose Set Top 5. In order for the compilation process goes as expected, needs to be done in the compiler settings, click Project -> Compiler Options..., in I / O, Unused Outputs: select "0", and in Simulation, Timing Model, select "Active-HDLSIM/Active - VHDL " 6. Then compile the project by Compile -> Project. It will produce a new file with the name "and3in.jed" (this file will be used to download the programs to IC). [Trial 3] Simulating Active-HDL Sim [Preparation] I/O Device - Module -
![Others PC with WARPR 6.3 Galaxy and Active-HDL Simulator [Procedure] 1. Open the Active-HDL Sim application from Tools Active-HDL Sim 2. Open the and3in.](/docs-images/39/18891696/images/8-0.png "vhd file at the address \"C:\Rangkaian Logika\VHDL \ and3in\vhd\" through the menu File -> Open VHDL 3. Then a window will appear as shown below: Fig. III-6. Active-HDL Sim 4.")
8 Others PC with WARPR 6.3 Galaxy and Active-HDL Simulator [Procedure] 1. Open the Active-HDL Sim application from Tools Active-HDL Sim 2. Open the and3in.vhd file at the address "C:\Rangkaian Logika\VHDL \ and3in\vhd" through the menu File -> Open VHDL 3. Then a window will appear as shown below: Fig. III-6. Active-HDL Sim 4. Add the signal to be simulated by selecting Waveform -> Add Signals..., add the signals a, b, c and y into the simulation by double-clicking Fig. III-7. Signal Option 5. When finished click Add 6. At a signal, set stimulator by Right-click select stimulators..., the stimulator type: select Clock, 2000ns Rate this wavelength, and then click Apply, once completed, click Close
9 Fig. III-8. Stimulators 7. In the same way, set b stimulators for the type of clock signals with a wavelength of 1000ns 8. In the same way, set c stimulators for the type of clock signals with a wavelength of 500ns 9. On the toolbar entry 100ns, enter a new value of 4000ns 10. On the toolbar, click Run Until 11. By adjusting the image through the Zoom in and Zoom out, then you will get the following image simulation: Fig. III-9. Simulation Result Table III-1. Result Table of 3-Input AND Gate Using Active-HDL Sim Input Output a b c y EXPERIMENT 2 : IC GAL PROGRAMMING [Trial 4] IC GAL Programming Using Universal Programmer [Preparation] I/O Device Slide Switch (SW1, SW2, SW3), LED (D1)
![Module - Others PC with IC Programmer ALL-11, Cable (to connect I/O device with IC), Breadboard (to implant the IC) [Procedure] 1. Turn off the All-11 Universal Programmer 2.](/docs-images/39/18891696/images/10-0.png "Place the IC GAL on the All-11 Universal Programmer 3. Turn on the All-11 Universal Programmer 4. Open the file \"access.exe\"! 5.")
10 Module - Others PC with IC Programmer ALL-11, Cable (to connect I/O device with IC), Breadboard (to implant the IC) [Procedure] 1. Turn off the All-11 Universal Programmer 2. Place the IC GAL on the All-11 Universal Programmer 3. Turn on the All-11 Universal Programmer 4. Open the file "access.exe"! 5. On the Device menu, choose a product developed by Lattice, and select GAL22V10 (no UES) Fig. III-10. Device Menu 6. After that will appear the window below: Fig. III-11. Download Window
11 7. Delete the contents of IC GAL through the Erase menu! 8. Select File, then select Load JEDEC file, locate the address of where you save the file "and3in.jed"! 9. Do programming by selecting menu Program 10. Turn off the All-11 Universal Programmer 11. Take the IC GAL from the All-11 Universal Programmer 12. Place the IC GAL is already programmed on the breadboard, rangkaikan correctly, point output (15 feet) to an anode of the LED on the feet! 13. Complete the following table, compared with the simulation results in table: Table III-2. Result Table of 3-Input AND Gate Using IC GAL Input Output a b c y ASSIGNMENT 1. Make applications of 5-input OR gate! 2. Consider the following code: entity and2in is port( input: in std_logic_vector(1 downto 0); output: out std_logic); end and2in; 3. Explain the purpose of the code: "input: in std_logic_vector (1 down to 0)"! 4. Explain the difference with the code: "output: out std_logic"! 5. Explain the difference in the working principle of the PAL /GAL compared to the FPGA! 6. Make the application program code Demultiplexer 2 to 4 using VHDL, making them into a package! 7. Make an application program Demultiplexer 4 to 16 by utilizing the package at number 4! Simulate it! Include a print-out simulation results into a report!
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