EE-612: Nanoscale Transistors (Advanced VLSI Devices) Spring 2005 Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA 765-494-3515 lundstro@purdue.edu 1
evolution of silicon technology Bell Labs, 1947 Intel, 2002 2
Evolution of silicon technology Minimum Feature Size 100 µ m 1 10 µ m 1K 1M 1 µm 100 nm 1G 1T? 10 nm 1P 1 nm 1950 1970 1990 2010 2030 2050 Year 2004 ITRS: 2004: 37 nm 2006: 28 nm 2008: 22 nm 2010: 18 nm 2014: 11 nm 2016: 9 nm 2018: 7 nm www.public.itrs.net 3
course objectives» To understand nanoscale MOSFET device physics» To appreciate how device performance affects circuits and systems» To understand device scaling challenges» To be introduced to new material/device approaches 4
course prerequisites» Introductory level understanding of semiconductor physics and devices as well as basic electronic circuits. (EE255 and EE305/606 at Purdue) (basic MOS physics, devices, and CMOS circuits will be briefly reviewed) 5
course outline Part 1: Sub-micron MOSFETs, Circuits, and Systems 10 weeks 2 exams Part 2: Nanoscale MOSFETs 5 weeks final exam Part 3: Supplemental Seminars online at www.nanohub.org live 6
course text Fundamentals of Modern VLSI Devices Yuan Taur and Tak Ning Cambridge Univ. Press, 1998 www.cup.cam.ac.uk/ 7
course grading Exam 1: 25% -classic, long-channel MOSFETs Exam 2: 25% -submicron MOSFETs, circuits and systems Homework: 25% Final: 25% -nanoscale MOSFETs 8
course overview Part 1a: -introduction -semiconductor equations / device simulation -1D MOS electrostatics / capacitors -polysilicon gates / non-equilibrium effects MOSFET IV: exact, square law, bulk charge ballistic velocity saturation subthreshold conduction Vt, body effect, effective mobility 9
semiconductor equations conservation laws: r D = ρ r ( J q)= G R n r ( J q)= G R p n, p,v ( ) ( ) constitutive relations: r r r D = κε 0 E = κε 0 V ρ = q( p n + N D+ N ) A r r r J n = nqµ n E + qd n n r r r J p = pqµ p E qd p p R = f (n, p) etc. 10
device simulation MINIMOS 6.0 * SIMPLE MINIMOS SIMULATION DEVICE CHANNEL=N GATE=NPOLY + TOX=150.E-8 W=1.E-4 L=0.85E-4 BIAS UD=4. UG=1.5 PROFILE NB=5.2E16 ELEM=AS DOSE=2.E15 + TOX=500.E-8 AKEV=160. + TEMP=1050. TIME=2700 IMPLANT ELEM=B DOSE=1.E12 AKEV=12 + TEMP=940 TIME=1000 OPTION MODEL=2-D OUTPUT ALL=YES END 11
1D MOS electrostatics (L >> t ox ) V = 0 V = 0 V G qψ S E C x E FG E F E V V = 0 12
1D MOS electrostatics accumulation flat band depletion/ inversion qψ S E C E C qψ S E C E FG E F E FG E F E F E FG E V E V E V ψ S < 0 ψ S = 0 ψ S > 0 13
Poisson-Boltzmann equation D r = ρ ( J r n q)= G R ( J r p q)= G R ( ) ( ) qψ S E FG E C E F E V d 2 ψ dx = q 2 ε N A e qψ / k BT 1 ( ) n 2 i N A ( e qψ /k BT ) ψ S > 0 14
1D MOS electrostatics log 10 Q S ( ψ S ) C/cm 2 qψ S E C ~ e qψ S /2k B T ~ e qψ S /2k B T E F E G E V ~ ψ S ψ S > 0 ψ S 15
depletion approximation ρ W x qn A qψ S E C E E G E F E V E S W ψ S > 0 16
depletion approximation E E S de dx = qn A ε ψ S = 1 2 E S W ρ W W x W = 2ε Siψ S qn A D S qn A Q S ( ψ S )= qn A W = 2qε Si N A ψ S D S = ε Si E S = ρ S = qn A W 17
δ-depletion approximation log 10 Q S ( ψ S ) C/cm 2 qψ S E C ~ e qψ S /2k B T ~ e qψ S /2k B T E F E G E V Q S = 2qN A ε Si ψ S ψ S > 0 2ψ B ψ S 18
1D MOS electrostatics C Q i acc FB C ox inv depl V G V T V G above threshold: Q i = C ox ( V GS V T ) 19
Inversion layer charge Q = C ( V V )? i ox GS T V GS 1.2V V T = 0.3V Q i 2 10 6 C/cm 2 T ox = 1.5 nm Q i q 1 1013 /cm 2 20
MOSFET IV: low V DS 0 V G V D Q i ( x)= C ox V GS V T V(x) ( ) I D = W Q i ( x)υ x (x) = W Q i ( 0)υ x (0) I D = W C ox ( V GS V T )µ eff E x E x = V DS L I D = W L µ C V eff ox( V GS T )V DS 21
MOSFET IV: high V DS 0 V G V D V( x)= ( V GS V T ) I D = W Q i ( x)υ x (x) = W Q i ( 0)υ x (0) I D = W C ox ( V GS V T )µ eff E x I D = W L µ eff C ox V GS V T ( ) 2 2 ( E x = V V GS T) L 22
MOSFET IV I D V GS I D = W 2L µ C V eff ox( V GS T) 2 square law V DS I D = W L µ C V eff ox( V GS T )V DS 23
real MOSFETs 130 nm technology (L G = 60 nm) Intel Technical J., Vol. 6, May 16, 2002. 24
velocity saturation 1.5V 60nm 25 104 V/cm velocity cm/s ---> 10 7 υ = µe υ = υ sat 10 4 electric field V/cm ---> 25
MOSFET IV: high V DS 0 V G V D I D = W Q i ( x)υ x (x) = W Q i ( 0)υ x (0) I D = W C ox ( V GS V T )υ sat E >>10 4 I D = W υ sat C ox ( V GS V T ) 26
real MOSFETs 130 nm technology (L G = 60 nm) I D W Q i (0)υ sat 1.6 ma/µm Intel Technical J., Vol. 6, May 16, 2002. 27
MOSFET IV: subthreshold Q i Q i = C ox ( V GS V T ) log 10 Q i Q i = C ox ( V GS V T ) Q i ~ e q ( V GS V T )/k B T V T V G V G 28
MOSFET IV: subthreshold 0 V G V D Log 10 I DS --> on-current S > 60 mv/decade off-current V GS --> 29
MOSFETs fundamentals For a review, consult: R. F. Pierret, Semiconductor Device Fundamentals, Addison-Wesley. 30
course overview Part 1b: -2d electrostatics -channel length / effective channel length -parasitic S/D resistance / gate resistance -MOSFET scaling Vt considerations / channel profile design Interconnects CMOS circuits (digital) CMOS systems and ultimate limits CMOS circuits (RF) 31
2D electrostatics reverse short channel effect V T = φ ms + 2ψ B Q S (2ψ B ) C ox V T --> classic short channel effect V T roll-off channel length ---> 32
2D electrostatics M. Ieong, et al., Science, Vol. 306, p. 2058, Dec. 17, 2004 electrostatic integrity 33
device scaling ~ L Each technology generation: L L 2 A A 2 Number of transistors per chip doubles (scaling) (Moore s Law) 34
device scaling Goals of device scaling: shrink size by factor, κ shrink area by κ 2 reduce voltages by factor, κ reduce current by factor, κ result is lower power-delay product, but Off-currents are increasing exponentially! Log 10 I DS --> S > 60 mv/decade V GS --> 35
circuits V DD V DD V IN P V OUT V OUT --> N V DD V IN --> 36
circuit speed V OUT If C load = C G : V IN C load τ = C GV DD I D (on) L υ 0.5 ps --> f = 2000 GHz! 37
interconnects Metal 7 Metal 6 Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 transistor 38
speed τ = C LoadV DD I D (on) speed is controlled by the DC on-current 39
power P1 1) standby power: N1 I D (off) P off = N G I D (off)v DD P1 V dd I charge 2) dynamic power: V in N1 C L P on =α f C TOT V DD 2 I discharge 40
power Power density will increase Power Density (W/cm2) 10000 1000 100 10 1 4004 8008 8080 8086 Rocket Nozzle Nuclear Reactor Hot Plate 8085 286 386 486 P6 Pentium proc 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp 41
course overview Part 2: nanoscale MOSFETs -gate capacitance -gate leakage -high-k gate dielectrics -reliability -SOI technology -SOI devices -strained channel MOSFETs -new channel materials Ballistic MOSFETs 42
nanoscale CMOS 43
gate capacitance 1.2 nm 44
gate capacitance Q i = C ( G V GS V ) T C G = C ox C inv C ox + C inv C ox? C ox = ε ox t ox C inv = ε Si t inv Is t ox >> t inv still a good assumption at the nanoscale? 45
quantum effects classical n(x) = N C F 1/2 [( E F E C )/k B T] energy--> E F n(x) quantum n(x) ~ sin 2 kx 0 W x W x 46
quantum effects n(x) E C E G E F E V ψ S > 0 47
gate leakage Jim Hutchby, 2003 48
SOI technology Device physics: -floating body effects, ideal subthreshold swing Device structures: -partially depleted, fully-depleted, UTB, DG, tri-gate, FinFET, M. Ieong, et al., Science, Vol. 306, p. 2058, Dec. 17, 2004 49
strained channel MOSFETs Strained Silicon Silicon germanium Rim, et al., 1998 IEDM 50
ballistic MOSFETs L = 10 nm n(x, E) 51
course overview Part 3: - a collection of seminars on nanoscale CMOS and beyond 52
ultimate CMOS Gate Source Drain TSi=7nm Lgate=6nm L ~ 6 nm IBM (2002) Jim Hutchby, 2003 Berkeley FinFET Intel tri-gate 53
carbon nanotube transistors? Source Drain Gate 8nm HfO 2 CNT Pd CNT Pd SiO 2 50nm p ++ Si Stanford, Purdue, Harvard, 2004 Delft, 1998 54
molecular transistors? G D S 55
EE-612 at the intersection of: -devices and circuits -microelectronics and nanoelectronics 56