Lecture 090 Large Signal MOSFET Model (3/24/10) Page 090-1

Transcription

1 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-1 LECTURE 9 LARGE SIGNAL MOSFET MODEL LECTURE ORGANIZATION Outline Introduction to modeling Operation of the MOS transistor Simple large signal model (SAH model) Subthreshold model Short channel, strong inversion model Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages and CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-2 INTRODUCTION TO MODELING Models Suitable for Understanding Analog Design The model required for analog design with CMOS technology is one that leads to understanding and insight as distinguished from accuracy. Technology Understanding and Usage Updating Model Thinking Model Simple, ±1% to ±5% accuracy Updating Technology Comparison of simulation with expectations Design Decisions- "What can I change to accomplish...?" Expectations "Ballpark" Computer Simulation Extraction of Simple Model Parameters from Computer Models Refined and optimized design Fig.3.-2 This lecture is devoted to the simple model suitable for design not using simulation. CMOS Analog Circuit Design P.E. Allen - 21

2 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-3 Categorization of Electrical Models Linearity Linear Nonlinear Time Independent Small-signal, midband R in, A v, R out (.TF) DC operating point = f(v D,v G,v S,v B ) (.OP) Based on the simulation capabilities of SPICE. Time Dependence Time Dependent Small-signal frequency response-poles and zeros (.AC) Large-signal transient response - Slew rate (.TRAN) CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-4 OPERATION OF THE MOS TRANSISTOR Formation of the Channel for an Enhancement MOS Transistor Subthreshold (V G <V T ) V B = Threshold (V G =V T ) V B = V S = V G < V T V D = ;; n + ;; Depletion Region V S = V G =V T V D = ;; Inverted Region ;; Strong Threshold (V G >V T ) V B = V S = V G >V T V D = n + ;; ; Inverted Region Fig CMOS Analog Circuit Design P.E. Allen - 21

3 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-5 Transconductance Characteristics of an Enhancement NMOSFET when V DS =.1V V GS V T : V B = V S = v G =V T V D =.1V ;; ;; Depletion Region V GS =2V T : V B = VS = V G = 2V T V D =.1V ;; Inverted Region ;; V GS =3V T : V B = V S = V G = 3V T V D =.1V ;; Inverted Region V T V T V T 2V T 3V T 2V T 3V T 2V T 3V T v GS v GS v GS Fig CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-6 Output Characteristics of the Enhancement NMOS Transistor for V GS = 2V T V DS =: V DS =.5V T : V B = V B = V S = v G =2V T VD = V ;; Inverted Region ;; V S = V G = 2V T V D =.5V T ;; ;; Channel current V DS =V T : V B = V S = V G = 2V T V D =V T A depletion region ; n + forms between the drain and channel ;; V GS = 2V T.5V T V T V GS = 2V T.5V T V T V GS = 2V T.5V T V T Fig CMOS Analog Circuit Design P.E. Allen - 21

4 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-7 Output Characteristics of the Enhanced NMOS when = 2V T V GS =V T : V GS =2V T : V B = V B = V S = v G =V T V D = 2V T ;; ;; V S = V G = 2V T V D = 2V T ;; n + ;; ; V GS =3V T : V B = V S = V G = 3V T V D = 2V T ; n + Further increase in V G will cause the FET to become active ;; V T V T V T V GS =V T 2V T 3V T V GS =2V T 2V T 3V T V GS =3V T 2V T 3V T Fig CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-8 Output Characteristics of an Enhancement NMOS Transistor 2 VGS = id(μa) 1 VGS = 2.5 SPICE Input File: Output Characteristics for NMOS M1 6 1 MOS1 w=5u l=1.u VGS M2 6 2 MOS1 w=5u l=1.u VGS M3 6 3 MOS1 w=5u l=1.u VGS M4 6 4 MOS1 w=5u l=1.u VGS VGS = 2. VGS = 1.5 VGS = vds (Volts) Fig M5 6 5 MOS1 w=5u l=1.u VGS VDS 6 5.model mos1 nmos (vto=.7 kp=11u +gamma=.4 +lambda=.4 phi=.7).dc vds 5.2.print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).end CMOS Analog Circuit Design P.E. Allen - 21

5 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-9 Transconductance Characteristics of an Enhancement NMOS Transistor V DS = 4V V DS = 3V V DS = 5V id(μa) V DS = 2V V DS = 1V SPICE Input File: Transconductance Characteristics for NMOS M1 1 6 MOS1 w=5u l=1.u VDS M2 2 6 MOS1 w=5u l=1.u VDS M3 3 6 MOS1 w=5u l=1.u VDS M4 4 6 MOS1 w=5u l=1.u VDS v GS (Volts) Fig M5 5 6 MOS1 w=5u l=1.u VDS VGS 6 5.model mos1 nmos (vto=.7 kp=11u +gamma=.4 lambda=.4 phi=.7).dc vgs 5.2.print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).probe.end CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-1 SIMPLE LARGE SIGNAL MODEL (SAH MODEL) Large Signal Model Derivation 1.) Let the charge per unit area in the channel inversion layer be QI(y) = -C ox [v GS -v(y)-v T ] (coul./cm2 ) 2.) Define sheet conductivity of the inversion layer per square as S = μ o Q I (y) cm2 coulombs v s cm2 = amps volt = 1 /sq. 3.) Ohm's Law for current in a sheet is JS = W = - dv SEy = -S dy dv = - SW dy = - dy μ o Q I (y)w 4.) Integrating along the channel for to L gives L dy = - W μ o Q I (y)dv = W μ o C ox [v GS -v(y)-v T ]dv 5.) Evaluating the limits gives v(y) n + n + y dy p Source Drain - yy+dy L dy = -Wμ o Q I (y)dv id = W μ oc ox L (vgs-vt)v(y)- v 2(y) 2 id= W μ oc ox L (vgs-vt)vds- 2 2 CMOS Analog Circuit Design P.E. Allen - 21 v GS + - id + - v D Fig.11-3

6 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-11 Saturation Voltage - V DS (sat) Interpretation of the large signal model: = v GS -V T Active Region Saturation Region Increasing values of v GS The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the inverted parabolas. d d = μ oc ox W L [(v GS -V T ) - ] = (sat)=v GS -V T Useful definitions: μ o C ox W L = K W L = Fig Cutoff Saturation Active = v GS - V T v GS V T Fig CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-12 The Simple Large Signal MOSFET Model Regions of Operation of the MOS Transistor: 1.) Cutoff Region: v GS - V T < = (Ignores subthreshold currents) 2.) Active Region Output Characteristics of the MOSFET: < < v GS - V T = μ ocoxw 2L 2(v GS -V T )- 3.) Saturation Region < v GS - V T < μ o CoxW id = 2L v GS -V T /I D.5 Active Region = v GS -V T Saturation Region Channel modulation effects.25 Cutoff Region v GS -V T V GS -V T v GS -V T V GS -V T v GS -V T V GS -V T v GS -V T V GS -V T v GS -V T = 1. =.86 =.7 =.5 = V GS -V T V GS -V T Fig CMOS Analog Circuit Design P.E. Allen - 21

7 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-13 Illustration of the Need to Account for the Influence of on the Simple Sah Model Compare the Simple Sah model to SPICE level 2: 25μA 2μA 15μA 1μA 5μA 2 K' = 44.8μA/V k =, v DS (sat) = 1.V 2 K' = 44.8μA/V k=.5, v DS (sat) = 1.V SPICE Level 2 2 K' = 29.6μA/V k =, v (sat) DS = 1.V μa (volts) V GS = 2.V, W/L = 1μm/1μm, and no mobility effects. CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-14 Modification of the Previous Model to Include the Effects of on V T From the previous derivation: L dy = - W μ o Q I (y)dv = W μ o C ox[v GS-v(y)-V T ]dv Assume that the threshold voltage varies across the channel in the following way: V T (y) = V T + kv(y) where V T is the value of V T the at the source end of the channel and k is a constant. Integrating the above gives, = W μ oc ox L (v GS -V T )v(y)-(1+k) v2 (y) 2 or = W μ oc ox L (v GS -V T ) -(1+k) v2 DS 2 To find (sat), set the d /d equal to zero and solve for = (sat), (sat) = v GS-V T 1+k Therefore, in the saturation region, the drain current is = W μ oc ox 2(1+k)L (v GS - V T )2 For k =.5 and K = 44.8μA/V2, excellent correlation is achieved with SPICE 2 CMOS Analog Circuit Design P.E. Allen - 21

8 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-15 Influence of vds on the Output Characteristics Channel modulation effect: As the value of increases, the effective L decreases causing the current to increase. Illustration: Note that L eff = L - X d Therefore the model in saturation becomes, = K W 2L eff (v GS -V T )2 S d d = - K W 2L eff 2 (v GS - V T ) 2 dl eff d = Leff dx d d Therefore, a good approximation to the influence of on is ( = ) + d d = ( = )(1 + ) = K W 2L (v GS-V T ) 2 (1+ ) B V G > V T VD > V DS (sat) ; ; L eff X d Depletion Region Fig11-6 CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-16 Channel Length Modulation Parameter, Assume the MOS is transistor is saturated- = μc oxw 2L (v GS - V T ) 2 (1 + ) Define () = when = V. () = μc oxw 2L (v GS- V T ) 2 Now, = ()[1 + ] = () + () Matching with y = mx + b gives the value of 3 () 2 () 1 () V GS3 V GS2 V GS1-1 CMOS Analog Circuit Design P.E. Allen - 21

9 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-17 Influence of Channel Length on Note that the value of varies with channel length, L. The data below is from a.25μm CMOS technology. Channel Length Modulation (V-1) NMOS PMOS Channel Length (microns) Fig.13-6 Most analog designers stay away from minimum channel length to get better gains and matching at the sacrifice of speed. CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-18 Influence of the Bulk Voltage on the Large Signal MOSFET Model The components of the threshold voltage V are: SB = : V T = Gate-bulk work function ( MS ) V BS = V V GS + voltage to change the surface potential (-2 F ) + voltage to offset the channel-bulk depletion charge (-Q b /C ox ) V SB1 > : V BS1 > V V GS + voltage to compensate the undesired interface charge (-Q ss /C ox ) We know that Q b = 2F + vbs Therefore, as the bulk becomes more reverse biased with respect to the source, the threshold voltage must increase to offset the increased channelbulk V SB2 >V SB1 : V SB2 >V SB1 : V GS depletion charge. V D > V D > V D > = CMOS Analog Circuit Design P.E. Allen - 21

10 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-19 Decreasing values of bulk-source voltage V BS = I D > v GS -V T V GS v V T V GS T1 V T2 V T In general, the simple model incorporates the bulk effect into V T by the previously developed relationship: V T (v BS ) = V T + 2 f + v BS - 2 f CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-2 Summary of the Simple Large Signal MOSFET Model Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued Bulk-Source (v BS ) influence on the transconductance characteristics- N-channel reference convention: G B Non-saturationi D = Wμ ocox v L (vgs-vt)vds- v + + DS DS 2 2 (1 + v v GS v BS DS) - - S Fig Saturationi D = Wμ ocox L (vgs-vt)vds(sat)- (sat) 2 2 (1+vDS)= W μ ocox 2L (vgs-vt) 2 (1+vDS) where: μo = zero field mobility (cm2/volt sec) Cox = gate oxide capacitance per unit area (F/cm2) = channel-length modulation parameter (volts-1) VT = VT + 2 f + vbs - 2 f VT = zero bias threshold voltage = bulk threshold parameter (volts-.5) 2 f = strong inversion surface potential (volts) For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert the current. D + CMOS Analog Circuit Design P.E. Allen - 21

11 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-21 Silicon Constants Constant Symbol V G k ni o si ox Constant Description Value Units Silicon bandgap (27 C) Boltzmann s constant Intrinsic carrier concentration (27 C) Permittivity of free space Permittivity of silicon Permittivity of SiO x x x o 3.9 o V J/K cm-3 F/cm F/cm F/cm CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-22 MOSFET Parameters Model Parameters for a Typical CMOS Bulk Process (.25μm CMOS n-well): Parameter Symbol VT K' 2 F Parameter Description Threshold Voltage (V BS = ) Transconductance Parameter (in saturation) Bulk threshold parameter Channel length modulation parameter Surface potential at strong inversion Typical Parameter Value Units N-Channel P-Channel.5± ±.15 V 12. ± 1% 25. ± 1% μa/v2.4.6 (V)1/2.32 (L=L min ).6 (L 2L min ).56 (L=L min ).8 (L 2L min ) (V) V CMOS Analog Circuit Design P.E. Allen - 21

12 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-23 SUBTHRESHOLD MODEL Large-Signal Model for Weak Inversion The electrons in the substrate at the source side can be expressed as, n p () = n po exp s V t The electrons in the substrate at the drain side can be expressed as, n p (L) = n po exp s - V t Therefore, the drain current due to diffusion is, = qad n p (L)-n p () n L = W L qxd nn po exp s V t 1-exp - where X is the thickness of the region in which flows. In weak inversion, the changes in the surface potential, s are controlled by changes in the gate-source voltage, v GS, through a voltage divider consisting of C ox and C js, the depletion region capacitance. d s dv GS = where C ox C ox +C js = 1 n s = v GS n + k 1 = v GS-V T n + k 2 k 2 = k 1 + V T n CMOS Analog Circuit Design P.E. Allen - 21 V t Poly Oxide Channel Dep. Substrate C ox C js φs v GS Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-24 Large-Signal Model for Weak Inversion Continued Substituting the above relationships back into the expression for gives, = W L qxd nn po exp k 2 V t exp v GS -V T nv t 1-exp - V t Define I t as k 2 I t = qxd n n po exp V t to get, = W L I t exp v GS -V T nv t V t where n If >, then = I W t L exp v GS -V T nv t 1+ V A The boundary between nonsaturated and saturated is found as, V ov = V DS (sat) = V ON = V GS -V T = 2nV t 1-exp - 1μA V GS =V T 1V V GS <V T Fig CMOS Analog Circuit Design P.E. Allen - 21

13 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-25 SHORT CHANNEL, STRONG INVERSION MODEL What is Velocity Saturation? The most important short-channel 15 effect in MOSFETs is the velocity saturation of carriers in the channel. 5x14 A plot of electron drift velocity versus electric field is shown below. An expression for the electron drift velocity as a function of the electric field is, v d μ n E 1+E/E c 2x14 where v d = electron drift velocity (m/s) μ n = low-field mobility (.7m2/V s) E c = critical electrical field at which velocity saturation occurs Electron Drift Velocity (m/s) 14 5x Electric Field (V/m) Fig13-1 CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-26 Short-Channel Model Derivation As before, J D = J S = W = Q I(y)v d (y) = WQ I (y)v d (y) = WQ I(y)μ n E 1+E/E i c D Replacing E by dv/dy gives, 1+ 1 E c dv dy = WQ dv I(y)μ n dy Integrating along the channel gives, L i D 1+ 1 E c dv WQI dy dy = (y)μ n dv The result of this integration is, = μ n C ox E c L W L [2(v GS-V T ) - 2] = where = 1/(E c L) with dimensions of V E E c = WQ I (y)μ n E μ n C ox W 1+ L [2(v GS-V T ) - 2] CMOS Analog Circuit Design P.E. Allen - 21

14 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-27 Saturation Voltage Differentiating with respect to and setting equal to zero gives, V DS (sat) = 1 1+2(V GS -V T -1 (V GS -V T ) 1- (V GS-V T ) 2 + if (V GS -V T ) 2 < 1 Therefore, V DS (sat) V DS (sat) 1- (V GS-V T ) 2 + Note that the transistor will enter the saturation region for < v GS - V T in the presence of velocity saturation. CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-28 Large Signal Model for the Saturation Region Assuming that (V GS -V T ) 2 < 1 gives V DS (sat) (V GS -V T ) Therefore the large signal model in the saturation region becomes, = K 2[1+(v GS -V T )] W L [ v GS - V T ]2, (V GS -V T ) 1- (V GS-V T ) 2 + CMOS Analog Circuit Design P.E. Allen - 21

15 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-29 The Influence of Velocity Saturation on the Transconductance Characteristics The following plot was made for K = 11μA/V2 and W/L = 1: id/w (μa/μm) 1 θ = θ =.2 8 θ =.4 6 θ =.6 4 θ =.8 θ = v GS (V) Fig13-2 Note as the velocity saturation effect becomes stronger, that the drain current-gate voltage relationship becomes linear. CMOS Analog Circuit Design P.E. Allen - 21 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-3 Circuit Model for Velocity Saturation A simple circuit model to include the influence of velocity saturation is shown: We know that = K W 2L (v GS -V T )2 and v GS = v GS + R SX or v GS = v GS - R XS Substituting v GS into the current relationship gives, = K W 2L (v GS - R SX -V T )2 Solving for results in, K W = 2 1+K W L R L (v GS - V T )2 SX(v GS -V T ) Comparing with the previous result, we see that = K W L R SX R SX = L K W = 1 E c K W Therefore for K = 11μA/V2, W = 1μm and E c = 1.5x16V/m, we get R SX = 6.6k. is CMOS Analog Circuit Design P.E. Allen - 21

16 Lecture 9 Large Signal MOSFET Model (3/24/1) Page 9-31 SUMMARY The modeling of this lecture is devoted to understanding how the circuit works The two primary current-voltage characteristics of the MOSFET are the transconductance characteristic and the output characteristic The simple Sah large signal model is good enough for most applications and technology The Sah model can be improved in the region of the knee and for the weak dependence of drain current on drain-source voltage in the saturation region Most designers do not work at minimum channel length because of the channel length modulation effect and because worse matching occurs for small areas The threshold voltage is increased as the bulk-source is reverse biased The subthreshold model accounts for very small currents that flow in the channel when the gate-source voltage is smaller than the threshold voltage The subthreshold current is exponentially related to the gate-source voltage Velocity saturation occurs at minimum channel length and can be modeled by including a source degeneration resistor with the simple large signal model CMOS Analog Circuit Design P.E. Allen - 21