MOS Transistors as Switches

Transcription

1 MOS Transistors as Switches G (gate) nmos transistor: Closed (conducting) when Gate = 1 (V DD ) D (drain) S (source) Oen (non-conducting) when Gate = 0 (ground, 0V) G MOS transistor: Closed (conducting) when Gate = 0 (ground, 0V) S D Oen (non-conducting) when Gate = 1 (V DD ) For nmos switch, source is tyically tied to ground and is used to ull-down signals: Out G when Gate = 1, Out = 0, (OV) when Gate = 0, Out = Z (high imedance) S For MOS switch, source is tyically tied to V DD, used to ull signals u: G S when Gate = 0, Out = 1 (V DD ) when Gate = 1, Out = Z (high imedance) Out Note: The MOS transistor is a symmetric device. This means that the drain and source terminals are interchangeable. For a conducting nmos transistor, V DS > 0V; for the MOS transistor, V DS < 0V (or V SD > 0V).

2 The CMOS Inverter Truth Table V DD I Out I Out I Out GND R in Note: Ideally there is no static ower dissiation. When "I" is fully is high or fully low, no current ath between V DD and GND exists (the outut is usually tied to the gate of another MOS transistor which has a very high inut imedance). Power is dissiated as "I" transistions from 0 1 and 1 0 and a momentory current ath exists between Vdd and GND. Power is also dissiated in the charging and discharging of gate caacitances.

3 Parallel Connection of Switches Y Y = 0, if A or B = 1 A B A + B A B Y = 1 if A or B = 0 A + B Y Series Connection of Switches Y A Y = 0, if A and B = 1 B A B A Y = 1, if A and B = 0 B A B Y

4 NAND Gate Design -tye transistor tree will rovide "1" values of logic function n-tye transistor tree will rovide "0" values of logic function Truth Table (NAND): AB A B K-ma (NAND): NAND circuit examle: Vdd P tree = A + B N tree = A B Y B A B Y A

5 NOR Gate Design -tye transistor tree will rovide "1" values of logic function n-tye transistor tree will rovide "0" values of logic function Truth Table: AB 00 1 A B K-ma: NOR circuit examle: Vdd A B P tree = A B N tree = A + B Y A B Y

6 What logic gate is this? Vdd A B Y = 1 when A B Y = 0 when A + B Y Answer: AND function, but oor design! Why? nmos switches cannot ass a logic "1" without a threshold voltage (V T ) dro. where V T = 0.7V to 1.0V (i.e., V DD G threshold voltage will vary) V DD D S V DD - V T outut voltage = 4.3V to 4.0V, a weak "1"

7 The nmos transistor will sto conducting if V GS < V T. Let V T = 0.7V, G 5V S D 0V 5V D? 0V? As source goes from 0V 5V, V GS goes from 5V 0V. When V S > 4.3V, then V GS < V T, so switch stos conducting. V D left at 5V V T = 5V 0.7V = 4.3V or V DD V T. What about nmos in series? 5V 5V 5V 5V 0V 5V 0V 4.3V 0V 4.3V 0V 4.3V 0V (V DD V T ) 5V - 0.7V 4.3V Only one threshold voltage dro across series of nmos transistors

8 For MOS transistor, V T is negative. MOS transistor will conduct if V GS > V T (V SG > V T ), or V GS < V T 0V G V T = 0.7V V GS = 0V 5V = 5V 5V S D conducting V GS < V T or V GS > V T 5V < 0.7V 5V > 0.7V How will MOS ass a "0"? G 0V When V GS < V T, sto conducting 5V 0V S D 5V? D? So when V GS < 0.7V, V D will go from 5V 0.7V, a weak "0" How are both a strong "1" and a strong "0" assed? Transmission gate ass transistor configuration When I = 1, A B B = strong 1, if A = 1; B = strong 0, if A = 0 I When I = 0, non-conducting

9 About that AND Gate... Vdd A No!!! Poorly designed AND (circuit designer fired) B Y Instead use this, A B Y Vdd Y B A

10 More Comlex Gates F = AB + CD N tree will rovide 0's, P tree will rovide 1's 0's of function F is F, F = AB + CD = AB + CD nmos transistors need high true inuts, so it is desirable for all inut variables to be high true, just as above. Y A C AB + CD B D Likewise, a Ptree will rovide 1's. F = AB + CD, need a form involving A, B, C, D Aly DeMorgan's Theorem: F = AB CD = (A + B) (C + D) A B Imlementation C D Y

11 Can also use K-mas: AB F = AB + CD CD For N tree, minimize 0's; for P tree, minimize 1's AB 0 CD N tree = AB + CD 0 AB CD P tree = A C + A D + B C + B D = A (C + D) + B (C + D) = (A + B) (C + D) 1 1 1

12 Introduction to Static Load Inverters 1) R O resistor load When I = 1, inverter dissiates static ower. I Switching oint of inverter deends on ratio of R to R ON (on resistance of nmos device. V OH = 5V, V OL close to 0V, deends on ratio R/R ON Note: outut can swing from almost 0V to 5V (V DD ) ) Again, static ower dissiation occurs when I = 1. D S O I Load is enhancement-mode nmos device. Note: outut swings from nearly 0V to (V DD V Tn ) Using a transistor as a load tends to require much less silicon area than a resistor. V OH = V DD V Tn, V OL can be close to 0V, deending on ratio of R ON of two enhancement devices

13 Deletion-mode nmos nmos device with V Tn < 0V (negative threshold voltage). Device is always conducting if V GS > 0V. 3) I D S O V GS = 0V always Load device is always on, looks like a load resistor. Dissiates static ower when I = 1 V OH = 5V; V OL nearly 0V, deending on ratio of R ON,de to R ON,enh. Deletion-mode devices were used before it was economical to ut both -tye and n-tye devices on the same die. 4) MOS device as static load S Here also the load device is always on (conducting). D O Dissiates static ower when I = 1. I V OH = 5V; V OL nearly 0V, deending on ratio of R ON, to R ON,n

14 Basic MOS Device Equations Drain Gate Bulk (or substrate for nmos device in n-well technology) Source The nmos device is a four terminal device: Gate, Drain, Source, Bulk. Bulk (substrate) terminal is normally ignored at schematic level, usually tied to ground for the nmos case. In analog alications, however, the bulk terminal may not be ignored. Gate controls channel formation for conduction between Drain and Source. Drain at higher otential than Source Source usually tied to GND to act as ull-down (nmos). Three regions of oerations first-order (ideal) equations: Cutoff region I D = 0A V GS V Tn (nmos threshold voltage) Linear region V DS I D = (V V )V GS Tn DS 0 < V DS < V GS V Tn Note: I D is linear with resect to (V GS V Tn ) only when ( V ) DS is small. Saturation region I D = ( V ) GS V T 0 < V n GS V Tn < V DS

15 Device arameters: = transistor gain factor, deendent on rocess arameters and device geometry (K n ) rocess deendent, constant = µε t ox W L under control of the designer As W/L increases, effective RON of device decreases µ = surface mobility of the carriers in the channel ε = ermittivity of the gate insulator tox = thickness of the gate insulator See Figure.5,.8 concerning µ, ε, and tox SPICE reresents by a factor given by K' = µcox = µ ε tox = KP So, K' W I D = ( V GS V T ) ; saturation region n L

16 VI characteristic I D V DS V GS boundary between linear & saturation regions (dashed line) V GS - V T = V DS V GS5 D LINEAR V GS4 V GS I SATURATION V GS3 V GS V GS1 CUTOFF V DS Things to note: In the "linear" region, ID becomes less and less linear with V GS as V DS becomes large. This is because the ( V ) DS term in the linear region grows large. Higher V GS values increase channel conductance allowing for higher values of I D for a given V DS.

17 *MOSFET Characteristics Vds 1 0 DC 10 Vgs 0 DC -.73 Vdummy 3 0 DC 0 M Mfet.MODEL Mfet NMOS(KP=3686U VTO=.30 LAMBDA=0.137).DC Vds Vgs robe.end

18 What do W and L hysically look like? nmosfet layout: Source n+ diffusion Gate (olysilicon) Drain n+ diffusion W L In digital logic, tyically will draw all transistors with the minimum gate length and vary the width. Larger W larger transconductance (more current flow for given gate voltage), higher gate caacitance During fabrication rocess, the actual width and length of the channel can be reduced by diffusion from the bulk, source, and drain into the device channel. SPICE has some MOSFET model arameters to account for this effect, LD and WD, where the actual the actual length and width is calculated as L effective = L drawn - LD W effective = W drawn - WD If LD, WD arameters not secified in the model, then SPICE assumes they are 0.

19 Ideal Inverter V out V DD switching oint V DD V in Actual Inverter Characteristics, some definitions V out (V) V OH V OL V IL V IH V in (V) V th V IL reresents the maximum logic 0 (LOW) inut voltage that will guarantee a logic 1 (HIGH) at the outut V IH reresents the minimum logic 1 (HIGH) inut voltage that will guarantee a logic 0 (LOW) at the outut

20 Noise Margin Illustration of Noise Margin: Vin Vout Inut logic 1 V DD V DD V OH Outut logic 1 NM H V IH V IL Inut logic 0 0V NM L V OL 0V Outut logic 0 Calculate noise margin using NM L = V IL - V OL NM H = V OH - V IH How do we determine V IL, V OL, V OH, and V IH? We must exam the inverter's transfer characteristic.

21 CMOS Inverter Regions of Oeration A B D E V out V out (V) 3 C I DD (A) I DD V in (V) Region A: 0 V in < V Tn MOS nonsaturated; nmos cutoff nmos is cutoff because V in < V Tn Why is the MOS device in the linear region? Linear region V SD < V SG - V T (5 5)V < (5 0)V 0.7 V 0V < 4.3V [for V DD = 5V and V T = 0.7V] Note that the MOS device can be in linear region even if I D 0A!

22 Region B: V Tn V in < V th MOS nonsaturated, nmos saturated Why is nmos saturated? Is V DSn > V GSn - V Tn? Because (V DSn = V out ) > V th and (V GSn = V in ) < V th, then V DSn > V GSn - V Tn V out > V in - V Tn [B-1] Why is MOS in linear region? It started out in linear and will remain in linear as long as V SD < V SG - V T (V DD - V out ) < (V DD - V in ) - V T V in < V out - V T [B-] V out in the above exression (Eqn. [B-]) is decreasing towards V th and V in is increasing towards V th. When Eqn. [B-] no longer holds, then the MOS device will become saturated. For the MOS device, then regions A B C corresond to linear linear saturated, resectively.

23 How can you redict the outut voltage for region B? The nmos is saturated, so I Dn = n (V V ) = in Tn n (V V ) GS n Tn The MOS is linear, so I D = ( (V V )V (V ) ) SG T SD SD I D = ( (V V V )(V V ) (V V ) ) DD in T DD out DD out Can solve for V out since I Dn = I D V DD S D D I D S GND I Dn Equivalent circuit for region B V out I Dn

24 Region C: Vin = V th MOS saturated, nmos saturated In order for nmos to be saturated, need V DSn > V GSn V Tn V out > V in V Tn In order for MOS to be saturated, need V SD > V SG V T V DD V out > V DD V in V T V out < V in + V T So Vout in region C, V in V Tn < V out < V in + V T The CMOS inverter has very high gain in region C so small changes in V in roduce large changes in V out. No closed form equation for V out. Somewhere in this region, V out = V in, which is the switching oint for this gate. Equivalent circuit for region C: V DD I D V out I Dn

25 What is V in in region C? In region C, both devices in saturation so I D = (V V V ) DD in T I Dn = n (V V ) in Tn So, using I Dn = I D, V in can be solved for (more on this later...) Region D: V th < V in V DD V T MOS saturated, nmos linear Hence, I D = (V V V ) DD in T n I Dn = ( (V V )V V ) in Tn out out Again, since I D = I Dn, we can solve for V out : V out (V in V Tn )V out + n (V DD Vin VT ) = 0 using x = b ± b 4ac a and, recognizing from above, a = 1, b = (V in V Tn ), c = n (V DD Vin VT ) we get

26 V out = (V in V Tn ) (Vin VTn ) (Vin VDD VT ). n I D Equivalent circuit for region D V out Region E: V in > V DD V T MOS is cutoff, nmos is linear mode Since V SG = V DD V in (< V T ), V out 0V due to nmos acting as ull-down while MOS in cutoff.

27 CMOS Inverter Transfer Characteristic 5 A B D E V out V out (V) 3 C I DD (A) I DD Analysis: V in (V) V OH : V in < V Tn, the nmos transistor is in cutoff while the MOS transistor is turned-on (inversion layer established). The result is V OH V DD. V OL : (V DD Vin) < V T, the MOS is in cutoff while the nmos is on and roviding a conduction channel to ground. Hence, V OL 0V. V IL : Inut low voltage, here the nmos transistor is saturated and the MOS is nonsaturated. Equating the currents rovides n (V V ) = ( (V V V )(V V ) (V V ) ). IL Tn DD IL T DD out DD out

28 V IL : (continued) Since two unknowns exist, V in = V IL and V out, a second equation is needed. Use the unity-gain condition to obtain this second equation, ( I / V ) ( I dv out Dn in D = dvin ( I / V ) D out / V in ) = 1, rovides V IL 1 + n = V out + n V Tn V DD V T. Now the two equations needed to solve for V IL and V out exist. V IH : Inut high voltage, here the nmos is nonsaturated and the MOS is saturated. Equating the drain currents yields n ( (VIH VTn )Vout Vout ) = (V DD VIH VT ), the first of two equations needed to solve two unknowns, V in = V IH and V out. Use the unity-gain condition to get the second, ( I / V ) ( I dv out D in Dn = dvin ( I Dn/ Vout ) / V in ) = 1. This rovides V IH + 1 = V out + V Tn + (VDD VT ), n n the second equation needed to solve for the two unknowns.

29 V th : At the CMOS inverter's switching oint, or inverter threshold, V th = V in = V out and both the MOS and nmos transistors are saturated. Again, equating the drain currents, n (V V ) = th Tn (V V V ) DD th T is obtained which can be easily solved to rovide V th, V th = V Tn + n 1 + (V DD n V T ) Note: switching oint of gate (V th ) is V DD -ifn = 1 and VTn = V T. So, switching oint of inverter is function of the ratio of the nmos/mos gains and the threshold voltages of the nmos, MOS transistors.

30 β n /β Ratio The n (gain of nmos) / (gain of MOS) ratio determines the switching oint of the CMOS inverter. V out (V) 5 4 Equal ull-u/ull-down "strength" Strong ull-u 3 n = 10 n = 1 n = Strong ull-down VDD V in (V) Switching oint = V DD / if n / = 1 and V Tn = V T

31 Recall that = µε W tox L. If we assume that the nmos and MOS transistors have equal W/L ratios, then µnε Wn tox Ln n = µε W tox L = µ n µ In silicon, the ratio µn/µ is usually between to 3. = electron mobility hole mobility. This means, that if then L n = L, W must be to 3 times Wn in order for n =. V out if W L = W n L n because n > V DD V in

32 Calculate the switching oint of a static load inverter as function of n/: In region C, already know nmos device is saturated from revious analysis. V DD V out V in For MOS to be saturated need: V SD > V SG V T V DD V out > V DD 0V V T V out < V T Not true!!! V DD (If V out in region C is about and V T (tyically this is true)) V DD > MOS must be in linear region

33 Then I n D n = (VGSn VTn ) = n (V in VTn ) and ID = ( (VSG VT )VSD VSD ) I ( (V V )(V V ) (V V ) D = DD T DD out DD out ) Equate I Dn = I D and solve for V out. V Can also solve for n/, out = VT (VDD VT ) n + (Vin VTn ) n (V = DD V T (V ) in (V V out Tn) V T )

34 Consider again n (V = DD V T (V ) in (V V out Tn) V T ) for the seudo-nmos inverter. Let V T = V Tn = 0.V DD and V in = V out = V DD. Then, for VDD = 5V, n 6.1!!! Note that this is very different result from the CMOS inverter case! If V DD = 3.3V, but the value of V Tn = V T is unchanged (i.e., 1V in the above examle), then n 11.5 for a switching oint equal to V DD. The n / ratio deends on the absolute value of V DD! This means that the oeration of the seudo-nmos inverter will NOT scale with V DD (for a given CMOS technology). For the CMOS inverter, the n / ratio for a switching oint of V DD / is indeendent of V DD so its oeration will scale with suly voltage. This is a another big advantage of CMOS technology. Not unusual for static CMOS circuits to oerate over a very large range of ower suly voltages, i.e.,.0v to 6.0V is common.