Master/Slave Flip Flops Page 1
A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave is on) But never both at the same time Page 2
FF Timing Gate 1 Gate GATE Master Loads Slave Loads Master Loads Slave Loads Master Loads Slave Loads Gate 1 time Page 3
Output Changes in Response to Falling Clock Gate 1 Gate GATE Master Loads Slave Loads Master Loads Slave Loads Master Loads Slave Loads 1 time Page 4
FF etailed Schematic Master latch () Usually call the gate Slave latch (SR) Page 5
A Falling Edge Triggered FF Edge-triggered Falling edge triggered Page 6
Oscillator (Toggle Circuit) Operation time Page 7
Rising Edge Triggered FF Schematic Edge-triggered Rising edge triggered Page 8
Oscillator (Toggle Circuit) Operation time Page 9
Flip Flop Transition Table + 0 0 0 0 1 0 1 0 1 1 1 1 + = No clock shown since it is edge triggered (assumed) Page 10
Falling vs. Rising Edge Triggered fall rise fall rise Page 11
Alternative Flip Flops T JK Page 12
Toggle Flip Flop T + T T 0 0 0 0 1 1 1 0 1 1 1 0 No Action Toggle + = T + T = T + Clock edge is assumed in this transition table Page 13
Toggle Flip Flop T + T T 0 0 0 0 1 1 1 0 1 1 1 0 No Action Toggle + = T + T = T + An oscillator with an enable input (T) T Page 14
Toggle Flip Flop T Page 15
JK Flip Flop J K + J K J K 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 No Change Reset Set Toggle Kind of a cross between a SR FF and a T FF + = K + J Page 16
JK Flip Flop J K Page 17
Why Alternative FF s? With discrete parts (TTL family) JK or T FF s could reduce gate count for the input forming logic Extensively used With VLSI IC s and FPGA s JK or T FF s must be built from FF+gates Larger, slower than a FF Not used Page 18
Flip Flops With Additional Control Inputs Page 19
What is this???? Page 20
What is this? Enable A falling edge triggered, -type FF with enable Master only loads when =Enable= 1 Page 21
What is this???? Page 22
What is this? Set A falling edge triggered, -type FF with an asynchronous set If Set=1 then =>1, regardless of or Page 23
What is this???? Page 24
What is this? Set A falling edge triggered, -type FF with a synchronous set If Set=1 then =>1 on the next falling edge of the clock, regardless of Page 25
Flip Flops With Additional Control Inputs A variety of FF s have been made over the years They contain combinations of these inputs: Enable Set Reset The Set and Reset can be either: Asynchronous (independent of ) Synchronous (work only on edge) Page 26
Flip Flop Timing Characteristics Page 27
Clock-to- Time (t ) t = t NOT + t AN + 2 x t NOR Why 2 x t NOR? The output does not change instantaneously Page 28
t t time Page 29
Setup Time (t setup ) t setup = t NOT + t AN + 2 x t NOR The input has to get there early enough to set the master latch before the clock turns off Page 30
t setup t setup time Page 31
Rising Edge FF Setup Time (t SETUP ) Same setup time as before Clock is delayed through the NOT gate Page 32
t setup-old time Page 33
dly t not t setup-old t setup-old time Page 34
new dly t not t setup-old t setup-old time Page 35
new dly t setup t setup-old time Page 36
Falling Edge Hold Time (t hold ) t hold = 0ns (AN gates turn off immediately) You have to keep the old value there until the AN gates are shut off (but no longer) Page 37
Rising Edge Hold Time (t hold ) t hold = t NOT You have to keep the old value there until the AN gates are shut off Page 38
t hold t hold = t NOT Clock edge AN gate turns off, can now change time Page 39
Flip Flop Timing t hold t setup t time Page 40
Timing of a Synchronous System Input Input Forming Forming Logic Logic t CYCLE >= t + t IFL + t SETUP t t IFL t SETUP time Page 41
Example of a Synchronous System 4 +1 Circuit 4 4 One transition per clock edge CNT = 0000 0001 0010 0011 0100 1111 0000 Page 42