Lecture 10: Sequential Circuits

Save this PDF as:

Size: px
Start display at page:

Download "Lecture 10: Sequential Circuits"

Transcription

1 Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004

2 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing q Two-Phase Clocking Slide 2

3 Sequencing q Combinational logic output depends on current inputs q Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in CL out CL CL Finite State Machine Pipeline Slide 3

4 Sequencing Cont. q If tokens moved through pipeline at constant speed, no sequencing elements would be necessary q Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses q This is called wave pipelining in circuits q In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. Slide 4

5 Sequencing Overhead q Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. q Inevitably adds some delay to the slow tokens q Makes circuit slower than just the logic delay Called sequencing overhead q Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Slide 5

6 Sequencing Elements q Latch: Level sensitive a.k.a. transparent latch, latch q Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register q Timing iagrams Transparent Opaque Edge-trigger (latch) Latch Flop (flop) Slide 6

7 Sequencing Elements q Latch: Level sensitive a.k.a. transparent latch, latch q Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register q Timing iagrams Transparent Opaque Edge-trigger (latch) Latch Flop (flop) Slide 7

8 Latch esign q Pass Transistor Latch q Pros + Tiny + Low clock load q Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s Slide 8

9 Latch esign q Transmission gate + No V t drop - Requires inverted clock Slide 9

10 Latch esign q Inverting buffer + Restoring + No backdriving + Fixes either X Output noise sensitivity Or diffusion input Inverted output Slide 10

11 Latch esign q Tristate feedback + Static Backdriving risk X q Static latches are now essential Slide 11

12 Latch esign q Buffered input + Fixes diffusion input + Noninverting X Slide 12

13 Latch esign q Buffered output + No backdriving X q Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading Slide 13

14 Latch esign q atapath latch + Smaller, faster - unbuffered input X Slide 14

15 Flip-Flop esign q Flip-flop is built as pair of back-to-back latches X X Slide 15

16 Enable q Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 0 Latch Latch en en en Flop 1 0 en Flop Flop en Slide 16

17 Reset q Force output low when reset asserted q Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Reset Asynchronous Reset reset reset reset reset reset reset Slide 17

18 Set / Reset q Set forces output high when enabled q Flip-flop with asynchronous set and reset reset set reset set Slide 18

19 Sequencing Methods q Flip-flops q 2-Phase Latches q Pulsed Latches Flip-Flops Flop T c Combinational Logic Flop 2-Phase Transparent Latches Pulsed Latches 1 2 p Latch t pw p Latch T c /2 Combinational Logic t nonoverlap Latch Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 t nonoverlap Latch p Latch Slide 19

20 Timing iagrams Contamination and Propagation elays t pd Logic Prop. elay A Combinational Logic Y A Y t cd t pd t cd t pcq t ccq Logic Cont. elay Latch/Flop Clk- Prop elay Latch/Flop Clk- Cont. elay Flop t setup t hold t pcq t pdq Latch - Prop elay t ccq t pcq t setup t hold Latch - Cont. elay Latch/Flop Setup Time Latch/Flop Hold Time Latch t setup t hold t t ccq pcq t cdq t pdq Slide 20

21 Max-elay: Flip-Flops t pd ( ) Tc sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 Slide 21

22 Max-elay: Flip-Flops ( setup ) tpd Tc t + tpcq sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 Slide 22

23 Max elay: 2-Phase Latches ( ) tpd = tpd1+ tpd 2 Tc sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 Slide 23

24 Max elay: 2-Phase Latches ( 2 ) tpd = tpd1+ tpd 2 Tc tpdq 123 sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 Slide 24

25 Max elay: Pulsed Latches t pd ( ) Tc max sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p t pcq tpd tsetup T c t pw 1 (b) t pw < t setup 2 Slide 25

26 Max elay: Pulsed Latches ( setup ) tpd Tc max tpdq, tpcq + t tpw sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p t pcq tpd tsetup T c t pw 1 (b) t pw < t setup 2 Slide 26

27 Min-elay: Flip-Flops 1 t CL cd F1 2 F2 1 t ccq t cd 2 t hold Slide 27

28 Min-elay: Flip-Flops 1 t t t CL cd hold ccq F1 2 F2 1 t ccq t cd 2 t hold Slide 28

29 Min-elay: 2-Phase Latches t t cd1, cd 2 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold Slide 29

30 Min-elay: 2-Phase Latches t t t t t cd1, cd 2 hold ccq nonoverlap 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2! 1 t nonoverlap 2 t ccq 1 t cd 2 t hold Slide 30

31 Min-elay: Pulsed Latches p tcd 1 CL L1 Hold time increased by pulse width 2 p L2 p t pw t hold 1 t ccq t cd 2 Slide 31

32 Min-elay: Pulsed Latches tcd thold tccq + t 1 pw CL p L1 Hold time increased by pulse width 2 p L2 p t pw t hold 1 t ccq t cd 2 Slide 32

33 Time Borrowing q In a flop-based system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges q In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle Slide 33

34 Time Borrowing Example (a) Latch Combinational Logic Latch Combinational Logic Latch Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Latch Combinational Logic Latch Combinational Logic Loops may borrow time internally but must complete within the cycle Slide 34

35 How Much Borrowing? 2-Phase Latches T borrow c setup + nonoverlap ( ) t t t L1 1 2 Combinational Logic 1 L2 2 1 Pulsed Latches 2 T c t nonoverlap t t t borrow pw setup T c /2 Nominal Half-Cycle 1 elay t borrow t setup 2 Slide 35

36 Clock Skew q We have assumed zero clock skew q Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing Slide 36

37 Skew: Flip-Flops ( setup skew ) tpd Tc tpcq + t + t t t t + t cd hold sequencing overhead ccq skew 1 F1 1 t pcq Combinational Logic T c t pdq 2 t setup F2 t skew 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd Slide 37

38 Skew: Latches 2-Phase Latches ( 2 ) tpd Tc tpdq 123 sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew 2 T t t + t + t 2 ( ) c borrow setup nonoverlap skew Pulsed Latches cd hold pw ccq ( setup skew ) tpd Tc max tpdq, tpcq + t tpw + t t t + t t + t ( ) t t t + t sequencing overhead skew borrow pw setup skew Slide 38

39 Two-Phase Clocking q If setup times are violated, reduce clock speed q If hold times are violated, chip fails at any speed q In this class, working chips are most important No tools to analyze clock skew q An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times q Call these clocks 1, 2 (ph1, ph2) Slide 39

40 Safe Flip-Flop q In class, use flip-flop with nonoverlapping clocks Very slow nonoverlap adds to setup time But no hold times q In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 2 1 X Slide 40

41 Summary q Flip-Flops: Very easy to use, supported by all tools q 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing q Pulsed Latches: Fast, some skew tol & borrow, hold time risk Slide 41

Lecture 11: Sequential Circuit Design

Lecture 11: Sequential Circuit Design Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current

More information

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating

More information

Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay

More information

Sequential Circuit Design

Sequential Circuit Design Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines

More information

Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems

Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH

More information

Weste07r4.fm Page 183 Monday, January 5, 2004 1:39 AM. 7.1 Introduction

Weste07r4.fm Page 183 Monday, January 5, 2004 1:39 AM. 7.1 Introduction Weste07r4.fm Page 183 Monday, January 5, 2004 1:39 AM 7 7.1 Introduction The previous chapter addressed combinational circuits in which the output is a function of the current inputs. This chapter discusses

More information

Lecture 7: Clocking of VLSI Systems

Lecture 7: Clocking of VLSI Systems Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 Two-Phase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10 - Clocking Note: The analysis

More information

Latch Timing Parameters. Flip-flop Timing Parameters. Typical Clock System. Clocking Overhead

Latch Timing Parameters. Flip-flop Timing Parameters. Typical Clock System. Clocking Overhead Clock - key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where

More information

Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology

Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter

More information

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1 ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

More information

Timing Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency

Timing Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012 Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

More information

Introduction to CMOS VLSI Design

Introduction to CMOS VLSI Design Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, Addison-Wesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration

More information

Sequential Logic Design Principles.Latches and Flip-Flops

Sequential Logic Design Principles.Latches and Flip-Flops Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch

More information

Lecture 10: Latch and Flip-Flop Design. Outline

Lecture 10: Latch and Flip-Flop Design. Outline Lecture 1: Latch and Flip-Flop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flip-flops

More information

CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

More information

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit - FSM A Sequential circuit contains: Storage

More information

Sequential Logic: Clocks, Registers, etc.

Sequential Logic: Clocks, Registers, etc. ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design

More information

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1 WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits

More information

Lecture-3 MEMORY: Development of Memory:

Lecture-3 MEMORY: Development of Memory: Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,

More information

Memory Elements. Combinational logic cannot remember

Memory Elements. Combinational logic cannot remember Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

More information

Flip-Flops, Registers, Counters, and a Simple Processor

Flip-Flops, Registers, Counters, and a Simple Processor June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

More information

Master/Slave Flip Flops

Master/Slave Flip Flops Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

More information

路 論 Chapter 15 System-Level Physical Design

路 論 Chapter 15 System-Level Physical Design Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS

More information

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present

More information

Chapter 2 Clocks and Resets

Chapter 2 Clocks and Resets Chapter 2 Clocks and Resets 2.1 Introduction The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due

More information

Design Verification & Testing Design for Testability and Scan

Design Verification & Testing Design for Testability and Scan Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing

More information

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements

More information

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop

More information

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on

More information

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

More information

Topics. Flip-flop-based sequential machines. Signals in flip-flop system. Flip-flop rules. Latch-based machines. Two-sided latch constraint

Topics. Flip-flop-based sequential machines. Signals in flip-flop system. Flip-flop rules. Latch-based machines. Two-sided latch constraint Topics Flip-flop-based sequential machines! Clocking disciplines. Flip-flop rules! Primary inputs change after clock (φ) edge.! Primary inputs must stabilize before next clock edge.! Rules allow changes

More information

Theory of Logic Circuits. Laboratory manual. Exercise 3

Theory of Logic Circuits. Laboratory manual. Exercise 3 Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices

More information

ASYNCHRONOUS COUNTERS

ASYNCHRONOUS COUNTERS LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

More information

Class 11: Transmission Gates, Latches

Class 11: Transmission Gates, Latches Topics: 1. Intro 2. Transmission Gate Logic Design 3. X-Gate 2-to-1 MUX 4. X-Gate XOR 5. X-Gate 8-to-1 MUX 6. X-Gate Logic Latch 7. Voltage Drop of n-ch X-Gates 8. n-ch Pass Transistors vs. CMOS X-Gates

More information

CSE140: Components and Design Techniques for Digital Systems

CSE140: Components and Design Techniques for Digital Systems CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic

More information

Module 3: Floyd, Digital Fundamental

Module 3: Floyd, Digital Fundamental Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

More information

Layout of Multiple Cells

Layout of Multiple Cells Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed

More information

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

More information

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

More information

7. Latches and Flip-Flops

7. Latches and Flip-Flops Chapter 7 Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The

More information

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics

PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit A Sequential circuit contains: Storage elements:

More information

Set-Reset (SR) Latch

Set-Reset (SR) Latch et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0-? 0-? Indeterminate cross-coupled Nand gates

More information

NAME AND SURNAME. TIME: 1 hour 30 minutes 1/6

NAME AND SURNAME. TIME: 1 hour 30 minutes 1/6 E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 2005-2006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June

More information

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

More information

The enable pin needs to be high for data to be fed to the outputs Q and Q bar.

The enable pin needs to be high for data to be fed to the outputs Q and Q bar. of 7 -Type flip-flop (Toggle switch) The -type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure shows how the flip-flop (latch) can be made using -input logic circuits

More information

A New Paradigm for Synchronous State Machine Design in Verilog

A New Paradigm for Synchronous State Machine Design in Verilog A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital

More information

Chapter 5. Sequential Logic

Chapter 5. Sequential Logic Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends

More information

Chapter 9 Latches, Flip-Flops, and Timers

Chapter 9 Latches, Flip-Flops, and Timers ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary

More information

Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

More information

CS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on

CS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on CS 61C: Great Ideas in Computer Architecture Finite State Machines Instructors: Krste Asanovic & Vladimir Stojanovic hbp://inst.eecs.berkeley.edu/~cs61c/sp15 1 Levels of RepresentaKon/ InterpretaKon High

More information

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE. MEDIUM SPEED OPERATION - 8MHz (typ.) @ CL = 50pF AND DD-SS = 10. MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RES-

More information

IEEE. Proof. INCREASING circuit speed is certain to remain the major. Dual-Edge Triggered Storage Elements and Clocking Strategy for Low-Power Systems

IEEE. Proof. INCREASING circuit speed is certain to remain the major. Dual-Edge Triggered Storage Elements and Clocking Strategy for Low-Power Systems TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 5, MAY 2005 1 Dual-Edge Triggered Storage Elements and Clocking Strategy for Low-Power Systems Nikola Nedovic, Member,, and Vojin

More information

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates

More information

Digital Fundamentals

Digital Fundamentals igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage

More information

S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India

S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Power reduction on clock-tree using Energy recovery and clock gating technique S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Abstract Power consumption of

More information

TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN

TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN USING DIFFERENT FOUNDRIES Priyanka Sharma 1 and Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department

More information

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

More information

Combinational Logic Design Process

Combinational Logic Design Process Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIP-FLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1

More information

Two-Phase Clocking Scheme for Low-Power and High- Speed VLSI

Two-Phase Clocking Scheme for Low-Power and High- Speed VLSI International Journal of Advances in Engineering Science and Technology 225 www.sestindia.org/volume-ijaest/ and www.ijaestonline.com ISSN: 2319-1120 Two-Phase Clocking Scheme for Low-Power and High- Speed

More information

EE552. Advanced Logic Design and Switching Theory. Metastability. Ashirwad Bahukhandi. (Ashirwad Bahukhandi) bahukhan@usc.edu

EE552. Advanced Logic Design and Switching Theory. Metastability. Ashirwad Bahukhandi. (Ashirwad Bahukhandi) bahukhan@usc.edu EE552 Advanced Logic Design and Switching Theory Metastability by Ashirwad Bahukhandi (Ashirwad Bahukhandi) bahukhan@usc.edu This is an overview of what metastability is, ways of interpreting it, the issues

More information

Counters & Shift Registers Chapter 8 of R.P Jain

Counters & Shift Registers Chapter 8 of R.P Jain Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without

More information

CS311 Lecture: Sequential Circuits

CS311 Lecture: Sequential Circuits CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce

More information

Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle.

More information

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012 Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Register File, Finite State Machines & Hardware Control Language

Register File, Finite State Machines & Hardware Control Language Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework

More information

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation

More information

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse. DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting

More information

ECE124 Digital Circuits and Systems Page 1

ECE124 Digital Circuits and Systems Page 1 ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly

More information

Admin. ECE 550: Fundamentals of Computer Systems and Engineering. Last time. VHDL: Behavioral vs Structural. Memory Elements

Admin. ECE 550: Fundamentals of Computer Systems and Engineering. Last time. VHDL: Behavioral vs Structural. Memory Elements Admin C 55: Fundamentals of Computer ystems and ngineering torage and Clocking eading Finish up Chapter ecitation How is it going? VHL questions/issues? Homework Homework ubmissions vis akai C 55 (Hilton):

More information

EE411: Introduction to VLSI Design Course Syllabus

EE411: Introduction to VLSI Design Course Syllabus : Introduction to Course Syllabus Dr. Mohammad H. Awedh Spring 2008 Course Overview This is an introductory course which covers basic theories and techniques of digital VLSI design in CMOS technology.

More information

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock 74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops

More information

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the

More information

TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING

TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and

More information

Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

More information

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters: Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS

More information

Asynchronous Counters. Asynchronous Counters

Asynchronous Counters. Asynchronous Counters Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter

More information

Counters and Decoders

Counters and Decoders Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

More information

Wiki Lab Book. This week is practice for wiki usage during the project.

Wiki Lab Book. This week is practice for wiki usage during the project. Wiki Lab Book Use a wiki as a lab book. Wikis are excellent tools for collaborative work (i.e. where you need to efficiently share lots of information and files with multiple people). This week is practice

More information

IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)

IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584-640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines

More information

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users

More information

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.

More information

Clock Distribution in RNS-based VLSI Systems

Clock Distribution in RNS-based VLSI Systems Clock Distribution in RNS-based VLSI Systems DANIEL GONZÁLEZ 1, ANTONIO GARCÍA 1, GRAHAM A. JULLIEN 2, JAVIER RAMÍREZ 1, LUIS PARRILLA 1 AND ANTONIO LLORIS 1 1 Dpto. Electrónica y Tecnología de Computadores

More information

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store

More information

Decimal Number (base 10) Binary Number (base 2)

Decimal Number (base 10) Binary Number (base 2) LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013 DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,

More information

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation

More information

Sequential 4-bit Adder Design Report

Sequential 4-bit Adder Design Report UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela

More information