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1 E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June 22, 2006, from noon to 1pm Final scores: June 23, 2006 NAME AND SURNAME TIME: 1 hour 30 minutes 1 (4 min.) How does the speed of the devices change if dimensions W, L and t ox (oxide thickness) are reduced a factor in all MOS transistors of an integrated circuit? Justify the answer. 2 (3 min.) Specify the classes IP (intellectual property) cores are usually divided in. Indicate which class is the most technology-independent one. 3 (5 min.) Input R of flip-flop FF1 is asynchronous. In order to achieve a synchronous reset in FF1 with an external asynchronous signal Ra by generating the Rs synchronized signal. Does the circuit of the figure achieve this purpose? If the affirmative case, justify it, otherwise propose an alternative. Ra CK CK D Q D Q FF1 R Rs 1/6
2 4 (2 min.) Despite the size of wafers used in VLSI provide room enough to implement large-area chips (more than 50 cm 2 ) it is not common because an important technological drawback discourages it. Which one is it? Justify the answer. 5 (6 min.) Compare the delay of a buffering chain consisting of n 4-input NAND gates with n inverters, both with constant relative fanout. Data: r = 2; t e1 (inverter) = t e1 (NAND4) = 1; t p (inverter) = 1; t p (NAND4) = 2. 6 (6 min.) The Noise Margin can be defined as the minimum interference voltage that can produce an incorrect operation in a circuit. In the dynamic circuit of the figure, V DD = 2.5 V, C IN = 20 ff, C D = 4 ff. Calculate its Noise Margin assuming that the inverter switches at V DD /2. Can the Noise Margin of this circuit be improved without adding any transistor? V DD y CK C IN x 1 C D x 2 C D x3 C D 2/6
3 7 (4 min.) Draw a dynamic OR-NAND gate at transistor level. b c a y 8 (3 min.) Indicate the fundamental difference between a tri-state dynamic flip-flop and a dynamic C 2 MOS flip-flop. 9 (4 min.) Fill in the following logic comparative table for CMOS technology. Indicate the number of transistors for a n-input logic function and the input capacitance per line. Assume gate capacitance C G NMOS = C 1 and r = 2. n Static Pseudo-NMOS Domino Zipper C 2 MOS CVSL C IN 10 (4 min.) Assuming equiprobabilistic and independent inputs, calculate the transition probability of a 3-input static NAND gate. 11 (3 min.) Indicate a design style that exhibits static power consumption. 3/6
4 12 (3 min.) What kind of logic is generally preferred for low power design, static or dynamic? Justify the answer. 13 (4 min.) Does it make sense to operate with a power supply V DD value below the voltage corresponding to the minimum value of the EDP figure of merit? Justify the answer. 14 (4 min.) How can the short-circuit current be completely eliminated in CMOS? 15 (4 min.) Can area and power consumption be exchanged in CMOS circuits? How? 16 (4 min.) Briefly explain the fundamentals of DVS (Dynamic Voltage Scaling)? 17 (4 min.) What difference exists between a PG adder and a carry-lookahead adder? Is the Manchester adder a carry propagate or a carry-lookahead adder? Justify the answers. 4/6
5 18 (6 min.) Calculate area and delay of two 8-bit carry select adders, consisting of 2 and 4 carry select stages, respectively. Which one of the two adders is preferred in terms of area-delay product? Data: Full Adder area: A FA = 1; Full Adder delay: t dfa = 1; MUX area (including sum and carry): A MUX = 0,2; MUX delay t dmux = 0,5 19 (4 min.) Fill in the delay of the following 16-bit multiplies expressed in clock cycles. Parallel/ Parallel Serial/ Parallel Robertson Booth Modified Booth Radix 4 Wallace Trees Serial/ Serial 20 (4 min.) Is it correct to state that the product delay of each multiplier of the previous question is proportional to the table numbers? Justify the answer. 21 (4 min.) Briefly indicate a main similarity and a main difference of an array multiplier and a Wallace-tree multiplier. 5/6
6 22 (5 min.) Which operations has to perform a radix-4 parallel-serial multiplier if the multiplier register contains the following value? /6
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