Three-Phase Dual-Rail Pre-Charge Logic
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1 Infineon Page 1 CHES Yokohama Three-Phase Dual-Rail Pre-Charge Logic L. Giancane, R. Luzzi, A. Trifiletti {marco.bucci, raimondo.luzzi}@infineon.com {giancane, trifiletti}@die.mail.uniroma1.it
2 Summary Advantages of pre-charged dual-rail logics Some implementation issues Impact of unbalanced loads and circuit asymmetries on the actual robustness against DPA The proposed logic style (TDPL) vs a reference dual-rail logic style (SABL) Simulation testbench and results on basic gates Case study: FULLADDER Page 2
3 Application scenario: masking a state machine Busses and registers can be easily XOR-masked. Unfortunately, this does not hold for combinatorial functions that, in general, are not linear with the XOR operator. x clk XOR(s m, m) F(x, s) XOR(s, m ) REG Dual-Rail pre-charged logic is a countermeasure suitable to be transparently applied to combinatorial functions. It has also the advantage to be glitch-free. Page 3
4 Just two gates are needed for the implementation of a complete dual-rail family Basic gates AND XOR NOT NAND XNOR OR NOR Using a dynamic logic, gates are cascoded in Domino style. Therefore, different fanouts can be simply obtained by using a suitable pair of static inverters Page 4
5 Load capacitances in a dual-rail gate The actual robustness of a dual-rail device depends on the actual balancing of its implementation. Load capacitance are the main issue, but also internal nodes are relevant. In facts, an accurate load balancing requires a full custom design flow (i.e. manual or semi-manual routing and a large amount of post-layout simulations). Page 5
6 Effect of unbalancing of complementary wires d(t) = X 1 (t) " X 0 (t) " X 0 X 0 (t) d(t) X 1 (t) " X 1 A DPA peak appears when a set X of traces is partitioned on two sets X 0 and X 1 in such a way their averages can be distinguished. Page 6
7 Effect of unbalancing of complementary wires (cont.) d " d is, in facts, the signal/noise ratio of a DPA peak where What does it mean? " 2 2 d = " X " X 1 and " X i = " X i N i As an example: a 5% unbalanced dual-rail will feature only a 1/20 attenuation and could be attacked, using 400*N traces, the same as a single rail using N traces....and 5% is a quite optimistic unbalancing estimation. Page 7
8 How can we make the energy consumption of the circuit balanced? Normally, both rails are pre-charged, but only one is discharged during the evaluation phase. z z z z evaluation 0 1 pre-charge The problem comes from the fact that the energy consumption depends on which wire (or internal node) switches. Page 8
9 Three-phase dual-rail In order to balance energy consumption we can simply make both the wires switch by adding a discharge phase. Page 9 z z z z evaluation 0 1 discharge pre-charge As a matter of fact, we can notice that now the information is not anymore on which wire switches, but on when wire switches (i.e. we use a sort of phaseencoding).
10 The proposed logic style (inverter) Page charge: outputs are pre-charged to VDD via P 1, P 2, P 5 ; 2. evaluation: N 7 is closed thus discharging one of the outputs via the pull down circuit (N 5, N 6 ) according on the input lines; 3. discharge: the additional pull down N 1, N 3, discharges the output line that was not discharged during the evaluation phase.
11 SABL vs TDPL SABL inverter TDPL inverter In TDPL, two additional pull-downs NMOS (N 1, N 4 ) and a PMOS switch (P 1 ) are added in order to implement the discharge phase. Page 11
12 Other gates in TDPL As in SABL, gates differ only in the pull-down circuit. AND XOR Page 12 Notice that, being a dual-rail logic, the AND gate is actually a universal gate (AND, NAND, OR, NOR).
13 Simulation testbench (TDPL vs SABL) Process: Infineon 0.12m, 1.5V supply voltage; Transistor sizes: W = 0.68m; L = 0.12m; Simulation: Spectre/BSIM3v3. Since power consumption mainly depends on transitions, all possible input transitions have been simulated. Page 13
14 NAND current traces for all input transitions: SABL vs TDPL + non constant constant + Page 14
15 Simulation results for the three basic gates NED = max(e) " min(e) max(e) NSD = " E E Page 15
16 Case study: TDPL vs SABL Full Adder Dual-rail FULLADDER based on XOR and NAND gates cascaded using a Domino logic (static inverters). Notice that, in TDPL, static inverters do not cause unbalanced energy consumption since, as the connection wires, each inverter switches the same number of times. Page 16
17 FULLADDER current traces: SABL vs TDPL Page 17
18 Simulation results for the FULLADDER (8x8) traces related to all possible input transitions each gate is unbalanced as shown in the previous testbench Page 18 NSD improvement over 25 times power consumption increasing about 50%
19 Balanced vs unbalanced TDPL Balanced and unbalanced TDPL behave almost the same: i.e. the goal to avoid full-custom layout seems to be achieved C BALANCED [pq] C UNBALANCED 10% [pq] 0,1761 0,1836 0,1761 0,1836 0,1764 0,1839 0,1764 0,1839 0,1761 0,1836 0,1761 0,1836 0,1764 0,1839 0,1764 0,1839 0,1764 0,1839 0,1764 0,1839 0,1761 0,1836 0,1761 0,1836 0,1764 0,1839 0,1764 0,1839 0,1761 0,1836 0,1761 0,1836 C BALANCED C UNBALANCED 10% MAX 0,1764 0,1839 MIN 0,1761 0,1836 AED 0,0003 0,0003 NED 0,002 0,002 SD 0,000 0,000 NSD 0,001 0,001 Page 19 The residual leakage seems to depend on second order effects such as: - parasitics which depend on the state of adiacent nodes; - power transfer through inputs; -...
20 Conclusions DPA-resistant dual-rail logic family suitable for a semicustom design flow almost constant energy consumption even in presence of heavily asymmetric interconnections and pull-downs: about 25 times more balanced than SABL in case of a FULLADDER; in facts, the same robustness as a full-custom dual-rail logic power consumption and area penalties smaller than MDPL Page 20
21 Questions? Page 21
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