Gates. J. Robert Jump Department of Electrical And Computer Engineering Rice University Houston, TX 77251

Transcription

1 Gates J. Robert Jump Department of Electrical And Computer Engineering Rice University Houston, T The Evolution of Electronic Digital Devices Logical Operations and the Behavior of Gates Binary Variables and Logical Operations Binary-Valued Signals and Gates Gate Implementations Logic Switches Gates Gate Electrical and Timing Properties Static Gate Parameters Noise Margins Fan-Out Dynamic Gate Parameters Electronic Gate Circuits Semiconductor Properties Diodes and Transistors PN Junctions and Diodes Unipolar Transistors Bipolar Transistors Logic Families Metal-Oxide-Semiconductor Logic Complementary Metal-Oxide-Semiconductor Logic Transistor-Transistor Logic Emitter-Coupled Logic Special Gate Circuits Open-Collector Gates Tri-State Gates Schmidt Trigger Inputs...38

2 CHAPTER 2. GATES The most elementary logic elements are digital devices called gates. They are used as the basic building blocks for constructing more complex logic devices. Although there are other ways to realize a gate, the only gates to be considered are those that are implemented as electronic circuits. They are the most common gate types used by digital design engineers today. This chapter is a brief introduction to the logical, electrical, and timing properties of electronic gates. It begins in the next section with a very brief discussion of the evolution of electronic digital devices. An electronic gate is a circuit with one or more input terminals and one output terminal. The direction of information flow is from the input terminals to the output terminal. Thus, a gate can be viewed as a device that transforms input signals into output signals. The types of transformations realized by gates are the subject of Section 2. Section 3 is an introduction to the internal structure of gates. It develops an idealized model of gate structures based on a primitive device called a logic switch. While this idealized model can not account for the electrical and timing properties of gates, it is useful for explaining how the logical behavior of gates can be realized by electronic circuits. The electrical and timing properties of electronic gates determine limitations on how they can be interconnected to realize complex digital operations. These properties are discussed in general terms in Section 4, where a gate is viewed as a "black box" that can be characterized by parameters that specify the important properties of its terminal signals. These parameters are the ones needed by a design engineer to determine the physical restrictions on the interconnection of gates. The values of these parameters are specified by the gate manufacturer. In practice, logic switches are implemented by transistors. Moreover, some of the circuits in common use are more complex than the idealized circuits in Section 3, and several different circuit types, called logic families, have evolved to meet different application requirements. For example, a family might be characterized by low power dissipation, by high speed, or by high noise tolerance. Several of the most widely used transistor circuits and logic families are discussed in Section 5. The final section of the chapter describes some special input and output circuits that can be added to gates. These circuits are used to enhance certain electrical, timing, or logical properties of gates. 1. The Evolution of Electronic Digital Devices The first electronic gate circuits were constructed from vacuum tubes and discrete passive components such as resistors, capacitors, and inductors. A single vacuum tube gate took more space and power than one of today's microprocessors. Moreover, they were slow and inherently unreliable by today's standards. The first major improvement in gate circuits was realized when transistors were substituted for vacuum tubes. This led to smaller, faster, more reliable, and cheaper circuits that used less power. As a result, larger and more powerful digital systems could be built. A major breakthrough was initiated with the development of integrated circuits (IC's). These are not so much a new type of circuit as a new method of fabricating circuits. It was found that the same techniques that are used to fabricate transistors can also be used to fabricate passive elements and the conducting lines that interconnect all of the circuit's components. Thus, a complete gate could be fabricated in a single package called an integrated circuit. The significant advantage of IC's over discrete component circuits is a direct result of the substantial reduction in physical size that results from microelectronic fabrication techniques. They are smaller, require less power, switch faster, and are more reliable. Moreover, they are cheaper since much of the manufacturing process can now be automated. Since the introduction of integrated circuits, there has been a steady and spectacular improvement in their properties. This has resulted from improvements in the manufacturing process due to accumulated experiences and the development of new techniques, as well as the development of new types of transistors and circuits. The major

3 advances have resulted from the ability to fabricate more and more complex circuits as single devices. The first devices consisting of one to four gates are now called small scale integrated circuits (SSI). The next step was to put more gates in a package and to interconnect them to form a small digital subsystem such as an adder or a register. Devices of this level of integration are called medium scale integrated circuits (MSI). This evolution of decreasing size, cost, and power consumption, and increasing complexity, speed, and reliability has continued. Today's most sophisticated IC's, called large scale integrated circuits (LSI) and very large scale integrated circuits (VLSI) are complete 16 and 32 bit computers in single packages that cost as little as a few dollars. Although they are called microcomputers, they are "micro" in size and cost only, they are as powerful as the "giant brains" of a few years ago. While this chapter is concerned primarily with gates, MSI, LSI, and VLSI circuits are just a large number of interconnected gates packaged as a single device. The electrical and timing properties of integrated circuits are determined by the type of transistors and the type of gate circuits that are used. Hence, the general discussion of these properties given in this section is just as relevant to a VLSI circuit as it is to the circuit of a single gate. 2. Logical Operations and the Behavior of Gates This section is an introduction to the behavior of gates. In particular, it establishes a model for representing the logical properties of gates as opposed to their electrical properties. This model is based on an area of mathematical logic called the propositional calculus and the related theory of Boolean algebra. Within that theory, variables are called binary variables because they can assume only two possible values. The most basic relationships that can exist between binary variables are called logical operations. Complex relationships are constructed by combining binary variables and logical operations according to a set of rules (the axioms of the theory). Theorems derived from the basic definitions and axioms are used to establish the properties of these relationships. The goal of this section is to establish a correspondence between gates and logical operations that will enable us to use logical operations as a model for gate behavior. A gate can then be viewed as a physical realization of a logical operation. When gates are connected together to form a network, we will then be able to use the theories of the propositional calculus and Boolean algebra to model network behavior. This section deals only with the properties of gates and logical operations. Gate networks will be covered in a later chapter Binary Variables and Logical Operations A binary variable is one that can assume exactly two different values. Although any two symbols could be used to represent these values, the digits "0" and "1" are the most common choice. When referring to values of binary variables, these symbols are called bits, an abbreviation of "binary digit." Binary variables are used extensively to represent the binary-valued signals in digital systems. They are the simplest and most fundamental types of data used in these systems. Most of the other data types, such as numbers and alphanumeric characters, encountered in digital systems can be represented as combinations of several binary variables. An operation establishes a fixed relationship between some variables. It can be viewed as a function that transforms the values of one or more operand variables into values for its result variables. If its variables are binary, an operation will be called a logical operation. Logical operations can be specified (i.e., defined) by listing the results of applying the operation to all possible values of its operands. Such a listing is usually presented in a tabular form called a truth table. To illustrate this, some of the more important logical operations are defined by the truth tables in Fig When an operation has two operands and one result, it is called a binary operation, and the symbol for the operation is usually written between its two operands. Thus = indicates that the value of the variable is equal to the result of applying the OR operation to the values of variables and. Negation is a unary operation (i.e., it has exactly one operand). Its application to a variable can be shown in either of two ways, ~ or. An operation with three or more operands is usually represented using a functional notation where its symbol (or name) is followed by the operand variables in parentheses. For example, MAJ(,,) denotes the MAJORIT operation applied to the three operands,, and.

4 ~ or MAJ(,,) Fig Important Logical Functions. There is a close correspondence between logical operations and the logical connectives of the propositional calculus. Indeed, if the bits 0 and 1 are interpreted to mean "false" and "true", respectively, then the logical operations NEGATION, AND, OR, NAND, NOR, ECLUSIVE OR, and EQUIVALENCE can be interpreted as the logical connectives of the same name. Variables in the propositional calculus are used to represent conditions. A condition is said to hold if and only if the value of its variable is "true". Logical expressions are formed by combining variables with logical connectives. Logical expressions represent compound conditions whose values ("true" or "false") are determined by the values of the variables and the meaning of the logical connectives. This is illustrated in Fig Thus, for example, if the variable A represents the condition that "two numbers x and y are equal", and variable B represents the condition that "a switch S is on", then ~A represents the condition that "x and y are not equal" A B represents the condition that "x equals y and S is on", and A B represents the condition that "x equals y or S is on". Logical Connective Example Meaning NEGATION C = ~A C holds if and only if A does not hold. AND C = A B C holds if and only if A holds and B holds. OR C = A B C holds if and only if A holds or B holds. ECLUSIVE OR C = A B C holds if and only if A or B holds, bot not both. NAND C = A B C holds if and only if it is not the case that A and B hold. NOR C = A B C holds if and only if it is not the case that either A or B holds EQUIVALENCE C = A B C holds if and only if both A and B hold or both A and B don't hold Fig. 2.2 The Meaning of the Logical Connectives. The binary logical operations defined in Fig. 2.1 are the most important because of their correspondence to the logical connectives of the propositional calculus or because they are easily implemented as electronic circuits. There are a total of 16 binary operations, one for each of the possible ways of filling in a four-row truth table. These are given below in Fig It is easy to see that there are 2 k possible ways to fill-in a k-row truth table. Thus, there are 2\S\up3(2)\S\up7(n) different logical operations of n operands. Even for small n, this number is quite large (e.g., 2\S\UP3(2)\S\up7(4) = 2 16 = 65,536 and = 2 32 = 4,294,967,296 ). This is one of the reasons that analytical techniques are needed for the synthesis of circuits that realize complex logical operations.

5 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f Symbol 0 ~ ~ 1 Fig The Binary Logical Operations Binary-Valued Signals and Gates An electronic gate is a circuit with one or more input terminals and one output terminal. The direction of information flow is from the input terminals to the output terminal. Thus, a gate can be viewed as a device that transforms input signals into output signals. This section will show that the transformations realized by gates can be represented by the logical operations introduced in Section 1. In order to establish the correspondence between logical operations and gates, it is first necessary to agree upon a representation for the binary values 0 and 1. The input and output signals of gates are voltages that can take on a range of values. For example, the signals of one popular type of gate can range between 0 and 5 volts. One way to associate binary valued variables with voltages, is to first pick a voltage value V T somewhere in the middle of the voltage range and call it the threshold voltage. Then, anytime the signal voltage is higher than V T, we say it has binary value 1; anytime it is below V T, we say it has binary value 0. This has the significant advantage that the gate does not have to detect the exact value of an input signal in order to determine its binary value. It only needs to know whether or not the signal is above or below the threshold value. Moreover, if a signal voltage generated as the output of a gate should vary slightly, it can still be properly detected as an input signal by another gate as long as the variation does not take it across the threshold voltage. In effect, we are dividing the range of all possible signal values into two regions, a high region to represent the binary value 1 and a low region to represent the binary value 0. This simplifies the physical design of gates and is one of the major factors in the high reliability and accuracy that can be realized with digital circuits. High Region V max V H Invalid Region Low Region V L V min Fig Gate Signal Regions. In practice, gates are designed so that their output signals have three identifiable regions instead of two. These regions are defined by two threshold voltages V H, the high threshold, and V L, the low threshold. They divide the possible range of signals into the three regions shown in Fig The values V max and V min are the maximum and minimum signal levels that can be generated by a gate. A signal in the range of values above V H is said to be in the high state and one in the the range below V L is in the low state. The region above V H and the one below V L are said to be valid regions and the range of values between V L and V H is said to be an invalid region. Gates are designed so that as long as all of their input signals are in a valid region, their output signals will also be in a valid region. The only time a gate will produce an output voltage in the invalid region is when its input signals change

6 causing its output signal to make a transition between the high and low regions. This separation of the two valid regions by an invalid region further improves the ability of a gate to distinguish between the high and low regions. If a gate's signals are ignored while they are changing between their high and low regions, then the state (high or low) of a gate's output signal is uniquely determined by the states of its input signals. Thus, the static behavior of a gate can be modeled by listing the state of its output signal produced by each of the possible signal configurations that could be applied to its input terminals. This listing will be called the static behavior table of the gate since it is only an approximate specification that ignores the effect of signal changes. The static behavior table for a typical two input gate is given in Fig. 2.5b. Here and are the input signals and is the output signal. GATE L L L L H H H L H H H H a. Gate. b. Static Behavior Table c. Truth Table Fig Typical Static Behavior and Truth Tables for Gates (H - High State, L - Low State) Note that if the values H and L in the tables are replaced by 1 and 0, respectively, then a truth table representation of the gate's behavior is obtained, as illustrated in Fig. 2.5c. This establishes the relationship between gates and logical operations. Indeed, if the input signals of a two input gate are represented by the binary variables and, then the output signal can be represented by a binary operation of the form " op " where "op" is the symbol for the logical operation realized by the gate. For example, the AND gate behavior can be represented by and the OR gate by. The truth tables and expressions for the standard one- and two-input gates are given in Fig Fig. 2.6 also shows the logic symbols used to represent gates in diagrams. These symbols are abbreviations for the gate circuit diagrams. The shape of a gate's logic symbol only indicates the logical operation realized by the gate. They do not give any information about the physical details of the gate circuits. Also, the shape of a gate symbol indicates the direction of information flow through the gate and which terminals are input terminals and which are output terminals. For example, when the orientation of the gates is as shown in Fig. 2.6, the input terminals are on the left and the output terminals on the right, so that information flows from left to right through the gate. The names of the two-input gates correspond to the logical operations they realize. The single-input inverter and buffer gates realize logical negation and the identity operation, respectively. A bubble on an output or input terminal of a logic symbol means that the signals on different sides of the bubble are inverted. For example, one of the symbols for a NAND gate is constructed from the symbol for an AND gate by putting an inversion bubble on its output terminal. This means that the truth table for a NAND gate can be obtained from the truth table for an AND gate by inverting the entries in the output column (i.e., replacing 0's by 1's and 1's by 0's) as shown in Fig Similarly, Fig. 2.7 also illustrates another symbol for a NAND gate, inversion bubbles on the input terminals of an OR gate symbol. It indicates that the NAND gate's truth table can also be obtained by inverting the entries in the input columns of an OR gate truth table. Note that since the rows in table Fig. 2.7d are ordered differently from the other tables, it is actually equivalent to the table in Fig. 2.7b instead of the table in Fig. 2.7c. Therefore, the two NAND gate symbols have the same truth table and are said to be logically equivalent.. A similar argument can be used to show that the two NOR gate symbols are also logically equivalent. Either symbol in Fig. 2.6e (2.6f) can be used to represent a NAND (NOR) gate. The choice of which one to use is usually based on the logical property of the gate one wants to emphasize.

7 = a. Buffer = ~ b. Inverter = = c. AND Gate d. OR Gate or or = = = = e. NAND Gate f. NOR Gate g. Exclusive OR Gate e. Equivalence Gate Fig Correspondence between Truth Tables, Logical Operations, and Gates ~ ( ) ~() ~() a. AND Gate b. NAND Gate c. OR Gate d. NAND Gate Fig Relationship between NAND, AND, and OR Gates. Gates with more than two input terminals are also available. They realize extensions of the basic two-variable logical operations to three or more variables. The logic symbols and logical operations for several three and four input gates are given in Fig The general rules for interpreting gates with more than two inputs are as follows: AND gates: OR gates: NAND gates: NOR gates: The output is true if and only if all inputs are true The output is true if and only if any one of the inputs is true The output is false if and only if all inputs are true The output is false if and only if any one of the inputs is true

8 ECLUSIVE OR gates: EQUIVALENCE gates: The output is true if and only if the number of true inputs is odd The output is true if and only if the number of true inputs is even The assignment of 1's and 0's to the high and low states of a signals can be done in two ways. The assignment of 0 to a low signal and 1 to a high signal used above is called the positive logic convention. The other possibility, called the negative logic convention, assigns 1 to low signals and 0 to high signals. In order to avoid confusion, the positive logic convention it will be used exclusively throughout these notes, unless specifically stated otherwise. One of the problems at the end of the chapter deals with the effect of using the negative logic convention and with mixing the two conventions. W W W W W W a. AND b. NOR c. ECLUSIVE OR U V W U V W U V W U V W U V W U V W d. OR e. NAND f. EQUIVALENCE Fig Truth Tables and Logic Symbols for Typical 3 and 4 input Gates.

9 3. Gate Implementations This purpose of this section is to show how gates can be realized from simple switches. We first present a model of a simple switch and discuss its properties. We then show how these switches can be used to build some of the basic gates. It is our intention to give only an idea of the logical structure of several gate circuits. Gates built from electronic switches, such as transistors, use the general structures described in this section. Therefore, the circuits presented here are a good model for describing the logical behavior of real devises. However, a much more detailed model is required to explain their physical properties such as speed of operation and power consumption Logic Switches A logic switch is a three-terminal device that is used to control the connection of two points in a circuit. One of the terminals is called the control terminal, and the other two are called data terminals. There are two possible states for a switch, closed and open. In the closed state, there is a direct connection between the two data terminals; in the open state, the two data terminals are disconnected. The state of a switch is determined by the value of its control signal and the type of the switch. The two possible types of logic switches, normally open and normally closed, are shown in Fig These names refer to the state of the switch when its control signal is 0, and the two symbols are a pictorial representation of this state. When the control signal is 1, each switch will change to the state opposite the one shown by its symbol. That is, the normally open switch will be open when its control signal is 0 and closed when it is 1. The normally closed switch will be closed if its control signal is 0 and open if it is 1. Data Data Control Control Data a. Normally Open Logic Switch Data b. Normally Closed Logic Switch Fig Logic Switches. The symbols in Fig. 2.9 represent a logic switch as a mechanical device with two contact points (the small circles) and an arm that can be moved to connect or disconnect these two points, changing the switch from one state to the other. When the arm moves towards the control terminal, a normally open switch closes and a normally closed switch opens. Therefore, the action of the switch can be viewed as follows: A control signal of value 1 exerts a force that pulls the arm of the switch towards the control terminal, while a 0 control signal exerts a force that pushes the arm away from the control terminal and back to its normal position. Ideally, a switch would have zero resistance between its data terminals in the closed state and infinite resistance in the open state. Moreover, it would switch between its two states in zero time and change directly from one resistance value to the other without assuming any intermediate values. However, this is not the case for the switches used to build real gates. They are electronic switches, usually realized from transistors, which differ in many ways from an ideal switch. They have a very small, but nonzero, resistance in the closed state and very large, but not infinite, resistance in the open state. These two values can also vary over a small range while the switch is closed or open, and can move through all intermediate values during a change from one state to the other. The time required to switch between states varies for different types of transistors and different gate circuits and can be very small (on the order of a nanosecond), but it is not zero. The primary use of the logic switch model will be to explain the logical operation of electronic gate circuits. For this purpose, the actual values of the resistances and switching times can be ignored. For a detailed analysis the internal operation of gates, it would be necessary to replace the logic switch model with a more detailed model of a transistor's behavior. Section 5 below is an introduction to how this is done.

10 3.2. Gates We now show how some simple gates can be constructed from logic switches. This section presents circuits for the inverter, NAND gates and NOR gates. It will be seen in the next chapter that any logical operation can be realized from a network composed only of NAND gates or only of NOR gates. Moreover, these gates are the ones most naturally built in many of the different technologies available today. Even though there are circuits available for the other logical operations such as AND and OR, internally, these circuits are constructed by interconnecting either NOR gates or NAND gates. Therefore, we will only discuss implementations of NOR gates, NAND gates and inverters in this chapter. The realization of other logical operations from these will be covered in the next chapter. Recall that an inverter is a gate with one input terminal and one output terminal, where the output signal is always the logical complement of the input signal. That is, the output is 1 when the input is 0, and 0 when the input is 1. Fig shows two ways we could make an inverter using logic switches. The top of each of the implementations (marked with a + symbol) is connected to a positive voltage source and the bottom is connected to ground (0 volts). a. Logic Symbol b. Passive Pullup Inverter c. Active Pullup Inverter Fig Inverter Implementations. For the passive pullup inverter, a low voltage (logic 0) on the input terminal will leave the switch open. In this case, no current will flow through the resistor and the output terminal will have the same value as the supply voltage. Hence, a low input will result in a high output (i.e., a 0 input causes a 1 output). On the other hand, if is high (logic 1), then the switch will be closed causing the output terminal to be grounded through the switch. In this case, a high input voltage (logic 1) causes a low output voltage (logic 0), and the inverter behavior is verified. In the active pullup inverter, the passive pullup resistor is replaced with a normally-closed switch. When is low, the top switch is closed and the bottom one is open. In this case, the output voltage at is equal to the supply voltage. If is high, the top switch is open and the bottom one is closed, which grounds producing a low output. Therefore, the input signal is complemented as before, and this circuit is also shown to be a valid implementation of an. NOR gates and NAND gates can be implemented in a manner similar to the inverter. For a passive pullup circuit, we need a collection of switches that will pull the output down if and only if the gate should produce a 0 output. The resistor will pull the output high whenever the switches are not pulling it low. For an active pullup circuit, we need two collections of switches, one to pull the output low to produce a 0 and one to pull it high when the output should be 1. Consider first the two-input NOR gate realized with a passive pullup. Its output should be low if either one of its inputs is high. This can be realized with two normally-open switches as shown in Fig. 2.11b. Here the gate inputs are connected to the control inputs of the two parallel switches. If the control input of either switch is 1, that switch will close and pull the output low. Only if both inputs are 0 will both switches be open allowing the resistor to pull the output high. A passive pullup NAND gate is shown in Fig. 2.11e. Here two normally-open switches are connected in series so that both must be closed (both inputs equal 1) to pull the output low. If either switch is open, the path connecting the output to ground will be broken and the output pulled high by the resistor.

11 a. NOR Gate Symbol. b. Passive Pullup NOR Gate. c. Active Pullup NOR Gate. d. NAND Gate Symbol. e. Passive Pullup NAND Gate. f. Active Pullup NAND Gate. Fig NOR and NAND Gate Implementations. Active pullup versions of the two-input NOR and NAND gates can also be built. For these we must use a set of switches to pull the output high and a different set to pull it low. A two-input NOR gate realized this way is illustrated by Fig. 2.11c. Note that the normally-open pulldown switches will pull the output low whenever either input is 1. Also, if either input is 1, the connection between the output and the positive source will be open since at least one of the series-connected, normally-closed pullup switches will be open. If both inputs are 0, then both pulldown switches are open and both pullup switches are closed, so that the output is high. A two-input NAND gate with active pullup is given in Fig. 2.11f. Here the pullup and pulldown switch structures have been reversed with series-connected switches to pull the output low when both inputs are 1 and parallel-connected switches to pull it high if either input is Gate Electrical and Timing Properties. Some of the electrical and timing properties of a gate are specified by means of parameters supplied by the gate manufacturer. This section is an introduction to the more important of these gate parameters. Other properties of gates, especially those that affect the interconnection of several gates, are a function of how the gates are used and

12 must be derived from the supplied parameters. Two of these, noise margin and fan-out, are included as illustrations of these derivations Static Gate Parameters Gate parameters vary with properties of their operating environment such as temperature and power supply voltage. Moreover, they usually vary from one gate to another due to variations in the manufacturing process. For example, the resistor values, transistor gains and other component parameters will not be exactly the same for two instances of a gate circuit, and these differences will affect the gate parameters. Instead of trying to provide exact values for the various parameters, worst case values are usually given. These specify limits on the parameter values as they vary over a range determined by realistic and conservative estimates of temperature, supply voltage, and component value variations. In effect, these worst case parameter values are guarantees of performance given by the gate manufacturer. For example, the worst case (i.e., lowest) high state output voltage of one type of gate is specified to be 2.4 volts as long as the operating temperature is between 0 degrees and 70 degrees C and the supply voltage is between 4.75 and 5.25 volts. This means that if the inputs to the gate are such as to make the output high, then the output voltage will not be lower than 2.4 volts. The main voltage parameters are illustrated on the transfer function of an inverter given in Fig For multi-input gates, Fig is typical of the transfer function between any one of its input terminals and its output terminal. Fig shows the voltage thresholds used to define the valid high and low signals regions. These regions are defined separately for input and output signals. The input thresholds are denoted V IH for the high threshold and V IL for the low threshold. The high output threshold is denoted V OH, and V OL denotes the low output threshold. A low input signal is any value below V IL and a low output signal is any value below V OL. Similarly, a high signal must be above V IH for input signals and above V OH for output signals. Note that as long as the input signal is in one of its valid regions (high or low), the output will be in a valid region. Only if the input is in the invalid region between V IL and V IH is it possible for the output to be in its invalid region between V OL and V OH. V OH - Output Signal v o V OL V IL V IH v i - Input Signal Fig Typical Voltage Parameters. As another example, consider a two-input NAND gate. A manufacturer of this gate guarantees that if both of the input voltages are above V IH, then the output voltage will be below V OL, and if one or both of the input voltages are below V IL, then the output voltage will be above V OH. These parameters do not specify the actual values of the input and output voltages, nor do they say anything about the output voltage if the input voltage is between V IL and V IH. In practice, these voltage limits are very conservative so that typical values of the actual signals are usually well above the high limits V OH and V IH and well below the low limits V OL and V IL.

13 When the output terminal of a gate is directly connected to the input terminal of another gate, the output signal of the first gate becomes the input signal of the second. Therefore, a low (high) output signal should be recognized as a low (high) input signal by other gates. For a gate input signal to be recognized as low, it must be less than V IL. All that is known about the actual value of a low gate output signal is that it is less than V OL. Hence, the gates must be designed so that V OL <V IL. A similar argument shows the V OH and V IH must be chosen so that V OH >V IH. The current required to drive a gate input is a measure of the load that gate represents on the output of a driving gate. There are two possibilities for the direction of this current. If it flows out of the driving gate then this gate is said to be a current source. If the direction of current flow is out of the driven gate, the driving gate is said to be a current sink. There are physical restrictions on the amount of current a gate can sink or source, and these limit the number of gate inputs that can be driven from a single gate output. Hence, the worst case input and output currents are important gate parameters. To determine the worst case currents, first consider the case where this current is flowing into a gate input terminal. Then, connecting this input terminal to the output of another gate will cause an increase in the current that the driving gate must source. This extra current will, in turn, cause an increased voltage drop across the pullup resistor or switch of the driving gate, resulting in a decrease in the terminal output voltage of this gate. This type of output characteristic is illustrated in Fig a. It is most detrimental when the output voltage is in the high state (i.e., greater than V OH ). Indeed, this decrease could cause the output voltage to drop below V OH. As a result, the maximum input and output currents when the input and output voltages are exactly V OH are two of the current parameters of interest. These currents are called the high level input and output currents and are denoted I IH and I OH. Thus, I IH is the maximum current that will flow into a gate input terminal when the voltage at that terminal is V OH. Similarly, I OH is the maximum current that a gate output terminal can supply when its output voltage is V OH. GATE GATE i o v o i o v o v o - Output Vol tage v o - Output Vol tage i o - Output Current i o - Output Current a. Current Sourcing. a. Current Sinking. Fig Typical Gate Output Characteristics.

14 If the current flow is out of the input terminal of the driven gate and into the output terminal of a driving gate, then it is the low level output state that determines the worst case conditions. To see this, note that increasing the output current will increase the voltage drop across the resistance of the pulldown switch thereby increasing the terminal output voltage of the driving gate. Fig. 2.13b illustrates this situation. It could cause the low level output voltage to exceed V OL. Hence, the low level output current I OL is defined as the maximum current a gate output terminal can sink when its output voltage is V OL. The low level input current I IL is the maximum current load required a single gate input terminal when its input voltage is V OL. The DC power dissipation of a gate is a measure of the amount of energy wasted by a gate while its inputs are stable. The manufacturer usually specifies the voltage and current requirements placed on the power supply by the gate. The DC power dissipation can then computed as the product of these two values. For some circuit types the supply current depends on whether the gate output is high or low. For these, the maximum supply voltage plus the maximum high state supply current and the maximum low state supply current are usually specified. In this case, it is necessary to know the ratio of time in the high state to time in the low state in order to calculate the power dissipation of a circuit. For example, if the supply voltage is 5 volts, the high state current is 2 ma, the low state current is 5.5 ma, and the gate has a 50% duty cycle (i.e., spends half its time in each state), then the maximum average power dissipation is ( ) + ( ) = mw. The power dissipated by some gates is different when they are switching than when they are stable. In this case, the total power dissipated depends on the rate at which a gate is switching between levels, and it increases as the rate is increased. For this type of circuit, the power dissipation is usually specified, by the manufacturer, as a graph of power vs. frequency Noise Margins Noise signals are unwanted signals that interfere with the operation of a circuit. They can be generated outside the circuit they affect, or by the circuit itself. Noise generated outside the circuit can be coupled into the circuit by either electromagnetic or electrostatic radiation. It could also be propagated into the circuit through the AC power lines and the power supply. For example, nearby electric motors generate power surges that can affect the voltage output level of the power supply for a circuit. Any circuit that oscillates at a high frequency (e.g., those in radios) can propagate electromagnetic energy into other nearby circuits. Noise generated inside a circuit is usually due to current changes in one part of the circuit inducing unwanted signals into another part. For example, if two wires run parallel to one another and the current in one changes, that can create a field that induces a voltage in the other. Current changes in one part of a circuit can also propagate through the power supply to other parts, since the supply voltage must go to all parts of the circuit. We will not go further into a detailed discussion of noise sources and effects. For our purposes it is sufficient to model the effect of noise as the addition of the noise signal to the valid signal. That is, if v o is the output signal of a gate and v n is a noise signal that alters v o, then the actual signal observed at the gate output would be given by v o ± v n. That is, the output signal is altered by the amount of the noise, which could either increase or decrease the output signal depending on the polarity of the noise signal and how it is coupled with the gate output signal. While no noise signal is desirable, a gate can tolerate some noise and still correctly recognize the logical value of a signal. This is one of the advantages of using a range of voltage values to represent each of the binary values, small variations in voltage do not change the binary value. The noise margin, defined below, is a measure of how much noise can be safely tolerated by a gate. Fig is a graphical illustration of the voltage parameters plotted on a common voltage scale. This figure emphasizes the relationships V OL < V IL and V OH > V IH that we have seen must hold if the output of a gate is to be used as input to another gate. The differences NM L = V IL - V OL and NM H = V OH - V IH are called the DC noise margins for the low and high states. As we have seen, the effect of noise on a gate is to change the values of the gate signals by adding or subtracting a noise component v n, so that the output signal v o is altered to v o ± v n. The value of v o is guaranteed to be lower than V OL. If this corrupted output signal is the input signal for other gates, then it will be correctly interpreted by the other gates, in spite of the noise, as long as v o + v n is less than V IL. Since V IL - v o is guaranteed to be greater than NM L, the gates can tolerate up to NM L volts of noise signal. That is, noise signals v n such that v n < NM L will be ignored by the gates. A similar argument shows that noise signals v n such that v n < NM H will also be ignored.

15 V max NM H V OH V IH NM L V IL V OL V min Fig DC Noise Margins. The DC noise margins give limits on the noise voltage that can be tolerated by a gate and are determined by the DC voltage parameters. However, they do not give any indication of the ease or difficulty with which noise of sufficient magnitude to exceed these limits can be coupled into the gate. The ability of a gate to reject noise signals is determined, to a large extent, by its dynamic properties, which will be discussed in a later section. One final comment about noise in gate circuits concerns the output impedance of the gates. Noise energy is more easily coupled into a gate circuit with high output impedance than one with a lower impedance. Thus, a gate circuit could have large DC noise margins and still be quite susceptible to noise if its output impedance is high Fan-Out Fan-out is the ability of a gate to drive more than one other gate. That is, the output signal of the driving gate is "fanned-out" to become the input signal of two or more other gates. The factors that limit the fan-out of a gate include its output current capacity, as specified by the parameters I OH and I OL, and the input current requirements of the driven gates as specified by their parameters I IH and I IL. Indeed, the sum of the currents I IH for all the gates driven by a gate must be less than the current I OH of the driving gate. Similarly, the sum of the I IL current parameters must be less than I OL for these gates. If all of the gates used in a system have the same current parameter values, then the fan-out limitation due to current considerations can be expressed by a constant integer that gives the maximum number of gate inputs that can be connected to a single gate output. It is defined as the largest integer less than or equal to min(i OH /I IH,I OL /I IL ), since I OH /I IH gives the number of gates that can be driven by a single gate if its output signal is high, and I OL /I IL is the maximum number if the output signal is low. The smaller of these two numbers is the limiting factor. Fig. 2.16a illustrates a typical fan-out calculations. Here, all the gates have equal current parameters. Each gate can source 0.5 ma in the high state and sink 20 ma in the low state. Each gate input requires 0.05 ma in the high state and 2 ma in the low state. Since 0.5/0.05 = 20/2 = 10, one of these gates can drive up to 10 others without exceeding its rated current. If the current parameters are not equal for all of the gates involved, then a separate fan-out calculation must be performed for each possible arrangement of connected gates to make sure that no gate's current rating has been exceeded. Fig. 2.16b illustrates this type of calculation. Here, the output current parameters of the driving gate are I OH = 0.4 ma and I OL = 8 ma. There are two driven gates with I IH = 0.04 ma and I IL = 1.6 ma, and three driven gates with I IH = 0.02 ma and I IL = 0.4 ma. Therefore, the current that must be supplied by the driving gate is 2(0.04)+3(0.02) = 0.14 ma in the high state and 2(1.6)+3(0.4) = 4.4 ma in the low state. Since 0.14 < I OH = 0.4 and 4.4 < I OL = 8, this arrangement is satisfactory. If the number of gates with I IL = 1.6 ma were increased from two to five, then the driving gate would be required to supply 9.2 ma in the low state which would exceed its rated capacity of 8 ma.

16 n a. Same Type Gates. b. Mixed Gate Types. Fig Fan-out Examples Dynamic Gate Parameters This section is concerned with the parameters that characterize the dynamic properties of gates. These properties characterize that behavior of a gate that is due to changes of its input and output signals. The most important dynamic property is the switching speed of a gate. It is characterized by the parameters propagation delay time (or just propagation delay) and transition delay time. Informally, the propagation delay time of a gate is the time it takes for a signal change at an input terminal to cause a signal change at the output terminal. Once an output signal has started to change, the transition delay time is the time required to complete this change. Propagation delay is defined more precisely as the time from that instant when the input signal is midway through its change to the instant when the output signal is midway through its change. The exact points on the two signal changes are somewhat arbitrarily chosen by different gate manufacturers. However, they are usually near the midpoint of the changes and they are specified in the data sheets for the gates. Fig. 2.17a illustrates this definition for a gate, such as an OR gate or AND gate, where the input and output changes are in the same direction. Fig. 2.17b shows the case where the input and output changes are out of phase, as they would be for a NAND gate or an inverter. time time v i v i v o v o t PLH t PHL t PHL t PLH a. In Phase Output. b. Out of Phase Output. Fig Propagation Delay Times. In most gates, the propagation delay for a high-to-low transition of the output signal is different from the delay associated with a low-to-high output signal change. This is indicated on data sheets and timing diagrams by specifying two delay parameters, t PLH, for a low-to-high transition, and t PHL, for a high-to-low transition. Note that the high-to-low or low-to-high designation always refers to output signal changes. For some gates, the high-to-low and low-to-high propagation delay times are nearly equal. For these, the gate manufacturer may only specify one parameter t P which is used for either type of transition.

17 v H v L time v L +0.9(v H -v L ) v L +0.1(v H -v L ) t TLH t THL Fig Transition Delay Times. The definition of transition delay time is illustrated in Figure As with propagation delay, the output transition time of a gate depends on the direction of the transition. Therefore, the high-to-low transition time t THL of a signal is defined as the time required for the signal to change from v H -0.1(v H -v L ) to v H -0.9(v H -v L ), where v H is the high level of the signal before the change, and v L denotes its low level after the change. Similarly, the low-tohigh transition time t TLH of a signal is the time required for the signal to change from v L +0.1(v H -v L ) to v L +0.9(v H - v L ). Thus, transition times are measured between the 10% and 90% points on the timing diagram of the signal change. Sometimes, t TLH is referred to as rise time and denoted t r. Also, t THL is frequently called fall time and denoted t f. The timing parameters of a gate depend on the conditions under which it is operated. For example, temperature, power supply voltage, fan-out, and the amount of capacitance a gate must drive (i.e., the capacitance as measured across the output terminals) can all affect the values of propagation delay and transition time that are observed. Therefore, when timing parameters are specified on a gate date sheet, either a worst case (i.e., maximum) time is given along with the values of supply voltage, temperature, etc., that were used in measuring this time, or the time is given as a curve plotted against the test condition parameters. One of the major factors affecting the switching speed of a gate is the time required to charge or discharge various internal and external capacitances associated with the semiconductor junctions, terminals, and wires of the gate circuits. Once a type of gate circuit has been selected, the digital system designer only has control over the external capacitance associated with a gate. The external capacitance at the output terminal of a gate can increase both the time required for output signal transitions and the gate propagation delay. This "load" capacitance is due, primarily, to two sources. First there is "stray" capacitance associated with all of the wires that are connected to the terminal. Second, there is an "input" capacitance associated with every gate input terminal. Therefore, the total capacitance at the output of a gate also depends on the number of gate inputs it is connected to. For some gate circuits the capacitive load due to gate input capacitance limits the fan-out of a gate more than the amount of current required to drive these inputs. For these gates, the propagation delay is usually specified as a curve of delay vs. output capacitive load. To determine the allowable fan-out, one has to first know the maximum gate delays that can be tolerated. Then, the maximum capacitive load can be determined from the delay vs. capacitance curve. The sum of stray capacitance plus gate input capacitances must not exceed this value. The switching speed of a gate circuit is usually proportional to the amount of power it dissipates. In fact, with many gate circuits, there is a tradeoff that can be made between their speed and power dissipation. Thus, a circuit can be designed to operate at a high speed (i.e., the delay parameters are small) at the cost of increased power consumption. Alternatively, a slower version of the circuit can be designed at a savings in power consumption. As a result, one commonly encountered measure of performance for a family of gate circuits is its speed-power product. This is obtained by multiplying the average propagation delay, the average supply current, and the recommended supply voltage. Some gates will operate correctly over a wide range of supply voltages (e.g., 5 to 15 volts). For these, both the speed and power dissipation are increased by increasing the supply voltage. This provides a convenient way to control the tradeoff between speed and power. The noise tolerance of gate circuits is also affected by the speed of those circuits in several ways. First, the propagation delay of a gate is not a "pure" delay since the output signal waveform is not necessarily an exact copy of the input signal waveform, delayed by a fixed amount. In fact, the output signal will not follow an input signal change at all unless that change persists for some minimum time. In other words, very short input pulses (e.g., 1 or 2 nanoseconds) would be filtered out by a slow gate and not seen at the gate output terminal. As a general rule, if the input signal changes from one level to the other and then back again before the output starts to respond to the

18 first change, neither change will occur at the output terminal. Therefore, a slow gate circuit (i.e., one with relatively large propagation delay) would be less susceptible to noise pulses than a faster one. On the other hand, high frequency signals are coupled more easily from one part of a circuit to another. Moreover, it is the sharp transition times of pulse signals that contribute to the high frequency components of these signals. Thus, if two gate circuits had equal propagation delays but one had longer transition times, it would be less likely to generate noise that could be easily coupled into its neighbors. That is, noise would be less of a problem for a system built with these gates than for one built from the gates with faster transition times. 5. Electronic Gate Circuits This section is a survey of the basic types of electronic gate circuits that are most commonly used in new systems today. It will not attempt a detailed analysis of the circuits, since a study of digital electronics is beyond the scope of these notes and is not necessary for understanding the system design concepts presented in the following chapters. Instead, this section will present a brief look at the electronic circuits used to realize gates, emphasizing the distinguishing properties of the different types of circuits and comparing their relative advantages and disadvantages. This is sufficient to develop some feel for the physical properties of gate circuits and to design simple digital systems. However, anyone wishing to design large and complicated systems will need to study digital electronics in much more depth in order to understand "real-world" problems encountered in the design of a sophisticated system. This is especially true when high speed systems are considered Semiconductor Properties Electronic gates use diodes and transistors as their internal switches. To understand something about how these devices work, we must first consider the material from which they are made. Early transistors were made from germanium, but the semiconductor material used for most digital circuits today is silicon. These materials are called semiconductors since they have an ability to conduct current that is somewhere between that of a conductor (e.g., a copper wire) and an insulator (e.g., rubber). Current is defined in terms of the flow of charge. In a conductor, this charge is carried by electrons that are loosely bound by the atomic structure of the material and, therefore, free to move easily through the material. An insulator is characterized by a lack of charge carriers, as all of the electrons in its atoms are tightly bound by the structure of the material and not free to move. In a semiconductor, there are more free charge carriers than in an insulator but less than in a conductor. This is due to the structure of semiconductors that that does not bind all its electrons to a given position as tightly as is done in an insulator, but does exert more force to prevent their movement than is found in a conductor. There are two mechanisms for the movement of charge in semiconductors. Negative charge is carried by free electrons as in conductors. These free electrons are created by breaking away from their normal lattice position to become mobile, leaving behind an ion that is missing an electron to complete its natural lattice structure. These positively charged locations, called holes, can also be viewed as moving when an electron is stolen from a nearby location, filling the deficiency but creating a new one at a different location. In a pure semiconductor there is one hole for every free electron. The movement of positive charge (holes) in one direction through a semiconductor has the same effect as movement of negative charge (electrons) in the opposite direction. By convention, current is said to flow in the direction of positive charge movement and opposite that of negative charge movement. The number and type of charge carriers in a semiconductor is determined by its physical composition. To create an excess of charge carriers of a given type, minute amounts (about one part in 10 5 ) of an impurity are put in the pure semiconductor. The atoms of these impurities are such that they have either one more or one fewer electron than the atoms of the semiconductor. When an impurity with one more electron is added, this electron becomes free to move about the material since it is not needed to complete the lattice structure at its original location. However, the positively charged ion it leaves behind is bound tightly to a fixed position in the material and becomes an immobile positive charge location. Over a large area the number of mobile electrons and immobile ions is equal. But, since the electrons are free to move but the ions are not, there can be regions in the material where there is an imbalance between the two.

19 The number of holes in a semiconductor is increased when an impurity with one fewer electron per atom than the host semiconductor is added. Each atom of this impurity will result in a location in the material which needs another electron to complete its natural lattice structure. These locations will try to steal an electron from a neighboring location. When this happens, the stolen electron will give the original location a net negative charge creating an immobile negative ion, and the location from which it was stolen will become a positively charged hole needing one electron to complete its lattice structure. The percentage of charge carriers and, therefore, the properties of the material can be precisely controlled in the manufacturing process. A semiconductor material with an excess of negative charge carriers is called an N-type semiconductor and one with an excess of positive charge carriers is called a P-type semiconductor. There are two fundamental types of transistors used in gate circuits, unipolar and bipolar transistors. Unipolar transistors (also called field effect transistors or FET's) are characterized by the property that current flow is made up of only one type of charge carrier, either holes or electrons but not both. Current flow in bipolar transistors is composed of the movement of both types of charge carrier, holes and electrons Diodes and Transistors The properties and the basic structure of gate circuits are determined to a great extent by the nature of the diodes and transistors from which they are constructed. It is necessary to have some understanding of the basic properties of these electronic elements in order to understand how gate circuits work. Therefore, this section will give a brief introduction to the basic properties of diodes and transistors PN Junctions and Diodes A semiconductor device contains both N- and P-type materials. As a result, it contains one or more boundaries where these two types of material meet. These boundaries, called PN junctions, play a very important role in the operation of the semiconductor devices. In Fig. 2.19a we see a typical junction between a region of N- type material and a region of P-type material. The negative charge carriers (electrons) in the N region move about randomly and occasionally reach the junction and cross over into the P region. Similarly, positive charge carriers (holes) cross from the P region to the N region. Before the two regions were brought together to from a junction, they were electrically neutral. That is, for every immobile ion trapped in the lattice structure there was a charge carrier of the opposite charge free to move around the material. When one of these charge carriers leaves its original region by crossing the junction, it leaves behind an immobile ion of the opposite charge. Once it crosses the junction, a charge carrier finds itself in a region with a lot of oppositely charged carriers with which it can combine causing both to disappear. Therefore, as holes and electrons move across a junction, there is a buildup of positively charged immobile ions in the N region near the junction and a similar buildup of a negatively charged ions near the junction in the P material. Since like charges repel, these charges buildup an electric field E which prevents further flow of mobile carriers across the junction. This is illustrated as the charge barriers in Fig. 2.19b. PN Junction P N a. Creation of a PN Junction. Charge Barriers P N E b. Charge Barriers at a PN Junction. Fig PN Junction. Now, if the two regions are connected to a battery (or other voltage source) as shown in Fig. 2.20a, the electric field due to the charge buildup at the junction is reduced by the electric field produced by the battery. This allows the mobile charge carriers to start diffusing across the junction again. The battery also removes electrons

20 from the P region and inserts them in the N region, which prevents the charge barrier from building back up and stopping the movement of carriers. In this case the junction is said to be forward-biased. The resistance due to the charge barriers at the junction is reduced as the magnitude of the battery voltage is increased. This is a nonlinear effect as shown in Fig. 2.20c. In fact, the charge flow is exponentially related to the voltage applied to the junction, so that the charge flow changes from almost none to a very large amount very quickly and for a relatively small change in applied voltage. As a result, we can identify two threshold points on the curve in Fig. 2.20c that characterize the behavior of the junction. When the junction voltage is below the first threshold V off, there is essentially no charge flow, and we say that the junction is cutoff. When the junction voltage exceeds the second threshold V on, there is substantial charge flow, and the junction is said to be conducting. For typical silicon semiconductor junctions, V off is about 0.65 volts and V on is about 0.75 volts. Also note that the voltage across the junction is limited to about 0.8 volts. For most switching circuit applications, we are not interested in the region between the two thresholds. If the battery terminals are reversed as shown in Fig. 2.20b, then the battery will strengthen the charge barriers and make it more difficult for charge carriers to move across the junction. The junction is now said to be reverse-biased. In this case there is still some movement of charge carriers across the junction, but it is primarily due to the electric field of the battery pushing free electrons from the P region to the N region and holes from the N to the P region. These are thermally generated holes and electrons that result from electrons breaking away from an atom of the base semiconductor material and are not due to the impurity atoms. Since the number of these holes and free electrons is very small compared to the number of impurity atoms, this reverse charge flow is also very small. + P N Holes Electrons a. Forward-Biased Junction P N b. Reverse-Biased Junction. Charge Flow V on V off c. Junction Behavior. Junction Voltage V Fig Conduction Through a PN Junction. A diode is just a single PN junction with a terminal connected to each of the regions. The N region is called the cathode and the P region the anode. This is shown in Fig. 2.21a, and the symbol used to represent it on circuit diagrams is shown in Fig. 2.21b. The current that flows through a reverse-biased diode is much smaller than the current through a forward-biased diode. For many applications it is sufficient to assume that this reverse current is zero compared to the forward current. Under this assumption, a diode will only conduct current in one direction, from the P region to the N region, and only when it is forward-biased. This direction is indicated by the arrowhead in the diode symbol. Anode P N Cathode Anode b. Diode Symbol Cathode a. Diode Structure. Fig Semiconductor Diode.